The i.MX8M Plus Media Applications Processor is part of the growing
mScale family targeting the consumer and industrial market. It brings
an effective Machine Learning and AI accelerator that enables a new
class of applications. It is built in Samsung 14LPP to achieve both
high performance and low power consumption and relies on a powerful
fully coherent core complex based on a quad core ARM Cortex-A53 cluster
and Cortex-M7 low-power coprocessor, audio digital signal processor,
machine learning and graphics accelerators.
Add the basic dtsi support for i.MX8MP.
Patch from Anson Huang for Kernel
https://patchwork.kernel.org/patch/11310915/
Signed-off-by: Peng Fan <peng.fan@nxp.com>
We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MP use similar ocotp as i.MX8MN, but has changed fuse banks
and ctrl register bit definitions, so update to reflect that.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MP has similar architecture as i.MX8MN, but it has different
clk root and index, so add that to make i.MX8MP could use
the non-dm clock driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MP use 0x182 as dummy id, 0xFF is not able the get the highest
bit, so enlarge bit mask to 0x1FF to make it could detect
cpu type correctly
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to
generated AXI bus errors with TZC380 enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
fsl_esdhc_imx driver will call "mxc_get_clock(MXC_ESDHC_CLK +
dev->seq)", however mxc_get_clock wrongly handle MXC_ESDHC_CLK
as root clk and cause sd card could not be detected in U-Boot proper,
as below:
"Loading Environment from MMC... unable to select a mode"
Handle MXC_ESDHC_CLK in mxc_get_clock to fix the issue.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Tested-by: Fabio Estevam <festevam@gmail.com>
After the conversion to DM_PMIC the following output is seen:
PMIC: PMIC: PFUZE100 ID=0x10
Remove the unnecessary PMIC string from the board file to
avoid the repetead string.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Commit ec837c82d7 ("imx6: wandboard: convert to DM_PMIC")
caused the following pmic_get() error:
CPU: Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: POR
DRAM: 2 GiB
PMIC: pmic_get() ret -19
...
and since the PMIC presence is used to determine the board D1 revision,
the following error is seen when booting a board rev D1:
WARNING: Could not determine dtb to use
and the kernel does not boot at all.
Fix the regression by passing "pfuze100@8" as the correct parameter
to the pmic_get() function in the DM case.
Fixes: ec837c82d7 ("imx6: wandboard: convert to DM_PMIC")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
It's true that booting normally doesn't take long enough for the
register to roll (which actually happens in a little over an hour, not
just a few seconds). However, the counter starts at power-on, and if
the board is held in reset to be booted over USB, one actually risks
hitting wrap-around during boot, which can both result in too short
delays (if the "st += delay" calculation makes st small) and
theoretically also unbound delays (if st ends up being UINT_MAX and
one just misses sampling digctl_microseconds at that point).
It doesn't take more code to DTRT, and once bitten, twice shy.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Engicam i.CoreM6 1.5 Quad/Dual MIPI dtsi is reusing fec node
from Engicam i.CoreM6 dtsi but have sampe copy of phy-reset-gpio
and phy-mode properties.
So, drop this phy reset methods from imx6qdl-icore-1.5 dsti file.
Cc: Jacopo Mondi <jacopo@jmondi.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The EDIMM STARTER KIT i.Core 1.5 MIPI Evaluation is based on
the 1.5 version of the i.Core MX6 cpu module. The 1.5 version
differs from the original one for a few details, including the
ethernet PHY interface clock provider.
With this commit, the ethernet interface works properly:
SMSC LAN8710/LAN8720 2188000.ethernet-1:00: attached PHY driver
While before using the 1.5 version, ethernet failed to startup
do to un-clocked PHY interface:
fec 2188000.ethernet eth0: could not attach to PHY
Similar fix has merged for i.Core MX6Q but missed to update for DL.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Sync Engicam device tree file from v5.4 linux-next.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Now all the fec related phy properties are now accessible
via dts. So drop the explicit config items from common
config file, imx6-engicam.h
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
According to the SOM and reference board the clock
can be taken from the external pin or provided from
ENET_REF_CLK. Add a new function that make the proper
set according the board type.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Make easy to map fdt file to board in order to use
this information later to apply specific change to
specific board combination.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The data sheet says that the DIV field cannot change while the CLKGATE
bit is set or modified. So do it a little more carefully, by first
clearing the bit, waiting for that to appear, then setting the DIV
field.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
The comment says to clear the bypass bit, but in fact it sets it, thus
selecting ref_xtal. And the next line of code does not set the divider
to 12, but to (the reset value of) 1.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
I tried clearing a bit by writing to hw_clkctrl_gpmi_clr, then
busy-waiting for it to actually clear. My board hung. The data sheet
agrees, these registers do not have _set, _clr, _tog, so fix up the
definitions. git grep -E 'clkctrl_(gpmi|ssp[0-9])_' says that nobody
uses those non-existing ops registers.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Adjust the environment for booting a mainline kernel by default.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add info about supported i.MX7, improve details the usage of
bcbonly subcommand.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address, so fix it
accordingly.
Reported-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address, so fix it
accordingly.
Reported-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address, so fix it
accordingly.
Reported-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
In cases when the same SPL should run on boards with i.MX8MM, that
differ in DDR configuration, it is necessary to try different
parameters and check if the training done by the firmware suceeds or
not.
Therefore we return the DDR training/initialization success to the
upper layer in order to be able to retry with different settings if
necessary.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
The DDR firmware binaries are not part of the U-Boot source code, so
we should look for them in the build directory, where they need to be
copied to before building U-Boot.
The ATF binary is already fetched from the build directory, but the
README files for the i.MX8M EVKs claim that it needs to be copied to
the source directory (which is still true for in-tree builds, but not
in general). Therefore we also fix the READMEs to use the build
directory as the correct location for all additional binary files.
Sined-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
In the case of i.MX6 and i.MX7 family SoCs it is safe (from an errata
point of view) to use thumb2 by default to save space.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Currently imx-specific bootaux command doesn't support ELF format
firmware for Cortex-M4 core.
This patches introduces a PoC implementation of handling elf firmware
(load_elf_image_phdr() was copy-pasted from elf.c just for PoC).
ELF64 binaries isn't supported yet.
This has the advantage that the user does not need to know to which
address the binary has been linked to. However, in order to handle
and load the elf sections to the right address, we need to translate the
Cortex-M4 core memory addresses to primary/host CPU memory
addresses (Cortex A7/A9 cores).
This allows to boot firmwares from any location with just using
bootaux, e.g.:
> tftp ${loadaddr} hello_world.elf && bootaux ${loadaddr}
Similar translation table can be found in the Linux remoteproc
driver [1].
[1] https://elixir.bootlin.com/linux/latest/source/drivers/remoteproc/imx_rproc.c
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Sync DTS with the mainline Linux and introduce fec node and
regulator configuration for rn5t567 PMU.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Sync DTS with the mainline Linux and introduce fec node.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Sync DTS with the mainline Linux and introduce fec node.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Take over maintainership for colibri_imx6/imx6ull/t30/vf modules.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Take over maintainership for apalis_imx6 and colibri_imx6 modules.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
The Embedded Artists COM board is based on NXP i.MX7ULP.
It has a BD70528 PMIC from Rohm with discrete DCDC powering option and
improved current observability (compared to the existing NXP i.MX7ULP EVK).
Add the initial support for the board.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
