Commit Graph

6452 Commits

Author SHA1 Message Date
Scott Wood
c45912d8ab NAND: sync with 2.6.27
This brings the core NAND code up to date with the Linux kernel.

Since there were several drivers in Linux as of the last update that are
not in u-boot, I'm not bringing over new drivers that have been added
since in the absence of an interested party.

I did not update OneNAND since it was recently synced by Kyungmin Park,
and I'm not sure exactly what the common ancestor is.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-10-29 10:42:16 -05:00
Kumar Gala
b1d0db1805 bootm: Added CONFIG_BOOTM_{LINUX, NETBSD, RTEMS}
Added the ability to config out bootm support for Linux, NetBSD, RTEMS

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-29 01:00:20 +01:00
Kumar Gala
5a98127d81 bootm: support subcommands in linux ppc bootm
Add support for 'bdt', 'cmdline', 'prep' to the linux PPC bootm.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-29 01:00:17 +01:00
Kumar Gala
49c3a861d1 bootm: Add subcommands
Add the ability to break the steps of the bootm command into several
subcommands: start, loados, ramdisk, fdt, bdt, cmdline, prep, go.

This allows us to do things like manipulate device trees before
they are passed to a booting kernel or setup memory for a secondary
core in multicore situations.

Not all OS types support all subcommands (currently only start, loados,
ramdisk, fdt, and go are supported).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-29 00:59:50 +01:00
Kumar Gala
be08315933 bootm: Move to using a function pointer table for the boot os function
This removes a bit of code and makes it easier for the upcoming sub bootm
command support to call into the proper OS specific handler.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-29 00:57:31 +01:00
Wolfgang Denk
d35c451d6c Merge branch 'master' of git://git.denx.de/u-boot-video 2008-10-28 08:37:19 +01:00
Graeme Russ
a369f4a492 i386: Renamed show_boot_progress in assembler code
Renamed show_boot_progress in assembler init phase to
show_boot_progress_asm to avoid link conflicts with C version

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2008-10-28 00:26:35 +01:00
Andy Fleming
16263ffd3c Merge branch 'denx' 2008-10-27 17:31:05 -05:00
Peter Tyser
4442f45b0e 85xx: Update MPC85xx_PORDEVSR_IO_SEL mask
The MPC8572 has a 4-bit wide PORDEVSR IO_SEL field. Other MPC85xx
processors have a 3-bit wide IO_SEL field but have the most
significant bit is wired to 0 so this change should not affect
them.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-10-27 16:45:43 -05:00
Wolfgang Denk
f8030519bb Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2008-10-27 22:31:32 +01:00
Becky Bruce
cd42516242 powerpc: fix pci window initialization to work with > 4GB DRAM
The existing code has a few errors that need to be fixed in
order to support large RAM sizes.  Fix those, and add a
comment to make it clearer.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-27 16:27:58 -05:00
Kumar Gala
219542a1a6 pci/fsl_pci_init: Removed a bunch pointless trailing backslashes.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-27 16:26:07 -05:00
Haavard Skinnemoen
6b59e03e02 lcd: Let the board code show board-specific info
The information displayed when CONFIG_LCD_INFO is set is inherently
board-specific, so it should be done by the board code. The current code
dealing with this only handles two cases, and is already a horrible mess
of #ifdeffery.

Yes, this duplicates some code, but it also allows boards to print more
board-specific information; this used to be very difficult.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-10-27 09:53:58 +01:00
Haavard Skinnemoen
6f93d2b8fc lcd: Set lcd_is_enabled before clearing the screen
This allows the logo/info rendering routines to use the regular
lcd_putc/lcd_puts/lcd_printf calls.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-10-25 22:59:41 +02:00
Haavard Skinnemoen
15b17ab52b lcd: Implement lcd_printf()
lcd_printf() has a prototype in include/lcd.h but no implementation. Fix
this by borrowing the lcd_printf() implementation from the cogent board
code (which appears to use its own LCD framework.)

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-10-25 22:58:51 +02:00
Haavard Skinnemoen
70dbc54c0a atmel_lcdfb: Straighten out funky vl_sync logic
If the board _didn't_ request INVLINE_INVERTED, we set INVLINE_INVERTED,
otherwise we don't. WTF?

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-10-25 20:33:32 +02:00
Haavard Skinnemoen
23bb28f0f7 atmel_lcdfb: Eliminate unneeded #include <asm/arch/hardware.h>
atmel_lcdfb doesn't actually need anything from asm/arch/hardware.h. It
includes a file that does, asm/arch/gpio.h, but this file doesn't
include <asm/arch/hardware.h> like it's supposed to.

Add the missing include to asm/arch/gpio.h and remove the workaround
from the atmel_lcdfb driver. This makes the driver compile on avr32.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-10-25 20:33:10 +02:00
Kumar Gala
c2083e0e11 86xx: Convert all fsl_pci_init users to new APIs
Converted MPC8610HCPD, MPC8641HPCN, and SBC8641D to use
fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup().

With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-10-24 17:35:48 -05:00
Kumar Gala
2dba0dea98 85xx: Convert all fsl_pci_init users to new APIs
Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS,
MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows()
and ft_fsl_pci_setup().

With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-24 17:35:12 -05:00
Kumar Gala
a2aab46072 pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-ranges
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-24 17:35:08 -05:00
Kumar Gala
b9a1fa9787 pci/fsl_pci_init: Add a common PCI inbound setup function
Add a common setup function that determines the pci_region(s) based
on how much memory we have in the system.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-24 17:35:05 -05:00
Kumar Gala
612ea01018 pci/fsl_pci_init: Enable larger address and setting inbound windows properly
* PCI Inbound window was setup incorrectly.  The PCI address and system
  address were swapped.  The PCI address should be setting piwar/piwbear
  and the system address should be setting pitar.

* Removed masking of addresses to allow for system address to support
  system address & PCI address >32-bits

* Set PIWBEAR & POTEAR to allow for full 64-bit PCI addresses

* Respect the PCI_REGION_PREFETCH for inbound windows

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-24 17:35:02 -05:00
Kumar Gala
8ab451c46b fdt: Added helper to set PCI dma-ranges property
Added fdt_pci_dma_ranges() that parses the pci_region info from the
struct pci_controller and populates the dma-ranges based on it.

The max # of windws/dma-ranges we support is 3 since on embedded
PowerPC based systems this is the max number of windows.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-24 17:34:57 -05:00
Kumar Gala
3bed2aaf2d fdt: Add fdt_getprop_u32_default helpers
Add helper functions to return find a node and return it's property
or a default value.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
2008-10-24 17:34:52 -05:00
Kumar Gala
8ba93f68a1 86xx: Enable 64-bit PCI resources on all Freescale boards
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-24 17:34:17 -05:00
Kumar Gala
0151cbaccf 85xx: Enable 64-bit PCI resources on all Freescale boards
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-24 17:33:06 -05:00
Kumar Gala
30e76d5e3b pci: Allow for PCI addresses to be 64-bit
PCI bus is inherently 64-bit.  While not all system require access to
the full 64-bit PCI address range some do.  This allows those systems
to enable the full PCI address width via CONFIG_SYS_PCI_64BIT.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
Acked-by: Wolfgang Denk <wd@denx.de>
2008-10-24 17:32:49 -05:00
Dave Liu
ae5f943ba8 85xx: Fix the incorrect register used for DDR erratum1
The 8572 DDR erratum1:
DDR controller may enter an illegal state when operating
in 32-bit bus mode with 4-beat bursts.

Description:
When operating with a 32-bit bus, it is recommended that
DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used.
This forces the DDR controller to use 4-beat bursts when
communicating to the DRAMs. However, an issue exists that
could lead to data corruption when the DDR controller is
in 32-bit bus mode while using 4-beat bursts.

Projected Impact:
If the DDR controller is operating in 32-bit bus mode with
4-beat bursts, then the controller may enter into a bad state.
All subsequent reads from memory is corrupted.
Four-beat bursts with a 32-bit bus only is used with DDR2 memories.
Therefore, this erratum does not affect DDR3 mode.

Work Arounds:
To work around this issue, software must set DEBUG_1[31] in
DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1
and CCSRBAR offset + 0x6f00 for DDR_2).

Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2
as condition, but it should be DDR_SDRAM_CFG register.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-10-24 17:29:37 -05:00
Dave Liu
d5b693090e 85xx: remove unused config definition
Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-10-24 16:18:33 -05:00
Kumar Gala
0f060c3bf8 85xx: Add basic e500mc core support
Introduce CONFIG_E500MC to deal with the minor differences between
e500v2 and e500mc.

* Certain fields of HID0/1 don't exist anymore on e500mc
* Cache line size is 64-bytes on e500mc
* reset value of PIR is different

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-24 15:10:47 -05:00
Kumar Gala
a38a5b6edd 85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic number
Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle
e500mc's 64-byte cacheline properly when it gets added.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-24 15:10:23 -05:00
Georg Schardt
5deb8022c3 ppc4xx: New board avnet fx12 minimodul
This patch adds support for the avnet fx12 minimodul.
It needs the "ppc4xx: Generic architecture for xilinx ppc405"
patch from Ricardo.

Signed-off-by: Georg Schardt <schardt@team-ctech.de>
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-24 17:34:26 +02:00
Ricardo Ribalda Delgado
1f4d53260e ppc4xx: Generic architecture for xilinx ppc405(v3)
As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
ppc440 boards, this patch presents a common architecture for all the
xilinx ppc405 boards.

Any custom xilinx ppc405 board can be added very easily with no code
duplicity.

This patch also adds a simple generic board, that can be used on almost
any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h

This patch is prepared to work with the latest version of EDK (10.1)

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-24 17:26:09 +02:00
Stefan Roese
485c00a57f ppc4xx: Disable DDR2 autocalibration on Kilauea for now
Since the new autocalibration still has some problems on some Kilauea
boards with 200MHz DDR2 frequency we disable the autocalibration and
use the hardcoded values as done before. This seems to work reliably
on all known DDR2 frequencies.

After the autocalibration issue is fixed we will enable it again.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-24 17:25:13 +02:00
Wolfgang Denk
d9d8c7c696 Fix strmhz(): avoid printing negative fractions
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-22 08:52:19 +02:00
Richard Retanubun
4a7f6b750d mpc83xx: Removed #ifdef CONFIG_MPC834X dependency on upmconfig function
This is done to allow other 83XX based platforms which also have UPM
(e.g. 8360) to configure and use their UPM in u-boot.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:41:04 -05:00
Anton Vorontsov
3bf1be3c0c mpc83xx: add support for switching between USB Host/Function for MPC837XEMDS
With this patch u-boot can fixup the dr_mode and phy_type properties
for the Dual-Role USB controller.

While at it, also remove #ifdefs around includes, they are not needed.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:40:01 -05:00
Anton Vorontsov
b3379f3fd1 mpc83xx: add ELBC NAND support for the MPC837XEMDS boards
Though NAND chip is replaceable on the MPC837XE-MDS boards, the
current settings don't work with the default chip on the board.
Nevertheless Freescale's U-Boot sets the option register correctly,
so I just dumped the register from the working u-boot. My guess is
that the old settings were applicable for some pilot boards, not
found in the production.

This patch also enables FSL ELBC driver so that we could access
the NAND storage in the u-boot.

The NAND support costs about 45KB, so the u-boot no longer fits
into two 128KB NOR flash sectors, thus we also have to adjust
environment location: add another 128KB to the monitor length.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>

It is due to hardware design and logic defect, that is the
I/O[0:7] of NAND chip is connected to LAD[7:0], so when
the NAND chip connected to nLCS3,  you have to set up the
OR3[BCTLD] = '1' for normal operation, otherwise it will have
bus contention due to the pin 48/25 of U60 is enabled.

Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not
asserted upon access to the NAND chip, keep the default state.

Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:17 -05:00
Anton Vorontsov
00f7bbae92 mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boards
The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB,
standalone or acting as a PCI agent. User's Guide says:

- When the CPLD recognizes its location on the PIB it automatically
  configures RCW to the PCI Host.
- If the CPLD fails to recognize its location then it is automatically
  configured as an Agent and the PCI is configured to an external arbiter.

This sounds good. Though in the standalone setup the CPLD sets PCI_HOST
flag (it's ok, we can't act as PCI agents since we receive CLKIN, not
PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without
any arbiter bad things will happen (here the board hangs during any config
space reads).

In this situation we must disable the PCI. And in case of anybody really
want to use an external arbiter, we provide "pci_external_aribter"
environment variable.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:14 -05:00
Anton Vorontsov
1da83a63d8 mpc83xx: add SGMII riser module support for the MPC8378E-MDS boards
This involves configuring the SerDes and fixing up the flags and
PHY addresses for the TSECs.

For Linux we also fix up the device tree.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:08 -05:00
Anton Vorontsov
e6d9c8916d mpc83xx: add TSECs' HRCWH masks for MPC837x processors
We'll use these masks to parse TSEC modes out of HRCWH.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:05 -05:00
Anton Vorontsov
6f9cc6608b mpc83xx: serdes: add forgotten shifts for rfcks
The rfcks should be shifted by 28 bits left. We didn't notice the bug
because we were using only 100MHz clocks (for which rfcks == 0).

Though, for SGMII we'll need 125MHz clocks.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:01 -05:00
Anton Vorontsov
55c531984d mpc83xx: fix serdes setup for the MPC8378E boards
MPC837xE specs says that SerDes1 has:

— Two lanes running x1 SGMII at 1.25 Gbps;
— Two lanes running x1 SATA at 1.5 or 3.0 Gbps.

And for SerDes2:

— Two lanes running x1 PCI Express at 2.5 Gbps;
— One lane running x2 PCI Express at 2.5 Gbps;
— Two lanes running x1 SATA at 1.5 or 3.0 Gbps.

The spec also explicitly states that PEX options are not valid for
the SD1.

Nevertheless MPC8378 RDB and MDS boards configure the SD1 for PEX,
which is wrong to do.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:33:25 -05:00
Anton Vorontsov
5c2ff323a9 mpc83xx: mpc8360emds: rework LBC SDRAM setup
Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes
it difficult to use (b/c then the memory is discontinuous and
there is quite big memory hole between the DDR/SDRAM regions).

This patch reworks LBC SDRAM setup so that now we dynamically
place the LBC SDRAM near the DDR (or at 0x0 if there isn't any
DDR memory).

With this patch we're able to:

- Boot without external DDR memory;
- Use most "DDR + SDRAM" setups without need to support for
  sparse/discontinuous memory model in the software.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:31:07 -05:00
Wolfgang Denk
def0819e92 FDT: don't use private kernel header files
On some systems (for example Fedora Core 4) U-Boot builds with the
following wanrings only:

...
In file included from /home/wd/git/u-boot/include/libfdt_env.h:33,
                 from fdt.c:51:
		 /usr/include/asm/byteorder.h:6:2: warning: #warning using private kernel header; include <endian.h> instead!

This patch fixes this problem.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-21 21:35:44 +02:00
Wolfgang Denk
06c2942218 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2008-10-21 21:19:35 +02:00
Stefan Roese
f4d14c5550 ppc4xx: Add 1.0 & 1.066 GHz to canyonlands bootstrap command for PLL setup
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:35:02 +02:00
Stefan Roese
43cbce69d4 ppc4xx: Correctly setup ranges property in ebc node
Previously only the NOR flash mapping was written into the ranges
property of the ebc node. This patch now writes all enabled chip
select areas into the ranges property.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:35:02 +02:00
Dirk Eibach
d7b26d5832 ppc4xx: Add GDSys neo 405EP board support
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:35:02 +02:00
Niklaus Giger
c11da19454 ppc4xx: Update configs for Netstal boards
I reorganized my config files, putting the common stuff into netstal-common.h
(got the idea by looking a amcc-common.h from Stefan).

Added stuff to boot the new powerpc linux via NFS (only tested with HCU4).

Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:34:57 +02:00