Use the full driver model GPIO and serial drivers in SPL now that these are
supported. Since device tree is not available they will use platform data.
Remove the special SPL GPIO function as it is no longer needed.
This is all in one commit to maintain bisectability.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is already set up in crt0.S. We don't need a new structure and don't
really want one in the 'data' section of the image, since it will be empty
and crt0.S's changes will be ignored.
As an interim measure, remove it only if CONFIG_DM is not defined. This
allows us to press ahead with driver model in SPL and allow the stragglers
to catch up.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function has grown into something of a monster. Some boards are setting
up a console and DRAM here in SPL. This requires global_data which should be
set up in one place (crt0.S).
There is no need for SPL to use s_init() for anything since board_init_f()
is called immediately afterwards.
Signed-off-by: Simon Glass <sjg@chromium.org>
This commit removes the dram reservation from board file,
because it is done in a common code.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit enables the last DRAM bank and reserves
the last 22 MiB of it, for the secure firmware.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Hyungwon Hwang <human.hwang@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Since more than one board requires memory reservation
for the secure firmware, the reservation code can be
made in a common code.
Now, to reserve some part of the the last bank,
board config should define:
- CONFIG_TZSW_RESERVED_DRAM - len in bytes
- CONFIG_NR_DRAM_BANKS - number of memory banks
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Hyungwon Hwang <human.hwang@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add basic Xilinx ZynqMP arm64 support.
Serial and SD is supported.
It supports emulation platfrom ep108 and QEMU.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This code was introduced to support the multiple .config
configuration in U-Boot. We do not need it any more.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
With a389531 we now call readl() from this file so add <asm/io.h> so
that we have a prototype for the function.
Signed-off-by: Tom Rini <trini@konsulko.com>
After discussion during the last u-boot mini summit with USB maintainer -
Marek Vasut - it has been decided, that gadget development should be
coordinated by DFU custodian.
Such patch formalizes current development status.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Integrate latest validated register settings from Toradex WinCE BSP
4.2 working accross all module versions from early V1.x, V1.2D, V2.2B
to V2.4A.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Specify a CONFIG_BOARD_SIZE_LIMIT of 256 KB in order to avoid
overwriting the factory configuration block located at offset 0x40000
in NOR flash.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
To save more than 20 KB of precious space in NOR flash get rid of the
following configuration options:
CONFIG_CMD_LOADB
CONFIG_CMD_LOADS
CONFIG_SYS_LONGHELP
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Migrate Toradex Colibri PXA270 to use CONFIG_SYS_GENERIC_BOARD.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
I couldn't quite figure out whether or not CONFIG_SYS_ENV_IS_NOWHERE
actually ever worked but nowadays this is called CONFIG_ENV_IS_NOWHERE.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Basically finish what the following commit started a long time ago:
488f5d8790
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
For mx35pdk/woodburn:
Acked-by: Stefano Babic <sbabic@denx.de>
Each way of the system cache has 256 entries for PH1-Pro4 and older
SoCs, whereas 512 entries for PH1-Pro5 and newer SoCs. The line
size is still 128 byte. Thus, the way size is 32KB/64KB for old/new
SoCs.
To keep lowlevel_init SoC-independent, set BOOT_RAM_SIZE to the
constant value 32KB. It is large enough for temporary RAM and
should work for all the SoCs of UniPhier family.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This function was intended for MN2WS0235 (what we call PH1-Pro4TV).
On that SoC, MPLL is already running on the power-on reset and it
makes sense to stop the PLL at early boot-up.
On the other hand, PH1-Pro4(R) does not have SC_MPLLOSCCTL register,
so this function has no point.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This code is duplicated in ph1-ld4/sg_init.c and ph1-pro4/sg_init.c.
Merge the same code into a new file, memconf.c.
The helper functions no longer have to be placed in the header file.
Also, move them into memconf.c.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The 3CS support card (CONFIG_DCC_MICRO_SUPPORT_CARD) used to be used
very often before, but it is recently getting a minority. Swith to
the 1CS support card (CONFIG_PFC_MICRO_SUPPORT_CARD).
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Two support card variants are used with UniPhier reference boards:
- 1 chip select support card (original CPLD)
- 3 chip selects support card (ARIMA-compatible CPLD)
Currently, the former is only supported on PH1-Pro4, but it can be
expanded to PH1-LD4, PH1-sLD8 with a little code change.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
PH1-Pro4 includes both EHCI and xHCI IP cores.
Unfortunately, U-Boot cannot enable EHCI and xHCI support
simultaneously. Some users may wish Super-Speed connection.
Disable CONFIG_USB_EHCI_HCD and enable CONFIG_USB_XHCI_HCD.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Support xHCI host driver used on Panasonic UniPhier platform.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Each USB port corresponds to the following IP core:
port0: xHCI (0x65a00000) SS+HS
port1: xHCI (0x65c00000) HS (SS PHY is not implemented)
port2: EHCI (0x5a800100) HS
port3: EHCI (0x5a810100) HS
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
EHCI host controllers have a common register interface.
We may wish to implement a generic EHCI driver someday.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Because uniphier_ehci_reset() is only called from ehci-uniphier.c,
it can be a static function there.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Now UniPhier platform highly depends on Device Tree configuration
(CONFIG_OF_CONTROL is select'ed by Kconfig). Since the EHCI is only
used on main U-Boot, we can drop platform devices of the EHCI
controllers. We still keep UART platform devices because they might
be useful for SPL.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Deassert the reset signal and provide the clock for STDMAC core.
This is necessary for the USB 2.0 host controllers.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
