This patch adds 200MHz clock configuration for stm32f746 discovery board.
This patch is based on STM32F4 and emcraft's[1].
[1]: https://github.com/EmcraftSystems/u-boot
Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
At present sandbox exits when the 'bootm' command completes, since it is not
actually able to run the OS that is loaded. Normally 'bootm' failure is
considered a fatal error in U-Boot.
However this is annoying for tests, which may want to examine the state
after a test is complete. In any case there is a 'reset' command which can
be used to exit, if required.
Change the behaviour to return normally from the 'bootm' command on sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Teddy Reed <teddy.reed@gmail.com>
For most of architectures in U-Boot, virtual address is straight
mapped to physical address. So, it makes sense to have generic
defines of ioremap and friends in <linux/io.h>.
All of them are just empty and will disappear at compile time, but
they will be helpful to implement drivers which are counterparts of
Linux ones.
I notice MIPS already has its own implementation, so I added a
Kconfig symbol CONFIG_HAVE_ARCH_IOREMAP which MIPS (and maybe
Sandbox as well) can select.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
These defines are valid only when iomem_valid_addr is defined,
but I do not see such defines anywhere. Remove.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, this is only defined in arch/arm/include/asm/types.h,
so move it to include/linux/types.h to make it available for all
architectures.
I defined it with phys_addr_t as Linux does. I needed to surround
the define with #ifdef __KERNEL__ ... #endif to avoid build errors
in tools building. (Host tools should not include <linux/types.h>
in the first place, but this is already messy in U-Boot...)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Modify the SPL build procedure for AM437x high-security (HS) device
variants to create a secure u-boot_HS.img FIT blob that contains U-Boot
and DTB artifacts signed (and optionally encrypted) with a TI-specific
process based on the CONFIG_TI_SECURE_DEVICE config option and the
externally-provided image signing tool.
Also populate the corresponding FIT image post processing call to be
performed during SPL runtime.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Modify the SPL build procedure for AM57xx and DRA7xx high-security (HS)
device variants to create a secure u-boot_HS.img FIT blob that contains
U-Boot and DTB artifacts signed with a TI-specific process based on the
CONFIG_TI_SECURE_DEVICE config option and the externally-provided image
signing tool.
Also populate the corresponding FIT image post processing call to be
performed during SPL runtime.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds commands so that when a secure device is in use and the SPL is
built to load a FIT image (with combined U-Boot binary and various
DTBs), these components that get fed into the FIT are all processed to
be signed/encrypted/etc. as per the operations performed by the
secure-binary-image.sh script of the TI SECDEV package. Furthermore,
perform minor comments cleanup to make better use of the available
space.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adds an API that verifies a signature attached to an image (binary
blob). This API is basically a entry to a secure ROM service provided by
the device and accessed via an SMC call, using a particular calling
convention.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds a generic C-callable API for making secure ROM calls on OMAP and
OMAP-compatible devices. This API provides the important function of
flushing the ROM call arguments to memory from the cache, so that the
secure world will have a coherent view of those arguments. Then is
simply calls the omap_smc_sec routine.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add an interface for calling secure ROM APIs across a range of OMAP and
OMAP compatible high-security (HS) device variants. While at it, also
perform minor cleanup/alignment without any change in functionality.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds missing flush_dcache_range and invalidate_dcache_range dummy
(empty) placeholder functions to the #else portion of the #ifndef
CONFIG_SYS_DCACHE_OFF, where full implementations of these functions
are defined.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
There are two enable methods supported by ARM64 Linux; psci and
spin-table. The latter is simpler and helpful for quick SoC bring
up. My main motivation for this patch is to improve the spin-table
support, which allows us to boot an ARMv8 system without the ARM
Trusted Firmware.
Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S
and the spin-table is supported in a really ad-hoc way, and I see
some problems:
- We must hard-code CPU_RELEASE_ADDR so that it matches the
"cpu-release-addr" property in the DT that comes from the
kernel tree.
- The Documentation/arm64/booting.txt in Linux requires that
the release address must be zero-initialized, but it is not
cared by the common code in U-Boot. We must do it in a board
function.
- There is no systematic way to protect the spin-table code from
the kernel. We are supposed to do it in a board specific manner,
but it is difficult to predict where the spin-table code will be
located after the relocation. So, it also makes difficult to
hard-code /memreserve/ in the DT of the kernel.
So, here is a patch to solve those problems; the DT is run-time
modified to reserve the spin-table code (+ cpu-release-addr).
Also, the "cpu-release-addr" property is set to an appropriate
address after the relocation, which means we no longer need the
hard-coded CPU_RELEASE_ADDR.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Upon further review this breaks most other platforms as we need to check
what core we're running on before touching it at all.
This reverts commit d73718f323.
Signed-off-by: Tom Rini <trini@konsulko.com>
With the change to set up pinctrl after relocation, link fails to boot. Add
a special case in the link code to handle this.
Fixes: d8906c1f (x86: Probe pinctrl driver in cpu_init_r())
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for Advantech SOM-DB5800 with the SOM-6867 installed.
This is very similar to conga-qeval20-qa3-e3845 in that there is a
reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867)
installed.
Currently supported:
- 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on
SOM-DB5800.
- 4x USB 2.0 (EHCI)
- Video
- SATA
- Ethernet
- PCIe
- Realtek ALC892 HD Audio
Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO
HDA_SDI0 is set in DT to enable HD Audio codec.
Pin defaults for codec pin complexs are not changed.
Not supported:
- Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500)
- USB 3.0 (XHCI)
- TPM
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If global NVS says internal UART is not enabled, hide it in the ASL
code so that OS won't see it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that platform-specific ACPI global NVS is added, pack it into
ACPI table and get its address fixed up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This introduces quark-specific ACPI global NVS structure, defined in
both C header file and ASL file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This introduces baytrail-specific ACPI global NVS structure, defined in
both C header file and ASL file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For any FSP-enabled boards that want to enable debug UART support,
setup_internal_uart() will be called, but this API is only available
on BayTrail platform. Change to wrap it with CONFIG_INTERNAL_UART.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
There are quite a number of BayTrail boards that uses an external
SuperIO chipset to provide the legacy UART. For such cases, it's
better to have a Kconfig option to enable the internal UART.
So far BayleyBay and MinnowMax boards are using internal UART as
the U-Boot console, enable this on these two boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
We have drivers for several more devices now, so drop the strings which are
no-longer used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Define a platform data structure for the MPC85XX GPIO driver to allow
use of the driver without device tree. Users should define the GPIO
blocks for their platform like this:
struct mpc85xx_gpio_plat gpio_blocks[] = {
{
.addr = 0x130000,
.ngpios = 32,
},
{
.addr = 0x131000,
.ngpios = 32,
},
};
U_BOOT_DEVICES(my_platform_gpios) = {
{ "gpio_mpc85xx", &gpio_blocks[0] },
{ "gpio_mpc85xx", &gpio_blocks[1] },
};
This is intended to build upon the recent submission of the base
MPC85XX driver from Mario Six. We need to use that new driver
without dts support and this patch gives us that flexibility.
This has been tested on a Freescale T2080 CPU, although only the first
GPIO block.
Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
Tested-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Simon Glass <sjg@chromium.org>
Rockchip uses driver model for all subsystems. Specify this in the arm
Kconfig rather than as defaults in the Rockchip Kconfig. This means that
boards cannot turn these options off, which seems correct.
Signed-off-by: Simon Glass <sjg@chromium.org>
According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
throughput.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
K2G SoC has a Cadence QSPI controller to communicate with NOR flash
devices. Add DT nodes to support the same.
Also, K2G EVM has a s25fl512s flash connect to QSPI bus at CS 0. Add nor
flash slave node for the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
K2G SoC has 4 SPI instances that are compatible with davinci_spi
controller(present on previous generation of Keystone2 devices). Add DT
nodes for the same. K2G EVM has a N25Q128A13 SPI NOR flash connected on
SPI-1. Add DT bindings for the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Add aliases for SPI nodes in order for it to be probed by the DM
framework.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.
For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Commit e677724 (arm: Fix setjmp) added code to fix compilation of the setjmp
code path with thumv1. Unfortunately it missed a constraint that the adr
instruction can only refer to 4 byte aligned offsets.
So this patch adds the required alignment hooks to make compilation
work again even when setjmp doesn't happen to be 4 byte aligned.
Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: Tom Rini <trini@konsulko.com>
We have standard drivers for panels and backlights which can do most of the
work for us. Move the tegra20 LCD driver over to use those instead of custom
code.
This patch includes device tree changes for the nvidia boards. I have only
been able to test seaboard. If this patch is applied, these boards will
also need to be synced with the kernel, and updated to use display-timings:
- colibri
- medcom-wide
- paz00
- tec
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Sync everything except the display panel, which will come in a future patch.
One USB port is left disabled since we don't want to support it in U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The errata command is useless in SPL, so don't build it. This fixes
multiple build failures on PowerPC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: York Sun <york.sun@nxp.com>
Fixes: 92623672f9 ("fsl: usb: make errata function common for PPC and ARM")
Currently on attempt to use global_data.h in an assembly file following
will happen:
-------------------->8-----------------
./arch/arc/include/asm/global_data.h: Assembler messages:
./arch/arc/include/asm/global_data.h:11: Error: bad instruction 'struct arch_global_data{'
./arch/arc/include/asm/global_data.h:12: Error: junk at end of line, first unrecognized character is `}'
scripts/Makefile.build:316: recipe for target 'arch/arc/lib/start.o' failed
-------------------->8-----------------
In this change we disable struct arch_global_data in ASM which fixes
the issue above.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Newer ARC toolchains don't support "-marchs" option any longer.
Instead "-mcpu=archs" should be used. What's also important older
toiolchains that support ARC HS cores will also happily accept
"-mcpu=archs" so that's a very safe move.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
The Parrot Board is an evaluation board with an Allwinner R16 (assumed
to be close to an Allwinner A33), 4GB of eMMC, 512MB of RAM, USB host
and OTG, a WiFi/Bluetooth combo chip, a micro SD Card reader, 2
controllable buttons, an LVDS port with separated backlight and
capacitive touch panel ports, an audio/microphone jack, a camera CSI
port, 2 sets of 22 GPIOs and an accelerometer.
The DTS file is identical to the one submitted to the upstream kernel.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Commit b19236fd1 ("sunxi: Increase SPL header size to 64 bytes to avoid
code corruption") Added defines for MMC0 and SPI as boot identification.
After verifying on an OLinuXino Lime2 with NAND and eMMC, the expected
values have been confirmed and added to spl.h
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
I will carry this work-around until it is cared in the kernel.
This looks up the AIDET node and sets up a register to handle
active low interrupt signals.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The AIDET (ARM Interrupt Detector Add-on Circuit) is a kind of
syscon block related with the interrupt controller.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
