x86: Add Advantech SOM-DB5800/SOM-6867 support
Add support for Advantech SOM-DB5800 with the SOM-6867 installed. This is very similar to conga-qeval20-qa3-e3845 in that there is a reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867) installed. Currently supported: - 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on SOM-DB5800. - 4x USB 2.0 (EHCI) - Video - SATA - Ethernet - PCIe - Realtek ALC892 HD Audio Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO HDA_SDI0 is set in DT to enable HD Audio codec. Pin defaults for codec pin complexs are not changed. Not supported: - Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500) - USB 3.0 (XHCI) - TPM Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
George McCollister
Bin Meng
parent
3ff11aaa50
commit
215099a522
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@ -8,6 +8,9 @@ choice
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prompt "Mainboard vendor"
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default VENDOR_EMULATION
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config VENDOR_ADVANTECH
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bool "advantech"
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config VENDOR_CONGATEC
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bool "congatec"
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@ -29,6 +32,7 @@ config VENDOR_INTEL
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endchoice
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# board-specific options below
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source "board/advantech/Kconfig"
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source "board/congatec/Kconfig"
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source "board/coreboot/Kconfig"
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source "board/efi/Kconfig"
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@ -14,7 +14,8 @@ dtb-y += bayleybay.dtb \
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minnowmax.dtb \
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qemu-x86_i440fx.dtb \
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qemu-x86_q35.dtb \
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broadwell_som-6896.dtb
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broadwell_som-6896.dtb \
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baytrail_som-db5800-som-6867.dtb
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targets += $(dtb-y)
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@ -0,0 +1,289 @@
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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* Copyright (C) 2016, George McCollister <george.mccollister@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/x86-gpio.h>
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#include <dt-bindings/interrupt-router/intel-irq.h>
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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/ {
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model = "Advantech SOM-DB5800-SOM-6867";
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compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
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aliases {
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serial0 = &serial;
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spi0 = &spi;
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};
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config {
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silent_console = <0>;
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};
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pch_pinctrl {
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compatible = "intel,x86-pinctrl";
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reg = <0 0>;
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/* HDA_RSTB */
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soc_gpio_s0_8@0 {
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pad-offset = <0x220>;
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mode-func = <2>;
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};
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/* HDA_SYNC */
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soc_gpio_s0_9@0 {
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pad-offset = <0x250>;
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mode-func = <2>;
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pull-assign = <1>;
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};
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/* HDA_CLK */
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soc_gpio_s0_10@0 {
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pad-offset = <0x240>;
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mode-func = <2>;
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};
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/* HDA_SDO */
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soc_gpio_s0_11@0 {
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pad-offset = <0x260>;
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mode-func = <2>;
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pull-assign = <1>;
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};
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/* HDA_SDI0 */
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soc_gpio_s0_12@0 {
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pad-offset = <0x270>;
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mode-func = <2>;
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};
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};
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chosen {
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stdout-path = "/serial";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,baytrail-cpu";
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reg = <0>;
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intel,apic-id = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "intel,baytrail-cpu";
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reg = <1>;
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intel,apic-id = <2>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "intel,baytrail-cpu";
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reg = <2>;
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intel,apic-id = <4>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "intel,baytrail-cpu";
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reg = <3>;
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intel,apic-id = <6>;
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};
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};
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pci {
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compatible = "intel,pci-baytrail", "pci-x86";
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#address-cells = <3>;
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#size-cells = <2>;
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u-boot,dm-pre-reloc;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
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0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
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0x01000000 0x0 0x2000 0x2000 0 0xe000>;
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pch@1f,0 {
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reg = <0x0000f800 0 0 0 0>;
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compatible = "pci8086,0f1c", "intel,pch9";
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#address-cells = <1>;
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#size-cells = <1>;
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irq-router {
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compatible = "intel,irq-router";
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intel,pirq-config = "ibase";
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intel,ibase-offset = <0x50>;
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intel,actl-addr = <0>;
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intel,pirq-link = <8 8>;
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intel,pirq-mask = <0xdee0>;
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intel,pirq-routing = <
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/* BayTrail PCI devices */
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PCI_BDF(0, 2, 0) INTA PIRQA
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PCI_BDF(0, 3, 0) INTA PIRQA
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PCI_BDF(0, 16, 0) INTA PIRQA
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PCI_BDF(0, 17, 0) INTA PIRQA
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PCI_BDF(0, 18, 0) INTA PIRQA
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PCI_BDF(0, 19, 0) INTA PIRQA
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PCI_BDF(0, 20, 0) INTA PIRQA
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PCI_BDF(0, 21, 0) INTA PIRQA
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PCI_BDF(0, 22, 0) INTA PIRQA
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PCI_BDF(0, 23, 0) INTA PIRQA
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PCI_BDF(0, 24, 0) INTA PIRQA
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PCI_BDF(0, 24, 1) INTC PIRQC
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PCI_BDF(0, 24, 2) INTD PIRQD
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PCI_BDF(0, 24, 3) INTB PIRQB
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PCI_BDF(0, 24, 4) INTA PIRQA
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PCI_BDF(0, 24, 5) INTC PIRQC
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PCI_BDF(0, 24, 6) INTD PIRQD
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PCI_BDF(0, 24, 7) INTB PIRQB
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PCI_BDF(0, 26, 0) INTA PIRQA
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PCI_BDF(0, 27, 0) INTA PIRQA
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PCI_BDF(0, 28, 0) INTA PIRQA
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PCI_BDF(0, 28, 1) INTB PIRQB
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PCI_BDF(0, 28, 2) INTC PIRQC
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PCI_BDF(0, 28, 3) INTD PIRQD
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PCI_BDF(0, 29, 0) INTA PIRQA
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PCI_BDF(0, 30, 0) INTA PIRQA
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PCI_BDF(0, 30, 1) INTD PIRQD
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PCI_BDF(0, 30, 2) INTB PIRQB
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PCI_BDF(0, 30, 3) INTC PIRQC
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PCI_BDF(0, 30, 4) INTD PIRQD
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PCI_BDF(0, 30, 5) INTB PIRQB
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PCI_BDF(0, 31, 3) INTB PIRQB
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/*
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* PCIe root ports downstream
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* interrupts
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*/
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PCI_BDF(1, 0, 0) INTA PIRQA
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PCI_BDF(1, 0, 0) INTB PIRQB
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PCI_BDF(1, 0, 0) INTC PIRQC
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PCI_BDF(1, 0, 0) INTD PIRQD
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PCI_BDF(2, 0, 0) INTA PIRQB
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PCI_BDF(2, 0, 0) INTB PIRQC
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PCI_BDF(2, 0, 0) INTC PIRQD
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PCI_BDF(2, 0, 0) INTD PIRQA
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PCI_BDF(3, 0, 0) INTA PIRQC
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PCI_BDF(3, 0, 0) INTB PIRQD
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PCI_BDF(3, 0, 0) INTC PIRQA
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PCI_BDF(3, 0, 0) INTD PIRQB
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PCI_BDF(4, 0, 0) INTA PIRQD
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PCI_BDF(4, 0, 0) INTB PIRQA
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PCI_BDF(4, 0, 0) INTC PIRQB
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PCI_BDF(4, 0, 0) INTD PIRQC
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>;
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};
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spi: spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich9-spi";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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compatible = "macronix,mx25l6405d",
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"spi-flash";
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memory-map = <0xff800000 0x00800000>;
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rw-mrc-cache {
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label = "rw-mrc-cache";
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reg = <0x006f0000 0x00010000>;
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};
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};
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};
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gpioa {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0 0x20>;
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bank-name = "A";
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};
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gpiob {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x20 0x20>;
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bank-name = "B";
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};
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gpioc {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x40 0x20>;
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bank-name = "C";
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};
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gpiod {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x60 0x20>;
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bank-name = "D";
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};
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gpioe {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x80 0x20>;
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bank-name = "E";
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};
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gpiof {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0xA0 0x20>;
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bank-name = "F";
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};
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};
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};
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fsp {
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compatible = "intel,baytrail-fsp";
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fsp,mrc-init-tseg-size = <0>;
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fsp,mrc-init-mmio-size = <0x800>;
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fsp,mrc-init-spd-addr1 = <0xa0>;
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fsp,mrc-init-spd-addr2 = <0xa2>;
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fsp,enable-spi;
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fsp,enable-sata;
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fsp,sata-mode = <1>;
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fsp,enable-azalia;
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fsp,lpss-sio-enable-pci-mode;
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fsp,enable-dma0;
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fsp,enable-dma1;
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fsp,enable-i2c0;
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fsp,enable-i2c1;
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fsp,enable-i2c2;
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fsp,enable-i2c3;
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fsp,enable-i2c4;
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fsp,enable-i2c5;
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fsp,enable-i2c6;
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fsp,enable-pwm0;
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fsp,enable-pwm1;
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fsp,igd-dvmt50-pre-alloc = <2>;
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fsp,aperture-size = <2>;
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fsp,gtt-size = <2>;
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fsp,scc-enable-pci-mode;
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fsp,os-selection = <4>;
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fsp,enable-igd;
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fsp,serial-debug-port-address = <0x3f8>;
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fsp,serial-debug-port-type = <1>;
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};
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microcode {
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update@0 {
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#include "microcode/m0130673325.dtsi"
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};
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update@1 {
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#include "microcode/m0130679907.dtsi"
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};
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};
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};
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@ -0,0 +1,28 @@
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if VENDOR_ADVANTECH
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choice
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prompt "Mainboard model"
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optional
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config TARGET_SOM_DB5800_SOM_6867
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bool "Advantech SOM-DB5800 & SOM-6867"
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help
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Advantech SOM-DB5800 COM Express development board with SOM-6867
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installed.
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SOM-6867 is a COM Express Type 6 Compact Module with either an Intel
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Atom E3845 or Celeron N2920 processor.
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SOM-DB5800 is a COM Express Development board with:
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10/100/1000 Ethernet
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PCIe slots
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4x USB ports
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HDMI/DisplayPort/DVI, LVDS, VGA
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SATA ports
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ALC892 HD Audio Codec
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endchoice
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source "board/advantech/som-db5800-som-6867/Kconfig"
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endif
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@ -0,0 +1,3 @@
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dsdt.aml
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dsdt.asl.tmp
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dsdt.c
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@ -0,0 +1,28 @@
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if TARGET_SOM_DB5800_SOM_6867
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config SYS_BOARD
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default "som-db5800-som-6867"
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config SYS_VENDOR
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default "advantech"
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config SYS_SOC
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default "baytrail"
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config SYS_CONFIG_NAME
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default "som-db5800-som-6867"
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config SYS_TEXT_BASE
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default 0xfff00000 if !EFI_STUB
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default 0x01110000 if EFI_STUB
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select X86_RESET_VECTOR if !EFI_STUB
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select INTEL_BAYTRAIL
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select BOARD_ROMSIZE_KB_8192
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config PCIE_ECAM_BASE
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default 0xe0000000
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endif
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@ -0,0 +1,7 @@
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Advantech SOM-DB5800-SOM-6867
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M: George McCollister <george.mccollister@gmail.com>
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S: Maintained
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F: board/advantech/som-db5800-som-6867
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F: include/configs/som-db5800-som-6867.h
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F: configs/som-db5800-som-6867_defconfig
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F: arch/x86/dts/baytrail_som-db5800-som-6867.dts
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@ -0,0 +1,8 @@
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#
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# Copyright (C) 2015, Google, Inc
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += som-db5800-som-6867.o start.o
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obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
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@ -0,0 +1,11 @@
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Power Button */
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Device (PWRB)
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{
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Name(_HID, EISAID("PNP0C0C"))
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}
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@ -0,0 +1,14 @@
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/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
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{
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/* platform specific */
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#include <asm/arch/acpi/platform.asl>
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/* board specific */
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#include "acpi/mainboard.asl"
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}
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@ -0,0 +1,24 @@
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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* Copyright (C) 2016 George McCollister <george.mccollister@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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int board_early_init_f(void)
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{
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/*
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* The FSP enables the BayTrail internal legacy UART (again).
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* Disable it again, so that the one on the EC can be used.
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*/
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setup_internal_uart(0);
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return 0;
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}
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int arch_early_init_r(void)
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{
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return 0;
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}
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@ -0,0 +1,9 @@
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/*
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* Copyright (C) 2015, Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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.globl early_board_init
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early_board_init:
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jmp early_board_init_ret
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@ -0,0 +1,61 @@
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CONFIG_X86=y
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CONFIG_VENDOR_ADVANTECH=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="baytrail_som-db5800-som-6867"
|
||||
CONFIG_TARGET_SOM_DB5800_SOM_6867=y
|
||||
CONFIG_HAVE_INTEL_ME=y
|
||||
CONFIG_ENABLE_MRC_CACHE=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_HAVE_VGA_BIOS=y
|
||||
CONFIG_GENERATE_PIRQ_TABLE=y
|
||||
CONFIG_GENERATE_MP_TABLE=y
|
||||
CONFIG_GENERATE_ACPI_TABLE=y
|
||||
CONFIG_SEABIOS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_SIGNATURE=y
|
||||
CONFIG_BOOTSTAGE=y
|
||||
CONFIG_BOOTSTAGE_REPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_CPU=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
# CONFIG_CMD_MMC is not set
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
# CONFIG_CMD_NFS is not set
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_BOOTSTAGE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CPU=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_RTC=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DEBUG_UART_BASE=0x3f8
|
||||
CONFIG_DEBUG_UART_CLOCK=1843200
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_ICH_SPI=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_VIDEO_VESA=y
|
||||
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
|
||||
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
|
||||
CONFIG_USE_PRIVATE_LIBGCC=y
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Google, Inc
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <configs/x86-common.h>
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_ARCH_EARLY_INIT_R
|
||||
#define CONFIG_ARCH_MISC_INIT
|
||||
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd,vga\0" \
|
||||
"stdout=serial,vga\0" \
|
||||
"stderr=serial,vga\0"
|
||||
|
||||
#define CONFIG_SCSI_DEV_LIST \
|
||||
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
|
||||
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
|
||||
|
||||
#define VIDEO_IO_OFFSET 0
|
||||
#define CONFIG_X86EMU_RAW_IO
|
||||
|
||||
#define CONFIG_ENV_SECT_SIZE 0x1000
|
||||
#define CONFIG_ENV_OFFSET 0x006ef000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue