Commit Graph

1851 Commits

Author SHA1 Message Date
Kieran Bingham
a5b04d00bf sh: Fix up rsk7203 target for out of tree build
Fix up rsk7203 target to build successfully using out-of-tree build.

Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2009-01-16 10:22:27 +09:00
Wolfgang Denk
e92c9a860e cpu/mpc824x/Makefile: fix warning with parallel builds
Parallel builds would occasionally issue this build warning:

    ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists

Use "ln -sf" as quick work around for the issue.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-01-14 22:35:30 +01:00
Wolfgang Denk
5f01ea63a6 Merge branch 'master' of /home/wd/git/u-boot/custodians 2009-01-14 00:27:06 +01:00
Haiying Wang
950264317e Change DDR tlb start entry to CONFIG param for 85xx
So that we can locate the DDR tlb start entry to the value other than 8. By
default, it is still 8.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2009-01-13 16:47:07 -06:00
Wolfgang Denk
a9f3acbcd0 MPC86xx: fix build warnings
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-01-12 14:50:35 +01:00
Jean-Christophe PLAGNIOL-VILLARD
3dd9395a0d at91rm9200: move define from lowlevel_init to header
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-06 21:41:59 +01:00
Jean-Christophe PLAGNIOL-VILLARD
d481c80d78 at91rm9200: rename lowlevel init value to CONFIG_SYS_
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-01-06 21:37:39 +01:00
Trent Piepho
ada591d2a0 mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.

This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.

The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.

get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.

checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:32:49 -06:00
Trent Piepho
9863d6aca1 mpc86xx: Double local bus clock divider
The local bus clock divider should be doubled for both 8610 and 8641.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:32:48 -06:00
Trent Piepho
446c381e3e mpc8568: Double local bus clock divider
The clock divider for the MPC8568 local bus should be doubled, like the
other newer MPC85xx chips.

Since there are now more chips with a 2x divider than a 1x, and any new
85xx chips will probably be 2x, invert the sense of the #if so that it
lists the 1x chips instead of the 2x ones.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:32:48 -06:00
Dave Liu
f51f07eb58 85xx: Fix the boot window issue
If one custom board is using the 8MB flash, it is set
as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000.
The current start.S code will be broken at switch_as.

It is because the TLB1[15] is set as 16MB page size,
EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000.

For the 8MB flash case, the EPN = 0xefxxxxxx,
RPN = 0xffxxxxxx. Assume the virt address of switch_as
is 0xef7ff18c, the real address of the instruction at
switch_as should be 0xff7ff18c. the 0xff7ff18c is out
of the range of the default 8MB boot LAW window
0xff800000 - 0xffffffff.

So when we switch to AS1 address space at switch_as,
the core can't fetch the instruction at switch_as any
more. It will cause broken issue.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-12-19 18:32:48 -06:00
Haiying Wang
181a365011 Set IVPR to kenrel entry point in second core boot page
Assuming the OSes exception vectors start from the base of kernel address, and
the kernel physical starting address can be relocated to an non-zero address.
This patch enables the second core to have a valid IVPR for debugger before
kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid
value for second core which runs kernel at different physical address other
than 0x0.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-12-19 18:32:41 -06:00
Trent Piepho
a5d212a263 mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.

In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems.  It
should be safe as the fifth bit was defined as reserved and set to 0.

Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:20:25 -06:00
Trent Piepho
58ec4866ed mpc8[56]xx: Put localbus clock in device tree
Export the localbus frequency in the device tree, the same way the CPU, TB,
CCB, and various other frequencies are exported in their respective device
tree nodes.

Some localbus devices need this information to be programed correctly, so
it makes sense to export it along with the other frequencies.

Unfortunately, when someone wrote the localbus dts bindings, they didn't
bother to define what the "compatible" property should be.  So it seems no
one was quite sure what to put in their dts files.

Based on current existing dts files in the kernel source, I've used
"fsl,pq3-localbus" and "fsl,elbc" for MPC85xx, which are used by almost all
of the 85xx devices, and are looked for by the Linux code.  The eLBC is
apparently not entirely backward compatible with the pq3 LBC and so eLBC
equipped platforms like 8572 won't use pq3-localbus.

For MPC86xx, I've used "fsl,elbc" which is used by some of the 86xx systems
and is also looked for by the Linux code.  On MPC8641, I've also used
"fsl,mpc8641-localbus" as it is also commonly used in dts files, some of
which don't use "fsl,elbc" or any other acceptable name to match on.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:20:20 -06:00
Kumar Gala
ecf5b98c7a 85xx: Add support to populate addr map based on TLB settings
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-19 18:20:08 -06:00
Wolfgang Denk
455ae7e87f Coding style cleanup, update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-12-16 01:02:17 +01:00
Timur Tabi
ecf5f077c8 i2c: merge all i2c_reg_read() and i2c_reg_write() into inline functions
All implementations of the functions i2c_reg_read() and
i2c_reg_write() are identical. We can save space and simplify the
code by converting these functions into inlines and putting them in
i2c.h.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-By: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-12-15 23:46:21 +01:00
Jean-Christophe PLAGNIOL-VILLARD
3aed3aa2c1 Fix new found CFG_
Also fix some minor typos.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-12-14 10:55:30 +01:00
Sergei Poselenov
0e0c862efe Remove compiler warning: target CPU does not support interworking
This warning is issued by modern ARM-EABI GCC on non-thumb targets.

Signed-off-by: Vladimir Panfilov <pvr@emcraft.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-12-13 23:41:23 +01:00
Wolfgang Denk
3680aed04f Merge branch 'master' of git://git.denx.de/u-boot-mips 2008-12-13 00:34:12 +01:00
Stefan Roese
71fa0714fe MIPS: Flush data cache upon relocation
This patch now adds a flush to the data cache upon relocation. The
current implementation is missing this. Only a comment states that it
should be done. So let's really do it now.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-12-10 23:29:12 +09:00
Stefan Roese
4417434368 MIPS: Add CONFIG_SKIP_LOWLEVEL_INIT
This patch adds the CONFIG_SKIP_LOWLEVEL_INIT option to start.S. This
enables support for boards where the lowlevel initialization is
already done when U-Boot runs (e.g. via OnChip ROM).

This will be used in the upcoming VCTH board support.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-12-10 23:29:09 +09:00
Nobuhiro Iwamatsu
e9d5f35497 sh: Update sh timer function
Change to write/readX function and fix timer problem.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-12-10 23:11:35 +09:00
Ben Warren
2145188bea Fix compile error in building MBX860T.
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-12-10 09:26:42 +01:00
Graeme Russ
1f5070c0c1 Fixed path to sc520 SSI include file
Signed Off By: Graeme Russ <graeme.russ@gmail.com>
2008-12-10 00:34:09 +01:00
Anatolij Gustschin
ee2e9ba917 video: fix FADS823 and RRvision compiling issues
Since commit 561858ee building for FADS823 and RRvision
doesn't work. Let's include version.h and timestamp.h
unconditionally to fix the problem.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-12-09 17:52:05 +01:00
Wolfgang Denk
13d36ec849 Merge branch 'master' of git://git.denx.de/u-boot-at91 2008-12-09 01:06:14 +01:00
Trent Piepho
5e3ab68e9a Section name should be ".data", not "data"
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-12-09 00:48:41 +01:00
Peter Tyser
561858ee7d Update U-Boot's build timestamp on every compile
Use the GNU 'date' command to auto-generate a new U-Boot
timestamp on every compile.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-12-06 23:36:43 +01:00
Remy Bohmer
83ad179e2f Remove redundant armv4 flag from arm926ejs compile flags
Currently the arm926ejs tree has the armv4 option set during compilation.
This flag does not belong here because a arm926 CPU is always a armv5 CPU.

Signed-off-by: Remy Bohmer <linux@bohmer.net>
2008-12-06 20:34:12 +01:00
Wolfgang Denk
90665e3d97 Merge branch 'master' of git://git.denx.de/u-boot-at91 2008-12-05 00:27:19 +01:00
Kumar Gala
9df59533f7 85xx: init gd as early as possible
Moved up the initialization of GD so C code like set_tlb() can use
gd->flags to determine if we've relocated or not in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-12-04 03:15:43 -06:00
Kumar Gala
aed461af81 85xx: Fix relocation of CCSRBAR
If the virtual address for CCSRBAR is the same after relocation but
the physical address is changing we'd end up having two TLB entries with
the same VA.  Instead we new us the new CCSRBAR virt address + 4k as a
temp virt address to access the old CCSRBAR to relocate it.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-12-04 03:15:43 -06:00
Peter Tyser
9427ccde03 85xx: Add PORDEVSR_PCI1 define
Add define used to determine if PCI1 interface is in PCI or PCIX mode.

Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-12-04 03:15:43 -06:00
Ed Swarthout
7008d26a40 fsl ddr skip interleaving if not supported.
Removed while(1) hang if memctl_intlv_ctl is set wrong.
Remove embedded tabs from strings.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-12-03 22:47:19 -06:00
Peter Tyser
a2cd50ed6e 85xx: Add CPU 2 errata workaround to all 8548 boards
All mpc8548-based boards should implement the suggested workaround
to CPU 2 errata. Without the workaround, its possible for the
8548's core to hang while executing a msync or mbar 0 instruction
and a snoopable transaction from an I/O master tagged to make
quick forward progress is present.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-12-03 22:46:42 -06:00
Jean-Christophe PLAGNIOL-VILLARD
ed3b18e05c AT91: remove non supported board AT91RM9200DF macro
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-12-02 21:59:29 +01:00
Wolfgang Denk
06efc122a0 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2008-11-25 11:47:41 +01:00
Wolfgang Denk
58c696eed8 AT91RM9200DK: fix broken boot from NOR flash
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-11-24 22:10:07 +01:00
Jens Scharsig
8052352f20 at91rm9200: fix broken boot from nor flash
This patch fix the broken boot from NOR Flash on AT91RM9200 boards, if
CONFIG_AT91RM9200 is defined and nor preloader is used.

Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
2008-11-24 22:10:04 +01:00
Dave Mitchell
ddf45cc758 ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initialization
Expanded OCM TLB to allow access to 64K OCM as well as 256K of
internal SRAM.

Adjusted internal SRAM initialization to match updated user
manual recommendation.

OCM & ISRAM are now mapped as follows:
        physical        virtual         size
ISRAM   0x4_0000_0000   0xE300_0000     256k
OCM     0x4_0004_0000   0xE304_0000     64k

A single TLB was used for this mapping.

Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-11-21 11:02:04 +01:00
Dave Mitchell
b14ca4b61a ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRs
Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
L2 cache DCRs from ppc440.h to this new header.

Also converted these DCR defines from lowercase to uppercase and
modified referencing modules to use them.

Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-11-21 10:52:33 +01:00
Stelian Pop
3e0cda071a AT91: Enable PLLB for USB
At least some (old ?) versions of the AT91Bootstrap do not set up the
PLLB correctly to 48 MHz in order to make USB host function correctly.

This patch sets up the PLLB to the same values Linux uses, and makes USB
work ok on the following CPUs:
	- AT91CAP9
	- AT91SAM9260
	- AT91SAM9263

This patch also defines CONFIG_USB_STORAGE and CONFIG_CMD_FAT for all
the relevant AT91CAP9/AT91SAM9 atmel boards.

Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-11-21 01:41:14 +01:00
Stefan Roese
25fb4eaaea ppc4xx: Clear all potentially pending exceptions in MCSR
This is needed on Canyonlands which still has an exception pending
while running relocate_code(). This leads to a failure after trap_init()
is moved to the top of board_init_r().

Signed-off-by: Stefan Roese <sr@denx.de>
2008-11-20 11:48:53 +01:00
Selvamuthukumar
9b827cf172 Align end of bss by 4 bytes
Most of the bss initialization loop increments 4 bytes
at a time. And the loop end is checked for an 'equal'
condition. Make the bss end address aligned by 4, so
that the loop will end as expected.

Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-11-18 23:13:16 +01:00
Wolfgang Denk
e0b0ec8430 Merge branch 'master' of git://git.denx.de/u-boot-mpc86xx 2008-11-18 21:40:38 +01:00
Becky Bruce
3111d32c49 mpc8641: Support 36-bit physical addressing
This patch creates a memory map with all the devices
in 36-bit physical space, in addition to the 32-bit map.
The CCSR relocation is moved (again, sorry) to
allow for the physical address to be 36 bits - this
requires translation to be enabled.  With 36-bit physical
addressing enabled, we are no longer running with VA=PA
translations.  This means we have to distinguish between
the two in the config file.  The existing region name is
used to indicate the virtual address, and a _PHYS variety
is created to represent the physical address.

Large physical addressing is not enabled by default.
Set CONFIG_PHYS_64BIT in the config file to turn this on.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-11-10 10:10:05 -06:00
Becky Bruce
c759a01a00 mpc8641: Change 32-bit memory map
The memory map on the 8641hpcn is modified to look more like
the 85xx boards; this is a step towards a more standardized
layout going forward. As part of this change, we now relocate
the flash.

The regions for some of the mappings were far larger than they
needed to be.  I have reduced the mappings to match the
actual sizes supported by the hardware.

In addition I have removed the comments at the head
of the BAT blocks in the config file, rather than updating
them.  These get horribly out of date, and it's a simple
matter to look at the defines to see what they are set to
since everything is right here in the same file.

Documentation has been changed to reflect the new map, as this
change is user visible, and affects the OS which runs post-uboot.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-11-10 10:10:04 -06:00
Becky Bruce
bf9a8c3430 mpc86xx: Change early FLASH mapping to 1M at CONFIG_MONITOR_BASE_EARLY
We define CONFIG_MONITOR_BASE_EARLY to define the initial location
of the bootpage in flash.   Use this to create an early mapping
definition for the FLASH, and change the early_bats code to use this.

This  change facilitates the relocation of the flash since the early
mappings are no longer tied to the final location of the flash.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-11-10 10:10:04 -06:00
Becky Bruce
c1e1cf6954 mpc86xx: Use SRR0/1/rfi to enable address translation, not blr
Using a mtmsr/blr means that you have to be executing at the
same virtual address once you enable translation.  This is
unnecessarily restrictive, and is not really how this is
usually done.  Change it to use the more common mtspr SRR0/SRR1
and rfi method.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-11-10 10:10:03 -06:00