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https://github.com/brain-hackers/u-boot-brain
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ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRs
Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and L2 cache DCRs from ppc440.h to this new header. Also converted these DCR defines from lowercase to uppercase and modified referencing modules to use them. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Dave Mitchell
Stefan Roese
parent
711e2b2af8
commit
b14ca4b61a
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@ -25,6 +25,7 @@
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#include <command.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <asm/ppc4xx-isram.h>
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#include <spd_sdram.h>
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#include "epld.h"
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@ -255,7 +256,7 @@ static int on_off( const char *s )
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************************************************************************/
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static void l2cache_disable(void)
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{
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mtdcr( l2_cache_cfg, 0 );
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mtdcr( L2_CACHE_CFG, 0 );
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}
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@ -265,24 +266,24 @@ static void l2cache_disable(void)
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************************************************************************/
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static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
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{
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mtdcr( l2_cache_cfg, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
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mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
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mtdcr( l2_cache_addr, 0 ); /* set L2_ADDR with all zeros */
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mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */
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mtdcr( l2_cache_cmd, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
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mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
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while (!(mfdcr( l2_cache_stat ) & 0x80000000 )) ;; /* poll L2_SR for completion */
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while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ;; /* poll L2_SR for completion */
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mtdcr( l2_cache_cmd, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
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mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
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mtdcr( l2_cache_cmd, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
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mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
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mtdcr( l2_cache_snp0, 0 ); /* snoop registers */
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mtdcr( l2_cache_snp1, 0 );
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mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */
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mtdcr( L2_CACHE_SNP1, 0 );
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__asm__ volatile ("sync"); /* msync */
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mtdcr( l2_cache_cfg, 0xe0000000 ); /* inst and data use L2 */
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mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */
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__asm__ volatile ("sync");
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}
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@ -294,7 +295,7 @@ static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
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************************************************************************/
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static int l2cache_status(void)
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{
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return (mfdcr( l2_cache_cfg ) & 0x60000000) != 0;
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return (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0;
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}
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@ -72,6 +72,7 @@
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <asm/ppc4xx-isram.h>
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#ifndef CONFIG_IDENT_STRING
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#define CONFIG_IDENT_STRING ""
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@ -679,65 +680,65 @@ _start:
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_460SX)
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mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
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mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
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#endif
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lis r2,0x7fff
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ori r2,r2,0xffff
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mfdcr r1,isram0_dpc
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mfdcr r1,ISRAM0_DPC
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and r1,r1,r2 /* Disable parity check */
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mtdcr isram0_dpc,r1
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mfdcr r1,isram0_pmeg
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mtdcr ISRAM0_DPC,r1
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mfdcr r1,ISRAM0_PMEG
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and r1,r1,r2 /* Disable pwr mgmt */
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mtdcr isram0_pmeg,r1
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mtdcr ISRAM0_PMEG,r1
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lis r1,0x8000 /* BAS = 8000_0000 */
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#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
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ori r1,r1,0x0980 /* first 64k */
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mtdcr isram0_sb0cr,r1
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mtdcr ISRAM0_SB0CR,r1
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lis r1,0x8001
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ori r1,r1,0x0980 /* second 64k */
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mtdcr isram0_sb1cr,r1
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mtdcr ISRAM0_SB1CR,r1
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lis r1, 0x8002
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ori r1,r1, 0x0980 /* third 64k */
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mtdcr isram0_sb2cr,r1
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mtdcr ISRAM0_SB2CR,r1
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lis r1, 0x8003
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ori r1,r1, 0x0980 /* fourth 64k */
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mtdcr isram0_sb3cr,r1
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mtdcr ISRAM0_SB3CR,r1
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#elif defined(CONFIG_440SPE)
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lis r1,0x0000 /* BAS = 0000_0000 */
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ori r1,r1,0x0984 /* first 64k */
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mtdcr isram0_sb0cr,r1
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mtdcr ISRAM0_SB0CR,r1
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lis r1,0x0001
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ori r1,r1,0x0984 /* second 64k */
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mtdcr isram0_sb1cr,r1
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mtdcr ISRAM0_SB1CR,r1
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lis r1, 0x0002
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ori r1,r1, 0x0984 /* third 64k */
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mtdcr isram0_sb2cr,r1
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mtdcr ISRAM0_SB2CR,r1
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lis r1, 0x0003
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ori r1,r1, 0x0984 /* fourth 64k */
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mtdcr isram0_sb3cr,r1
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mtdcr ISRAM0_SB3CR,r1
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#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
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lis r1,0x4000 /* BAS = 8000_0000 */
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ori r1,r1,0x4580 /* 16k */
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mtdcr isram0_sb0cr,r1
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mtdcr ISRAM0_SB0CR,r1
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#elif defined(CONFIG_460SX)
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lis r1,0x0000 /* BAS = 0000_0000 */
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ori r1,r1,0x0B84 /* first 128k */
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mtdcr isram0_sb0cr,r1
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mtdcr ISRAM0_SB0CR,r1
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lis r1,0x0001
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ori r1,r1,0x0B84 /* second 128k */
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mtdcr isram0_sb1cr,r1
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mtdcr ISRAM0_SB1CR,r1
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lis r1, 0x0002
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ori r1,r1, 0x0B84 /* third 128k */
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mtdcr isram0_sb2cr,r1
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mtdcr ISRAM0_SB2CR,r1
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lis r1, 0x0003
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ori r1,r1, 0x0B84 /* fourth 128k */
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mtdcr isram0_sb3cr,r1
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mtdcr ISRAM0_SB3CR,r1
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#elif defined(CONFIG_440GP)
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ori r1,r1,0x0380 /* 8k rw */
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mtdcr isram0_sb0cr,r1
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mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
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mtdcr ISRAM0_SB0CR,r1
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mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
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#endif
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#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
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75
include/asm-ppc/ppc4xx-isram.h
Normal file
75
include/asm-ppc/ppc4xx-isram.h
Normal file
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@ -0,0 +1,75 @@
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/*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _PPC4xx_ISRAM_H_
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#define _PPC4xx_ISRAM_H_
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/*
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* Internal SRAM
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*/
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define ISRAM0_DCR_BASE 0x380
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#else
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#define ISRAM0_DCR_BASE 0x020
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#endif
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#define ISRAM0_SB0CR (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
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#define ISRAM0_SB1CR (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
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#define ISRAM0_SB2CR (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
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#define ISRAM0_SB3CR (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
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#define ISRAM0_BEAR (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
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#define ISRAM0_BESR0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
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#define ISRAM0_BESR1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
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#define ISRAM0_PMEG (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
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#define ISRAM0_CID (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
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#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
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#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define ISRAM1_DCR_BASE 0x0B0
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#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/
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#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */
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#define ISRAM1_BESR0 (ISRAM1_DCR_BASE+0x05) /* SRAM1 bus error status reg 0 */
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#define ISRAM1_BESR1 (ISRAM1_DCR_BASE+0x06) /* SRAM1 bus error status reg 1 */
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#define ISRAM1_PMEG (ISRAM1_DCR_BASE+0x07) /* SRAM1 power management */
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#define ISRAM1_CID (ISRAM1_DCR_BASE+0x08) /* SRAM1 bus core id reg */
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#define ISRAM1_REVID (ISRAM1_DCR_BASE+0x09) /* SRAM1 bus revision id reg */
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#define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */
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#endif /* CONFIG_460EX || CONFIG_460GT */
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/*
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* L2 Cache
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*/
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#if defined (CONFIG_440GX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_460SX)
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#define L2_CACHE_BASE 0x030
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#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */
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#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */
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#define L2_CACHE_ADDR (L2_CACHE_BASE+0x02) /* L2 Cache Address */
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#define L2_CACHE_DATA (L2_CACHE_BASE+0x03) /* L2 Cache Data */
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#define L2_CACHE_STAT (L2_CACHE_BASE+0x04) /* L2 Cache Status */
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#define L2_CACHE_CVER (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
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#define L2_CACHE_SNP0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
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#define L2_CACHE_SNP1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
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#endif /* CONFIG_440GX */
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#endif /* _PPC4xx_ISRAM_H_ */
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@ -607,45 +607,6 @@
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#endif /* 440EP || 440GR || 440EPX || 440GRX */
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/*-----------------------------------------------------------------------------
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| L2 Cache
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+----------------------------------------------------------------------------*/
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#if defined (CONFIG_440GX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_460SX)
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#define L2_CACHE_BASE 0x030
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#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
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#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
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#define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */
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#define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */
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#define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */
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#define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
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#define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
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#define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
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#endif /* CONFIG_440GX */
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/*-----------------------------------------------------------------------------
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| Internal SRAM
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+----------------------------------------------------------------------------*/
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define ISRAM0_DCR_BASE 0x380
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#else
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#define ISRAM0_DCR_BASE 0x020
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#endif
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#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
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#define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
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#define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
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#define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
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#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
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#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
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#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
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#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
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#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
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#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
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#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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