This commit avoids generating ./SPL twice.
- Fist time descending to spl/
- Second time as a prerequisite of u-boot-with-spl.imx,
u-boot-with-nand-spl.imx.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Rename OBJCFLAGS to OBJCOPYFLAGS beforehand to use
"cmd_objcopy" in scripts/Makefile.lib in an upcoming commit.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Add bcm281xx architecture support code including a clock framework and
chip reset. Define register block base addresses for the bcm281xx
architecture and create an empty gpio header file required when
CONFIG_CMD_GPIO is set.
Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Reviewed-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Tim Kryger <tkryger@linaro.org>
The Kona architecture is present on a number of Broadcom mobile SoCs
including the bcm281xx family of chips.
Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Reviewed-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Tim Kryger <tkryger@linaro.org>
The function pll_sigma_delta_val uses "float" data which is not correct.
The exact "why" of this mangling is lost to history, but this changes us
to equivalent non-FP math to get the same results.
Reported-by: Wolfgang Denk <wd@denx.de>
Acked-by: Matt Porter <mporter@linaro.org>
commit 194dd74ad9
(DRA7: add ABB setup for MPU voltage domain)
Made an offset typo error by using 0x4A003B24 as the efuse offset
for OPP_NOM. As per TI documentation, 0x4A003B24 is for OPP_OD, and
0x4A003B20 is for OPP_NOM. Fix the same.
Reported-by: Praveen Rao <prao@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Schematic indicates GPIO5_7 is to be used for VTT regulator control
rather than GPIO0_21 so modify enable_vtt_regulator to reflect this.
Without this some boards will experience DDR3 corruption and fail to
boot.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[trini: Rework patch against mainline]
Signed-off-by: Tom Rini <trini@ti.com>
Conflicts:
Makefile
drivers/net/npe/Makefile
These two conflicts arise from commit 0b2d3f20
("ARM: NET: Remove the IXP NPE ethernet driver") and are
resolved by deleting the drivers/net/npe/Makefile file
and removing the CONFIG_IXP4XX_NPE line from Makefile.
In Kbuild, every makefile must have non-empty obj- or obj-y.
Otherwise, built-in.o will not be created and the link stage
will fail.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
If the whole code is surrounded by #ifdef(CONFIG_ ) .. #endif,
it should be moved to Makefile.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
- When CONFIG_DISPLAY_CPUINFO is not enabled,
print_cpuinfo() should be defined as an empty function
in a header, include/common.h
- Remove #ifdef CONFIG_DISPLAY_CPUINFO .. #endif
from caller, common/board_f.c and arch/arm/lib/board.c
- Remove redundant prototypes in arch/arm/lib/board.c,
arch/arm/include/asm/arch-am33x/sys_proto.h and
board/nokia/rx51/rx51.h, keeping the one in include/common.h
- Add #ifdef CONFIG_DISPLAY_CPUINFO to the func definition
where it is missing
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
We are going to switch over to Kbuild in upcoming commits.
Each makefile must have non-empty obj- or obj-y
to generate built-in.o on Kbuild.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit changes the working directory
where the build process occurs.
Before this commit, build process occurred under the source
tree for both in-tree and out-of-tree build.
That's why we needed to add $(obj) prefix to all generated
files in makefiles like follows:
$(obj)u-boot.bin: $(obj)u-boot
Here, $(obj) is empty for in-tree build, whereas it points
to the output directory for out-of-tree build.
And our old build system changes the current working directory
with "make -C <sub-dir>" syntax when descending into the
sub-directories.
On the other hand, Kbuild uses a different idea
to handle out-of-tree build and directory descending.
The build process of Kbuild always occurs under the output tree.
When "O=dir/to/store/output/files" is given, the build system
changes the current working directory to that directory and
restarts the make.
Kbuild uses "make -f $(srctree)/scripts/Makefile.build obj=<sub-dir>"
syntax for descending into sub-directories.
(We can write it like "make $(obj)=<sub-dir>" with a shorthand.)
This means the current working directory is always the top
of the output directory.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Gerhard Sittig <gsi@denx.de>
Add the SATA boot support for OMAP5 and dra7xx.
Renamed the omap_sata_init to the common init_sata(int dev)
for commonality in with sata stack.
Added the ROM boot device ID for SATA.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Typecast the argument with unsigned long long
for proper calculation of lldiv
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
SPL is using ps7_init.c/h files which are generated
from design tools which have to be copied to
boards/xilinx/zynq folder before compilation.
BSS section is moved to SDRAM because fat support
requires more space than SRAM size.
Added:
- MMC and QSPI support
- Boot OS directly from SPL
- Enable SPL command
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
Remove hard coded clock divider setting and use the Zynq clock framework
to dynamically calculate appropriate dividers at run time.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The GEM driver should not need to know about Zynq specific details of
RCLK related registers and bitfields in the SLCR. Move those details to
the slcr driver.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Cortex-A9 MPCore TRM' from ARM (ARM DDI 0407G ID072711) describes
in the section 4.1.1 how this value calculation should be done.
This patch fixes the problem if network activity such as ping or
tftp is attempted after u-boot has been idle for an hour,
it hangs, and cannot control-C out of it.
Signed-off-by: Uday Hegde <udayh@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch is here because of:
"arm: keep all sections in ELF file"
(sha1: 47ed5dd031)
Our tools expect to have elf with only LOAD header.
Without this fix also PHDR, INTERP and DYNAMIC headers
are available in ELF.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The entries in config.mk were needed so that U-Boot could be built
with an old version of the Raspberry Pi Foundation's toolchain. Without
them, the build would error out with:
...-ld: error: .../libgcc.a(_bswapsi2.o) uses VFP register arguments,
u-boot does not
However, none of the 3 toolchains in the latest version of their
tools.git, nor the Ubuntu/Linaro ARM compilers in at least Ubuntu Quantal
or Saucy, need these options set in order to compile a working U-Boot.
Hence, remove the options for simplicity.
Reported-by: Tom Rini <trini@ti.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
imx_get_fecclk() returns enet_ref instead of ipg.
Since the clock is used to calculate the prescaler
for the MDIO interface wrong values can be calculated.
Tested on a custom MX6S board with 100MBit interface
Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Currently when we boot a mx6dual U-boot reports that it is a mx6quad.
Report it as MX6D instead:
CPU: Freescale i.MX6D rev1.2 at 792 MHz
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Boot ROM may mask MMDC_CHx_MASK in CCM_CCDR(such as i.MX6SL TO1.2),
it will cause warm reset fail, need to clear this MMDC_CHx_MASK field
to make sure all the i.MX6 series SOCs reset function work. Otherwise,
uboot "reset" command will fail, tested on i.MX6SL EVK board with TO1.2.
Signed-off-by: Anson Huang <b20788@freescale.com>
For low freq boot mode(ARM boot up with 396MHz), ROM
will not set AHB clock to 132MHz, and the reset value of
AHB divider is incorrect which will lead to wrong AHB
rate, need to correct it. To enable low freq boot mode,
need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL
SabreSD board and i.MX6SL EVK board.
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
Use setbits/clrbits macro instead of readl/writel function.
(Suggested by Wolfgang)
Signed-off-by: Inha Song <ideal.song@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch fixed that cfg value is set to wrong value.
Because it didn't read the related register.
Signed-off-by: Inha Song <ideal.song@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
We use the switch CONFIG_SUPPORT_EMMC_BOOT today to enable some
additional features of the eMMC boot partitions. Add support for being
told that we have booted from one of these partitions to the spl
framework and implement this on TI OMAP/related.
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
The architecture is unmaintained and dead, remove it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michael Schwingen <michael@schwingen.org>
Cc: Tom Rini <trini@ti.com>
Because of the list of peripherals is not sequential,
such a routine does not check for valid correctly.
Error check will be done when call the exynos_pinmux_config function.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
These files are used by both SPL and main U-Boot.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
These files are for code that runs on the CPU (A15) on Tegra124 boards.
At this time, there is no A15-specific code here. The warmboot/LP0 files
aren't included as that code hasn't been ported yet.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This provides SPL support for Tegra124 boards - AVP early init, plus
CPU (A15) init/jump to main U-Boot.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
There's already an SoC-specific conditional in cpu.h to determine the
PLLP rate. Define the CSITE clock rate inside the same conditional, so
that we can remove a conditional from clock_enable_coresight(). This
means one less place to update the code for new SoCs.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This programming sequence is correct per Jimmy Zhang, and makes sense
too!
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Pass just the partition ID to power_partition(), rather than also passing
the partition's status register mask too. This makes it simpler to get
call-sites correct, since they don't need to pass two different values
that define the same thing and must match.
Consequently, we can remove the mask definitions from pmc.h.
Suggested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Use a named constant for the PLL lock bit in enable_cpu_clocks().
Construct the complete value of pmc_pwrgate_toggle, rather than doing a
read-modify-write; the register is simple enough and doesn't need to
maintain state between operations.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Based on the Tegra TRM, the system clock (which is the AVP clock) can
run up to 275MHz. On power on, the default sytem clock source is set to
PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to
408MHz which is beyond system clock's upper limit.
The fix is to set the system clock to CLK_M before initializing PLLP,
and then switch back to PLLP_OUT4, which has an appropriate divider
configured, after PLLP has been configured
Implement this logic in new function tegra30_set_up_pllp(),
which sets up PLLP and all PLLP_OUT* dividers, and handles the AVP
clock switching. Remove the duplicate PLLP setup from pllx_set_rate()
and adjust_pllp_out_freqs().
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
[swarren, significantly refactored the change]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra114 and later's PMC module removes the pwrgate_timer_on register
and replaces it with a clamp_status register. Adjust pmc.h to reflect
this, and update any code affected by the change.
The cpu.c change in this patch was extracted from a much larger patch
by Jimmy Zhang. The pmc.h change was written from scratch, but inspired
by related changes made by Tom Warren.
There could well be other differences in the PMC register set for chips
after Tegra20/30. However, they don't affect the code in U-Boot at
present, so I haven't attempted an exhaustive update of pmc.h.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Some clock sources have 3-bit muxes in bits 31:29. Implement core
support for this mux field.
Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Not all code that set or interpreted "mux_bits" was using the named
macros, but rather some was simply using hard-coded integer constants.
This makes it hard to determine which pieces of code are affected by
changes to those constants.
Replace the integer constants with the equivalent macro definitions so
that everything is nicely tied together.
Note that I'm not convinced all the code was using the correct integer
constants, and hence I'm not convinced that all the code is now using
the desired macros. However, this change is a purely mechanical
replacement and should have no functional change. Fixing any bugs will
come later, separately.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
OUT_CLK_SOURCE_ are currently named after the number of bits the mask
they represent includes. However, bit count is not the only possible
variable; bit position may also vary. Rename OUT_CLK_SOURCE_ to
OUT_CLK_SOURCE_31_30_ and OUT_CLK_SOURCE4_ to OUT_CLK_SOURCE_31_28 to
more completely describe exactly what they represent, without having to
go look up the definitions.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The only place where the MASK_BITS_* values are used is in
adjust_periph_pll(), which interprets the value 4 (old MASK_BITS_29_28,
new MASK_BITS_31_28) as being associated with mask OUT_CLK_SOURCE4_MASK,
i.e. bits 31:28. Rename the MASK_BITS_ macro to reflect how it's actually
implemented.
Note that no Tegra clock register actually uses all of bits 31:28 as
the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
those cases, nothing is stored in the bits above the mux field, so it's
safe to pretend that the mux field extends all the way to the end of the
register. As such, the U-Boot clock driver is currently a bit lazy, and
doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
them all together and pretends they're all 31:28. This patch doesn't
cause this issue; it was pre-existing. Hopefully, future patches will
clean this up.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The enum used to define the set of register bits used to represent a
clock's input mux, MUX_BITS_*, is defined separately for each SoC at
present. Move this definition to a common location to ease fixing up
some issues with the definition, and the code that uses it.
Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
For Tegra20, the SKU ID actually impacts how U-Boot programs the chip,
and hence we need to explicitly know about each and every SKU ID in order
to operate correctly.
However, for Tegra30/114, this isn't the case. Rather than forcing each
new user with a different SKU to manually add their SKU ID into the code,
simply accept any SKU ID.
If U-Boot ever starts e.g. programming maximal CPU clocks etc., we'll
need to undo this, or make the default case map to conservative defaults,
but for now it's likely the path to least support cost.
Reported-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Split the SATA clock enabling function and add PCI express clock
enabling function. The SATA clock enabling function starts up the
100MHz SATA reference PLL in ENET_PLL register, but the code can
be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull
this code into separate function. Moreover, add the PCIe clock
enabling code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Make indirect vectors addresses global, so they can be replaced by
various code that needs to do so. For example the MX6 PCI express
driver needs to temporarily replace data abort handler when reading
the config space.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Before this commit, all arch/arm/cpu/${CPU}/config.mk except ARMv8
had the same option:
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
This commit moves it into arch/arm/config.mk.
If the compiler does not support the option,
it is ignored by $(call cc-option,...).
So this commit gives no harm to ARMv8.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
If timer_init() is made a weak stub function, then it allows us to
remove several empty timer_init functions for those boards that
already have a timer initialized when u-boot starts. Architectures
that use the timer framework may also remove the need for timer.c.
Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Patch adds modification to shared omap5 abb_setup() function, and
proper registers definitions needed for ABB setup sequence. ABB is
initialized for MPU voltage domain at OPP_NOM.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support
for ES1.1 IDCODE change.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
The commit
f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls"
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that code.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
The commit
f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls"
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that code.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
My original intention was to have a 100ms timeout. However, the timer
operations used return values in ms not us, so we ended up with a 100s
timeout instead. Fixing this exposes that some operations need longer
to operate than 100ms, so bump the timeout up to a whole second.
Reported-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Andre Heider <a.heider@gmail.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang
for people using FSL kernel 3.0.35 and 3.10, so revert it for now.
Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Reported-by: Pierre Aubert <p.aubert@staubli.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Provide an argument to enable_fec_anatop_clock() to specify the clock frequency
that will be generated.
No changes are made to mx6slevk, which uses the default 50MHz fec clock.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Building some arm boards with older binutils may produce errors like this:
---8<---
crt0.S: Assembler messages:
crt0.S:70: Error: register expected, not '#(184)' -- `sub sp,#(184)'
--->8---
Use canonical version of the subtract mnemonic to avoid those issues.
Reported-by: Alexey Smishlayev <alexey@xtech2.lv>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Some targets will build fine but not boot if sections .hash and
.got.plt are not present in the binary. Add them back.
Also, Exynos machines require .machine_param section in SPL.
Add it.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
The OneNAND SPL used on PXA is slightly obscure. Due to the OneNAND limitation,
where we have only the first 1KiB of the OneNAND available upon power-up as a
memory-mapped area, from which the CPU starts executing, we place only the most
essential code into this first 1KiB . This code copies the rest of the SPL into
SRAM and jumps to it. This code is stored in section .text.0 .
The rest of the SPL is stored in section .text.1 . When running the OBJCOPY on
the SPL, it will preserve only .text section, but the .text.0 and .text.1 are
stripped away from the result, thus making the SPL binary empty. The patch adds
additional -j parameters to the OBJCOPY for PXA during the SPL build, which will
preserve the .text.0 and .text.1 sections.
Moreover, this patch also adds missing functions into the .text.0 section, since
otherwise the PXA270 with 1KiB-window OneNAND won't be able to boot.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Commit 762a88ccf8 introduces
a 64-bit division without using the lldiv() function,
which pulls in previously unused libgcc stuff.
Signed-off-by: Måns Rullgård <mans@mansr.com>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.
Conflicts:
include/configs/exynos5250-dt.h
Signed-off-by: Tom Rini <trini@ti.com>
Added support to find the bootmodes by reading
slcr bootmode register. this can be helpful to
autoboot the configurations w.r.t a specified bootmode.
Added this functionality on board_late_init as it's not
needed for normal initializtion part.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Relocation code based on a patch by Scott Wood, which is:
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
The enable_fec_anatop_clock method should be available for all MX6
variant as it is not MX6 SoloLite specific. This moves the code out of
the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC
instead.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator
in order to save power.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
When changing LDO voltages we need to wait for the required amount of time
for the voltage to settle.
Also, as the timer is still not available when arch_cpu_init() is called, we
need to call it later at board_postclk_init() phase.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Since ROM may modify the LDO ramp up time according to fuse setting,
it is safer to reset the ramp up field to its default value of 00:
00: 64 cycles of 24MHz clock;
01: 128 cycles of 24MHz clock;
02: 256 cycles of 24MHz clock;
03: 512 cycles of 24MHz clock;
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Adds code in pinmux and gpio framework to support Exynos5420.
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch intends to add DDR3 initialization code for Exynos5420.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
