Rename all i.MX6 pad declarations to MX6_PAD_x, so a board
may support either i.MX6Quad/Dual (MX6Q) or i.MX6Dual-Lite/Solo
(MX6DL) by including the proper header.
Boards mx6qarm2, mx6qsabreauto, mx6qsabrelite, and mx6qsabresd
only support MX6Q, so they include mx6q_pins.h.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK
hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron
MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to
DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it.
In these conditions:
tRCD(min) = 13.125 ns
tRP(min) = 13.125 ns
tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min)
tRAS(min, DDR3-1333H) = 36 ns
tRAS(min, DDR3-1600K) = 35 ns
MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field
MMDC1_MDCFG0[3:0].
MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded
as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18].
MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field
MMDC1_MDCFG1[2:0].
MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded
as 0x6 in the bit-field MMDC1_MDCFG1[31:29].
MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded
as 0x6 in the bit-field MMDC1_MDCFG1[28:26].
MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded
as 0x1A in the bit-field MMDC1_MDCFG1[25:21].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which
is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded
as 0x23 for the bit-field MMDC1_MDOR[5:0].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded
as 0x10 for the bit-field MMDC1_MDOR[13:8].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
MMDC1_MDOR.tXPR should be set as specified for the JEDEC DDR3 timing tXPR.
For all DDR3 speed bins:
tXPR(min) = max(5 nCK, tRFC(min) + 10 ns)
tRFC(2 Gb) = 160 ns
All the users of mx6q_4x_mt41j128.cfg have a 2-Gb density (Micron
MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and Micron
MT41K128M16JT-125:K for i.MX6 SABRE SD).
Hence, MMDC1_MDOR.tXPR should be set to max(5 nCK, 170 ns), which is 170 ns
and 91 nCK at 532 MHz, encoded as 0x5A in the bit-field MMDC1_MDOR[23:16].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
For all DDR3 speed bins:
tMRD(min) = 4 nCK
tMOD(min) = max(12 nCK, 15 ns)
Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK
at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
Move these fields into arch_global_data and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update for bsc9132qds.c, b4860qds.c]
Signed-off-by: Tom Rini <trini@ti.com>
QIXIS FPGA is accessable via both i2c and flash controller.
Only flash controller access is supported.
Add support of i2c based access. It is quite useful in the scenario
where either flash controller path is broken or not present.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
BSC9132QDS is a Freescale reference design board for BSC9132 SoC.
BSC9132 SOC is an integrated device that targets the evolving Microcell,
Picocell, and Enterprise-Femto base station market subsegments.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
BSC9132QDS Overview
--------------------
2Gbyte DDR3 (on board DDR), Dual Ranki
32Mbyte 16bit NOR flash
128Mbyte 2K page size NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
SD slot
USB-ULPI
eTSEC1: Connected to SGMII PHY
eTSEC2: Connected to SGMII PHY
PCIe
CPRI
SerDes
I2C RTC
DUART interface: supports one UARTs up to 115200 bps for console display
Apart from the above it also consists various peripherals to support DSP
functionalities.
This patch adds support for mainly Power side functionalities and peripherals
Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
All the dev boards of Freescale's QorIQ family have a RCW that is
supported by the u-boot.pbl build target. This patch adds one for the
P2041 dev board.
This RCW is suitable for the RAMBOOT_PBL scenarios and was tested on the
P2041RDB booting from the eSPI NOR Flash (P2041RDB_SPIFLASH config).
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Qixis FPGA has tag data contains image name and build date.
It is helpful to identify the FPGA image precisely.
Signed-off-by: York Sun <yorksun@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This function is called by "qixis_reset switch" command and
switch settings are calculated from qixis FPGA registers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This function is called by "qixis_reset switch" command
and switch settings are calculated from FPGA/qixis registers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Remove #ifdef so that "qixis dump" command is always available
Add "qixis_reset switch" command to dump switch settings
Qixis doesn't have 1:1 switch mapping. We need to reverse engineer from
registers to figure out switch settings. Not all bits are available.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor.
B4860QDS Overview
------------------
- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
ECC, 4 GB of memory in two ranks of 2 GB.
- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB of memory. Single rank.
- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
16x16 switch VSC3316
- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
8x8 switch VSC3308
- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
- B4860 UART port is available over USB-to-UART translator USB2SER or over
RS232 flat cable.
- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper
connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA
connector ports 0 and 2 for AMC mode.
- The B4860 configuration may be loaded from nine bits coded reset
configuration reset source. The RCW source is set by appropriate
DIP-switches:
- 16-bit NOR Flash / PROMJet
- QIXIS 8-bit NOR Flash Emulator
- 8-bit NAND Flash
- 24-bit SPI Flash
- Long address I2C EEPROM
- Available debug interfaces are:
- On-board eCWTAP controller with ETH and USB I/F
- JTAG/COP 16-pin header for any external TAP controller
- External JTAG source over AMC to support B2B configuration
- 70-pin Aurora debug connector
- QIXIS (FPGA) logic:
- 2 KB internal memory space including
- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
DDRCLK1, 2 and RTCCLK.
- Two 8T49N222A SerDes ref clock devices support two SerDes port clocks
- total four refclk, including CPRI clock scheme
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
QIXIS FPGA's QIXIS Tag Access register (QTAG) defines TAG, VER, DATE, IMAGE
fields. These fields have FPGA build version, image name and build date
information.
Add support to parse these fields to have complete FPGA image information.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The internal SRAM of Freescale's IFC NAND machine is of 64K and controller's
Address Mask Registers is initialised with the same.
So Update TLB and LAW size of NAND flash accordingly.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Static variables should be defined in C files, not header files, because
otherwise every C file that #includes the header file will generate a
duplicate of the variables. Since the vsc3316_xxx[] arrays are only
used by t4qds.c anyway, just put the variables there.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Lanes mux currently is configured in eth.c when initializing FMAN ethernet
ports, but SRIO and PCIe also need lanes mux, so we move the lanes mux to
p2041rdb.c which implements a board-specific initialization and will be
called at early stage.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The following features are supported:
* 128 MB DDR1 SDRAM
* DUART
* SD/MMC Card Socket
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Some MXS based boards do not implement the card-detect signal. Allow
user to specify alternate card-detect implementation.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
The '#' used as comments in the files cause the preprocessor
trouble, so change to /* */.
The mkimage command which uses this preprocessor output
was moved to arch/arm/imx-common/Makefile
.gitignore was updated to ignore .cfgtmp files.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Add DVI output support and make it the default video output.
Currently the CLAA WVGA panel is supported, but this panel has to be purchased
separately, so using the DVI output as the default would allow more people to
try the splash screen feature on a mx51evk.
If someone still wants to use the CLAA WVGA, just set the panel variable as:
set panel claa
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Add support for the Seiko 4.3'' WVGA panel on mx53loco.
By default, the CLAA WVGA panel is selected.
In order to support the Seiko panel, the enviroment variable 'panel' must be
set to 'seiko'.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Make the error handling more robust.
Check if each one of the PMIC writes fail and if they do, just return
immediately.
Also, print the cause for the failures.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
commit c73368150 (pmic: Extend PMIC framework to support multiple instances
of PMIC devices) introduced an extra 'retval' variable, but this is not
necessary since we have already the variable 'ret' in place.
So use 'ret' to store the return values from the pmic related calls and remove
'retval'.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The on-board number of available usdhc devices is something board
specific. The patch moves CONFIG_SYS_FSL_USDHC_NUM out of
mx6qsabre_common.h and adds usdhc2 and usdhc4 support for mx6qsabresd
board.
To keep the default mmc device for environment same as before (usdhc3),
it moves CONFIG_SYS_MMC_ENV_DEV out of mx6qsabre_common.h and changes
it to 1 for mx6qsabresd.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Since commit c733681 (pmic: Extend PMIC framework to support multiple instances
of PMIC devices) mx53loco fails to allocate the memory for PMIC:
U-Boot 2013.01-rc2-dirty (Dec 20 2012 - 15:55:01)
Board: MX53 LOCO
I2C: ready
DRAM: 1 GiB
pmic_alloc: No available memory for allocation!
pmic_init: POWER allocation error!
CPU: Freescale i.MX53 family rev2.0 at 800 MHz
Reset cause: POR
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Calling the PMIC related functions at a later stage, ie, from board_late_init()
fixes the issue.
Reported-by: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
This converts MPC8313ERDB NAND boot to use the new SPL infrastructure.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
commit c73368150 (pmic: Extend PMIC framework to support multiple instances
of PMIC devices) has incorrectly passed the PMIC name under the FSL PMIC case.
Fix that by passing "FSL_PMIC" as the parameter of pmic_get.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Make the necessary adaptions for the new PMIC framework, so that mx25pdk can
be built again.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Conflicts:
drivers/power/power_fsl.c
include/configs/mx35pdk.h
include/configs/mx53loco.h
include/configs/woodburn_common.h
board/woodburn/woodburn.c
These boards still use the old old PMIC framework, so they
do not merge properly after the power framework was merged into
mainline.
Fix all conflicts and update woodburn to use Power Framework.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed
800, 900, 1000, 1200, 1300MT/s.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.
This patch does:
s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g
All 85xx, 86xx, and 83xx have been built with this change.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Andy Fleming <afleming@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
This allows DDR configuration to be deferred to the final U-Boot image,
which is able to make use of SPD data. The SPL itself cannot use SPD due
to code size constraints. It previously used fixed register values for
DDR configuration, and those values did not work on the p2020rdb-pca
board I tested with. It's possible that different revisions of the board
require different settings. Using SPD eliminates that problem.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
- Sort by address, and fix column alignment
- Don't label things as localbus that aren't. Instead, put chipselect
info at the end of the description for localbus windows. Note that
NAND/NOR have their chipselects swapped when booting from NAND, and CS2
can be either PMC or VSC7385 depending on hwconfig.
- Shrink NAND to the 32K that's actually mapped in the localbus
- Assign an address and size to L2 SRAM. Remove the similarly named
but unintelligible "L2 SDRAM(REV.)".
- Remove the untrue comment about L1 stack being mapped with TLB0.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Introduces CONFIG_SPL_RELOC_TEXT_BASE and CONFIG_SPL_RELOC_STACK.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Add support for the OTG port on the mx35pdk Personality board.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
