Commit Graph

9491 Commits

Author SHA1 Message Date
Rajesh Bhagat
707c866f3d usb: xhci: fsl: Add code to use CONFIG_DM_USB
Adds code to use driver model for USB XHCI FSL driver

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2016-08-07 21:55:43 +02:00
Rajesh Bhagat
ba699a5f91 usb: ehci: fsl: Add code to use CONFIG_DM_USB
Adds code to use driver model for USB EHCI FSL driver

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2016-08-07 21:55:43 +02:00
Rajesh Bhagat
1e61ce9f7e drivers: usb: fsl: Make function for initialization to use in CONFIG_DM_USB
Moves code from ehci_hcd_init to new function ehci_fsl_init
which can be re-used in CONFIG_DM_USB.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2016-08-07 21:55:43 +02:00
Masahiro Yamada
2b58e1b76d usb: add (move) CONFIG_USB_HOST to Kconfig
The meaning of CONFIG_USB in U-Boot is different from that in Linux.

As you see in drivers/usb/Kconfig of Linux, CONFIG_USB enables the
USB host controller support, while CONFIG_USB_SUPPORT is used to
enable the whole of the USB sub-system.

When I added CONFIG_USB into Kconfig by commit 6e7e9294d3 ("usb:
add basic USB configs in Kconfig"), I planned to follow the Linux's
convention, i.e. CONFIG_USB to enable/disable the USB host support.

Then, commit 68f7c5db2d ("usb: Generic USB Kconfig option, that
fits both host and gadget and comments") changed the logic of the
CONFIG_USB to point to the whole of the USB sub-system.  As a result,
currently we do not have an option for USB host.

This commit adds CONFIG_USB_HOST, which will be useful to compile
in the USB host support code.

CONFIG_USB_HOST is not referenced at all, but strangely some boards
define it in board headers.  I removed them because USB_HOST will be
selected in Kconfig going forward.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-07 21:55:42 +02:00
Masahiro Yamada
96d8284bd5 usb: add CONFIG_USB_UHCI_HCD in Kconfig
There is no UHCI driver entry in Kconfig for now, but we have some
UHCI drivers, for example, LEON.  This is a placeholder in case we
want to move them to Kconfig in the future.

The help message was copied from Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-07 21:55:42 +02:00
Masahiro Yamada
93cb82477d usb: add CONFIG_USB_OHCI_HCD in Kconfig
Add this option as a common config for all OHCI controllers.  Its
help message was copied from Linux.  Also, I moved it below EHCI
to respect the order in Linux's Kconfig.

Add CONFIG_USB_OHCI_HCD=y to axs103_defconfig, which is the only
user of OHCI_GENERIC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-07 21:55:42 +02:00
Stefan Roese
6688452a3b net: usb: r8152: Add DM support
Add support for driver model, so that CONFIG_DM_ETH can be defined and
used with this driver.

This patch also adds the read_rom_hwaddr() callback so that the ROM MAC
address will be used to the DM part of this driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Ted Chen <tedchen@realtek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2016-08-07 21:55:42 +02:00
Peng Fan
bb42fb4f10 dm: ehci-mx6: support driver model
Support driver model for ehci mx6 driver.
Consolidate code to be shared between DM and non-DM, such as
introducing ehci_mx6_common_init.
For simplicity, some old fasion code are keeped for DM usage,
such as board_ehci_power and board_usb_phy_mode. And 'dr-mode',
usbphy and vbus handling code for DM is not added now.
These will be added in future patches.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Simon Glass <sjg@chromium.org>
2016-08-07 21:55:42 +02:00
Tom Rini
2863a9bfc2 Merge git://git.denx.de/u-boot-rockchip 2016-08-06 11:38:14 -04:00
Tom Rini
f2df3b6e99 zynq_sdhci.c: Fix warning in arasan_sdhci_probe
We no longer need to set 'caps' as it's not passed to sdhci_setup_cfg
anymore.

Fixes: 14bed52d27 ("mmc: sdhci: remove the unnecessary arguments for
		sdhci_setup_cfg")
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-08-05 20:55:31 -04:00
Tom Rini
7edb17670c Merge branch 'master' of git://git.denx.de/u-boot-tegra 2016-08-05 20:55:30 -04:00
Heiko Stübner
abd0128eb1 rockchip: remove log2 reimplementation from clock drivers
The already available ilog2 function does exactly the same in the common
case than the log2 function the current clock-driver reimplement.
So, simply move to that one.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
2016-08-05 18:07:07 -06:00
Kever Yang
fd4b2dc059 clock: rk3399: add support for dwmmc 400K
MMC core will use 400KHz for card initialize first and then switch to
higher frequency like 50MHz, we need to support both 400KHz and about
50MHz for dwmmc controller.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-08-05 18:02:51 -06:00
Heiko Stübner
aff8795c01 move: rockchip: move clock drivers into a subdirectory
With the number of Rockchip clock drivers increasing, don't clutter up
the core drivers/clk directory with them and instead move them out of
the way into a separate subdirectory.

Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Updated for rk3399:
Signed-off-by: Simon Glass <sjg@chromium.org>
2016-08-05 17:56:08 -06:00
Kever Yang
b0b3c86521 rk3399: add basic soc driver
This patch add driver for:
- clock driver including set_rate for cpu, mmc, vop, I2C.
- sysreset driver
- grf syscon driver

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-08-05 17:56:07 -06:00
Jaehoon Chung
89f69e5173 mmc: sdhci: fix the compiler warning when disable CONFIG_MMC_SDMA
When disabled CONFIG_MMC_SDMA, variable caps didn't use.
This patch fixes the compiler error for -Wunused-but-set-variable

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-08-05 20:48:01 +09:00
Xu Ziyuan
720724d098 mmc: dw_mmc: fix data starvation by host timeout under FIFO mode
This patch fixes data starvation by host timeout(HTO) error interrupt
which occurred under FIFO mode transfer on rk3036 board.

The former implement, the actual bytes were transmitted may be less than
should be. The size will still subtract value of len in case of there is
no receive/transmit FIFO data request interrupt.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-08-05 14:04:36 +09:00
Xu Ziyuan
2990e07a33 mmc: dw_mmc: transfer proper bytes to FIFO
The former implement, dw_mmc will push and pop the redundant data to
FIFO, we should transfer it according to the real size.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-08-05 14:04:31 +09:00
Jaehoon Chung
14bed52d27 mmc: sdhci: remove the unnecessary arguments for sdhci_setup_cfg
Some arguments don't need to pass to sdhci_setup_cfg.
Generic variable can be used in sdhci_setup_cfg, and some arguments are
already included in sdhci_host struct.

It's enough that just pass the board specific things to sdhci_setup_cfg().
After removing the unnecessary arguments, it's more simpler than before.
It doesn't consider "Version" and "Capabilities" anymore in each SoC
driver.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-05 11:31:07 +09:00
Jaehoon Chung
6a879ec8e7 mmc: sdhci: remove the unused argument for sdhci_setup_cfg
buswidth isn't used anywhere in sdhci_setup_cfg.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-05 11:21:25 +09:00
Jaehoon Chung
e1ea7c44d6 mmc: sdhci: revert "mmc: sdhci: Claer high speed if not supported"
This "commit 429790026021d522d51617217d4b86218cca5750" is wrong.
SDHCI_QUIRK_NO_HISPD_BIT is for skipping to set CTRL_HISPD bit.

For example, Exynos didn't have CTRL_HISPD. But Highspeed mode
is supported.
(This quirks doesn't mean  that driver didn't support the Highseepd mode.)

Note: If driver didn't support the Highspeed Mode, use or add the other
quirks.

After applied this patch, all Exynos SoCs are just running with 25MHz.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-08-05 11:21:25 +09:00
Xu Ziyuan
1bd4f92cdb mmc: display mmc list information like mmc_legacy type
It's nicer to see this:

=> mmc list
dwmmc@ff0c0000: 0
dwmmc@ff0f0000: 1 (eMMC)

than this:

=> mmc list
dwmmc@ff0c0000: 0dwmmc@ff0f0000: 1 (eMMC)

With the former, it's much clearer which mmc devices are on.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-08-05 11:21:25 +09:00
Jaehoon Chung
915ffa5213 mmc: use the generic error number
Use the generic error number instead of specific error number.
If use the generic error number, it can debug more easier.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-08-05 11:21:25 +09:00
Jaehoon Chung
70f862808e mmc: fsl_esdhc: remove the duplicated header file
"mmc.h" is already included. It's duplicated.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-05 11:21:25 +09:00
Jaehoon Chung
ccd60a8524 mmc: dw_mmc: remove the duplicated header file
<asm-generic/errno.h> is already included in <errno.h>.
It can use <errno.h> instead of <asm-generic/errno.h>

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-05 11:21:24 +09:00
Jaehoon Chung
a034ec06ff mmc: s5p_sdhci: unset the SDHCI_QUIRK_BROKEN_R1B
Unset the SDHCI_QUIRK_BROKEN_R1B for exynos SoC.
(Tested on Exynos4 Boards.)

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
2016-08-05 11:21:24 +09:00
Jaehoon Chung
17ea3c8628 mmc: sdhci: set to INT_DATA_END when there are data
There is no data, it doesn't needs to wait for completing data transfer.
(It seems that it can be removed.)
Almost all timeout error is occured from stop command without data.
After applied this patch, I hope that we don't need to increase timeout value anymore.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2016-08-05 11:21:24 +09:00
Masahiro Yamada
bae4a1fdf5 mmc: sdhci: clean up timeout detection
The current timeout detection logic is not very nice; it calls
get_timer(start) in the while() loop, and then calls it again after
the loop to check if a timeout error happened.

Because of the time difference between the two calls of get_timer(),
the timeout detected after the loop may not be true.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-08-05 11:21:24 +09:00
Stephen Warren
729c2db7a9 ARM: tegra: adapt to latest HSP DT binding
The DT binding for the Tegra186 HSP module apparently wasn't quite final
when I posted initial U-Boot support for it. Add the final DT binding doc
and adapt all code and DT files to match it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-04 13:36:58 -07:00
York Sun
8936691ba6 driver/ddr/fsl: Fix timing_cfg_2
Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the
change was wrong. wr_lat has 5 bits with MSB at [13] and lower
4 bits at [9:12], in big-endian convention.

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>
2016-08-02 09:47:34 -07:00
Sumit Garg
7fe1d6a410 crypto/fsl: Update blob cmd to accept 64bit addresses
Update blob cmd to accept 64bit source, key modifier and destination
addresses. Also correct output result print format for fsl specific
implementation of blob cmd.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-02 09:45:39 -07:00
Yunhui Cui
04e5c6d9cc driver: spi: fsl-qspi: remove compile Warnings
Warnins log:
drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);

Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-08-02 09:45:13 -07:00
Tom Rini
26fb8db0f4 Merge git://git.denx.de/u-boot-rockchip 2016-07-31 20:31:13 -04:00
Hans de Goede
4069437dfb net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers
This fixes the following CACHE warnings when using sun8i_emac:

=> dhcp
BOOTP broadcast 1
BOOTP broadcast 2
CACHE: Misaligned operation at range [7bf594a8, 7bf59628]
BOOTP broadcast 3
CACHE: Misaligned operation at range [7bf59c90, 7bf59e10]
CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8]
DHCP client bound to address 10.42.43.80 (1009 ms)

Note this commit also changes the max rx size from 2024 to 2044,
matching what the kernel driver uses.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-07-31 21:45:46 +02:00
Chen-Yu Tsai
4694dc56e9 sunxi: gpio: Add .xlate function for gpio phandle resolution
sunxi uses a 2 cell phandle for gpio bindings. Also there are no
seperate nodes for each pin bank.

Add a custom .xlate function to map gpio phandles to the correct
pin bank device. This fixes gpio_request_by_name usage.

Fixes: 7aa9748584 ("dm: sunxi: Modify the GPIO driver to support driver
		      model")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-07-31 21:45:12 +02:00
John Keeping
2b51784aef rockchip: rk3288: Fix pinctrl for GPIO bank 0
Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers
rather than the GRF registers.  In the GRF the top half of the register
is used as a mask so that some bits can be updated without affecting the
others, but in the PMU this feature is not provided and the top half of
the register is reserved.

Take the same approach as the Linux driver to update the value via
read-modify-write but setting the mask for only the bits that have
changed.  The PMU registers ignore the top 16 bits so this works for
both GRF and PMU iomux registers.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2016-07-31 07:24:20 -06:00
Kever Yang
46683f3da1 mmc-uclass: correct the device number
Not like the mmc-legacy which the devnum starts from 1, it starts from 0
in mmc-uclass, so the device number should be (devnum + 1) in get_mmc_num().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-07-31 07:24:20 -06:00
Vignesh R
a6f56ad1ee spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
the driver to use the same.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-07-30 00:15:00 +05:30
Wenyou Yang
b302669f46 sf: sf_params: Add AT25DF321 flash support
Add AT25DF321 flash support.
Fix AT25DF321A device name.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-07-30 00:15:00 +05:30
Vignesh R
fee3b6af90 spi: ti_qspi: Remove delay in read path for dra7xx
As per commit b545a98f5d ("spi: ti_qspi: Add delay
for successful bulk erase) says its added to meet bulk erase timing
constraints. But bulk erase is a cmd to flash and delay in read path
does not make sense. Morever, testing on DRA74/DRA72 evm has shown that
this delay is no longer required.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-07-30 00:15:00 +05:30
Vignesh R
c595a28530 spi: ti_qspi: Fix compiler warning when DEBUG macro is set
clk_div is uninitialized at the beginning of ti_spi_set_speed(), move
debug() print after clk_div calculation to avoid compiler warning and to
have proper value of clk_div printed during debugging.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-07-30 00:15:00 +05:30
Vignesh R
69eeefaa06 spi: ti_qspi: Fix failure on multiple READ_ID cmd
Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value
QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in
ti_qspi_cs_deactivate(). Therefore CS is never deactivated between
successive READ ID which results in sf probe to fail.
Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih
priv->cmd as required (similar to the convention followed in the
driver).

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-07-30 00:15:00 +05:30
Moritz Fischer
6bde34f1ae spi: Add support for N25Q016A
This commit adds support in the spi-nor driver for the
N25Q016A, a 16Mbit SPI NOR flash from Micron.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-07-30 00:15:00 +05:30
Tom Rini
4711e7f7af Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-07-28 08:45:00 -04:00
Tim Harvey
ec21aee653 pci: allow disabling of pci init/enum via env
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2016-07-28 13:27:17 +02:00
Tom Rini
fe34b6a484 Merge git://git.denx.de/u-boot-dm 2016-07-27 22:30:20 -04:00
Xu Ziyuan
02ebd42cf1 mmc: dw_mmc: reduce timeout detection cycle
It's no need to speed 10 seconds to wait the mmc device out from busy
status. 500 milliseconds enough.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-07-27 20:15:48 -06:00
Stephen Warren
61f5ddcb7a Add a power domain framework/uclass
Many SoCs allow power to be applied to or removed from portions of the SoC
(power domains). This may be used to save power. This API provides the
means to control such power management hardware.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-27 16:29:56 -06:00
Simon Glass
f1a485aa40 dm: socfpga: mmc: Support CONFIG_BLK
Update the driver to support using driver model for block devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-27 14:15:54 -06:00
Simon Glass
329a449f2c dm: mmc: zynq: Convert zynq to use driver model for MMC
Move zynq to the latest driver model support by enabling CONFIG_DM_MMC,
CONFIG_DM_MMC_OPS and CONFIG_BLK.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-27 14:15:54 -06:00