Do not define serial_putc() and serial_puts() calls if
CONFIG_SPL_SERIAL_SUPPORT is set.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
This code is part of battery boot support for i.MX28.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
If the LCD controller is on before the CPU goes into reset, the traffic on LCDIF
data pins interferes with the BootROM's boot mode sampling. So shut the
controller down.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Pass memory size from SPL via structure located in SRAM instead of SCRATCH
registers. This allows passing more data about boot from SPL to U-Boot, like the
boot mode pads configuration.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
This solves issues when larger amount of DRAM is used, like 256MB.
Behave the same in case of CPU bypass as we do in case of EMI
bypass, but wait 15 ms. We need to wait until the clock domain
stabilizes.
This issue seemed to have been caused by not waiting after frobbing
with the CPU bypass, it was unrelated to memory, but had a direct
impact, causing trouble. This was yet another X-File of the
imx-bootlets, sigh. The conclusion is, trying a semi-random delay
(there is delay after the EMI bypass change), the issue is fixed.
Another possible explanation is that we do not do the "simple memory
test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of
the memory, while also outputing something on the serial port). This
might have caused the similar delay in the imx-bootlets and therefore
they didn't need to add this explicitly.
For now, this seems good fix enough, but to me, whole that memory
init code in imx-bootlets is completely flunked and it'd need deeper
investigation.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's
implement get_clocks function. This is how it seems to be implemented
elsewhere.
Signed-off-by: Timo Ketola <timo@exertus.fi>
Acked-by: Stefano Babic <sbabic@denx.de>
Init the core regulator voltage to 1.2V. This is required for the correct
functioning of the GPU and when the ARM LDO is set to 1.225V. This is a
workaround to fix some memory clock jitter.
Note: This should be but can't be done in the DCD. The bootloader
prevents access to the ANATOP registers.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Chen <b02280@freescale.com>
CC: Jason Liu <r64343@freescale.com>
CC: Ranjani Vaidyanathan <ra5478@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <festevam@gmail.com>
This reverts commit 69d26d09de.
Apparently, this commit got mainline only because of out-of-tree
port and causes breakage on board that is mainline. Revert.
Reason:
* The OOT board has 512MB of DRAM, enabling this additional address
line enabled it to work fine with 512MB of RAM.
* Every mainline port has max. 256MB of DRAM, therefore this revert
has no impact on any mainline port
* Though this caused a problem with new M28 board with 256MB of DRAM
where the chips are wired differently. The patch-to-be-reverted
caused the DRAM to behave like this:
[128MB chunk #1][128MB chunk #1 again][128MB chunk #2][128MB chunk #2 again]
Therefore to retain the current one-memory-init-rules-them-all situation,
revert this patch until another board emerges and will actually be pushed
mainline that needs different setup.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Print CPU information within board_late_init().
This is in preparation for adding 1GHz support, which requires programming a PMIC
via I2C. As I2C is only available after relocation, print the CPU information
later at board_late_init(), so that the CPU frequency can be printed correctly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
mx5: Add clock config interface
Add clock config interface support, so that we
can configure CPU or DDR clock in the later init
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Signed-off-by: Eric Miao <eric.miao@linaro.org>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
get_ahb_clk() is a common function between mx5 and mx6.
Place it into imx-common directory.
Cc: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The MX53 SATA interface can use an internal clock (USB PHY1)
instead of an external clock. This is an undocumented feature, but used
on most Freescale's evaluation boards, such as MX53-loco.
As stated by Freescale's support:
Fuses (but not pins) may be used to configure SATA clocks.
Particularly the i.MX53 Fuse_Map contains the next information
about configuring SATA clocks :
SATA_ALT_REF_CLK[1:0] (offset 0x180C)
'00' - 100MHz (External)
'01' - 50MHz (External)
'10' - 120MHz, internal (USB PHY)
'11' - Reserved
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Add base address and MXC_SATA_CLK to return
the clock used for the SATA controller.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
To sets up lcd and mipi clock in EXYNOS display driver, added clock interface.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This is definitions of system registers and power mananagement registers for EXYNOS SoC.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Introduce a __weak misc_init_r function that just runs dieid_num_r().
Remove misc_init_r from cm_t35, mcx, omap3_logic and mt_ventoux as this was
all they did for misc_init_r.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Peter Barada <peter.barada@logicpd.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Enable -march=armv7-a for armv7 platforms if the tool-chain
supports it. This in turn results in Thumb-2 code generated
for these platforms if CONFIG_SYS_THUMB_BUILD is enabled.
Signed-off-by: Aneesh V <aneesh@ti.com>
Use ENTRY and ENDPROC with assembly functions to ensure
necessary assembler directives for all functions.
Signed-off-by: Aneesh V <aneesh@ti.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Warm reset is not functional in case of omap5430ES1.0.
So override the weak reset_cpu function to use
cold reset instead.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The reset.S has the function to do a warm reset on OMAP
based socs. Moving this to a reset.c file so that this
acts a common layer to add any reset related functionality
for the future.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Make the sysctrl structure common, so that it can
be used in generic functions across socs.
Also change the base address of the system control module, to
include all the registers and not simply the io regs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The different silicon revision variable names was defined for OMAP4 and
OMAP5 socs. Making the variable common so that some code can be
made generic.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The break statement is missing in init_omap_revision function, resulting
in a wrong revision identification. So fixing this.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The nominal opp vdd values as recommended for
ES1.0 silicon is set for mpu, core, mm domains using palmas.
Also used the right sequence to enable the vcores as per
a previous patch from Nishant Menon, which can be dropped now.
http://lists.denx.de/pipermail/u-boot/2012-March/119151.html
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The OMAP5 silicon has new DDR PHY design, which includes a external PHY
as well. So configuring the ext PHY parameters here. Also the EMIF timimg
registers and a couple of DDR mode registers needs to be updated based on
the testing from the actual silicon.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The control module provides options to set various signal
integrity parameters like the output impedance, slew rate,
load capacitance for different pad groups. Configure these
as required for the omap5430 sevm board.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Aligning all the clock related settings like the dpll frequencies, their
respective clock outputs, etc to the ideal values recommended for
OMAP5430 ES1.0 silicon.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
OMAP4 requires that parent domains scale ahead of dependent domains.
This is due to the restrictions in timing closure. To ensure
a consistent behavior across all OMAP4 SoC, ensure that
vdd_core scale first, then vdd_mpu and finally vdd_iva.
As part of doing this refactor the logic to allow for future
addition of OMAP4470 without much ado. OMAP4470 uses different
SMPS addresses and cannot be introduced in the current code
without major rewrite.
Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
|---------------| (SET1 default 1.4V)
| --------(programmed voltage)
| <- (This switch happens on mux7,pullup)
vdd_mpu(TPS) -----/ (OPP boot voltage)
--------- (programmed voltage)
vdd_core(TWL6030) -----------------------/ (OPP boot voltage)
Problem 1) |<----- Tx ------>|
timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.
By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
-------- (programmed voltage)
vdd_mpu(TPS) ------------/ (Opp boot voltage)
--------- (programmed voltage)
vdd_core(TWL6030) -------------/ (OPP boot voltage)
NOTE: This does not attempt to address OMAP5 - Aneesh please confirm
Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
OMAP Voltage controller is used to generically talk to
PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code
in multiple SoC code, introduce a common voltage controller
logic which can be re-used from elsewhere.
With this change, we replace setup_sri2c with omap_vc_init which
has the same functionality, and replace the voltage scale
replication in do_scale_vcore and do_scale_tps62361 with
omap_vc_bypass_send_value. omap_vc_bypass_send_value can also
now be used with any configuration of PMIC.
NOTE: Voltage controller controlling I2C_SR is a write-only data
path, so no register read operation can be implemented.
Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Add parameters to the OMAP MMC initialization function so the board can
mask host capabilities and set the maximum clock frequency. While the
OMAP supports a certain set of MMC host capabilities, individual boards
may be more restricted and the OMAP may need to be configured to match
the board. The PRG_SDMMC1_SPEEDCTRL bit in the OMAP3 is an example.
Signed-off-by: Jonathan Solnit <jsolnit@gmail.com>
This change adds initial support for NXP LPC32x0 SoC series.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
We certainly don't want the compiler to reorganise the code for dcache flushing.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Stefano Babic <sbabic@denx.de>
As well as pushed for ARM926EJS, we certainly don't want
the compiler to reorganise the code for dcache flushing
Fix checkpatch warnings as well.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marex@denx.de>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
Freescale SOCs require an header to u-boot.bin
The patch adds u-boot.imx to the default targets
if the imx file is set (IMX_CONFIG).
Signed-off-by: Stefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
CC: Loïc Minier <loic.minier@linaro.org>
CC: Mike Frysinger <vapier@gentoo.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Tested-by: Dirk Behme <dirk.behme@googlemail.com>
This fixes the issue where mxs_dma_init() was called either twice or never,
without introducing any new init hooks.
The idea is to allow each and every device using the APBH DMA block to
configure and request only the channels it uses, instead of making it call init
for all the channels as is now.
The common DMA block init part, which only configures the block, is then called
from CPUs arch_cpu_init() call.
NOTE: This patch depends on:
http://patchwork.ozlabs.org/patch/150957/
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Misaligned warnings are useful to debug faulty drivers.
A misaligned warning is printed also when the driver
is correct - use debug() instead of printf().
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
CC: Mike Frysinger <vapier@gentoo.org>
CC: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Since commit 5c1ad3e6f8
(net: fec_mxc: allow use with cache enabled) the FEC_MXC
driver uses flush_dcache_range() and invalidate_dcache_range()
functions. This driver is also configured for ARM1136 based
'flea3' and 'mx35pdk' boards which currently do not build
as there are no ARM1136 specific flush_dcache_range() and
invalidate_dcache_range() functions. Add various ARM1136
cache functions to fix building for 'flea3' and 'mx35pdk'.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
CC: Mike Frysinger <vapier@gentoo.org>
CC: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Each cpu directory currently has its own .lds file. This is only needed
in most cases because the start.o file is in a different subdir.
Now that we can factor out this difference, we can move most cpus over
to the common .lds file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Most ARM CPUs use a very similar link script. This adds a basic
script that can be used by most CPUs.
Two new symbols are introduced which are intended to eventually be
defined on all architectures to make things easier for generic relocation
and reduce special-case code for each architecture:
__image_copy_start is the start of the text area (equivalent to the
existing _start on ARM). It marks the start of the region which must be
copied to a new location during relocation. This symbol is called
__text_start on x86 and microblaze.
__image_copy_end is the end of the region which must be copied to a new
location during relocation. It is normally equal to the start of the BSS
region, but this can vary in some cases (SPL?). Making this an explicit
symbol on its own removes any ambiguity and permits common code to always
do the right thing.
This new script makes use of CPUDIR, now defined by both Makefile and
spl/Makefile, to find the directory containing the start.o object file,
which is always placed first in the image.
To permit MMU setup prior to relocation (as used by pxa) we add an area
to the link script which contains space for this. This is taken
from commit 7f4cfcf. CPUs can put the contents in there using their
start.S file. BTW, shouldn't that area be 16KB-aligned?
Signed-off-by: Simon Glass <sjg@chromium.org>
Fix:
clocks-common.c: In function 'setup_non_essential_dplls':
clocks-common.c:323:6: warning: variable 'sys_clk_khz' set but not used
[-Wunused-but-set-variable]
clocks-common.c: In function 'setup_non_essential_dplls':
clocks-common.c:323:6: warning: variable 'sys_clk_khz' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Tom Rini <trini@ti.com>
I2C ports have a 16-bit clock divisor. Add code to handle this special
case so that I2C speeds below 150KHz are supported.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Change this name to fit with the current convention in the Tegra
header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds basic support for the Tegra2 USB controller. Board files should
call board_usb_init() to set things up.
Configuration is performed through the FDT, with aliases used to set the
order of the ports, like this fragment:
aliases {
/* This defines the order of our USB ports */
usb0 = "/usb@0xc5008000";
usb1 = "/usb@0xc5000000";
};
drivers/usb/host files ONLY: Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A common requirement is to find the clock ID for a peripheral. This is the
second cell of the 'clocks' property (the first being the phandle itself).
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
config.mk is updated to provide this file to boards through the
built-in mechanism:
/include/ ARCH_CPU_DTS
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The 4.2.2 gcc in the ELDK42 release doesn't like the direct SP
load using a constant in tegra2_start. Change it to use a load
thru another reg using mov sp, %0 : : "r"(CONST).
Tested on my Seaboard T20-A03, U-Boot loads and runs OK. Also
compiled all tegra2 builds with both gcc 4.2.2 and 4.4.1 OK.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Implement reset for highbank platform. Reset is triggered via a wfi
instruction, so enabling armv7 for the compiler is necessary.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
udelay calls were off due to failing to convert us to ns. Fix this and drop
the unnecessary shifts since NS_PER_TICK is only 7ns.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
The get_tbclk function was missing and the recent commit "common: add
possibility for readline_into_buffer timeout" makes it required.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
This patch fixes the s3c24x0 timer code to work with the ARM
relocation feature.
Signed-off-by: David Mueller <d.mueller@elsoft.ch>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
Call i2c initialization in spl_board_init only if I2C
is configured for the board.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
This only outputs "Assuming u-boot.bin..." if debug is active.
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
This adds Linux booting to the SPL
This depends on CONFIG_MACH_TYPE patch by Igor Grinberg
(http://article.gmane.org/gmane.comp.boot-loaders.u-boot/105809)
Related CONFIGs:
CONFIG_SPL_OS_BOOT
Activates/Deactivates the OS booting feature
CONFIG_SPL_OS_BOOT_KEY
defines the IO-pin number u-boot switch - if pressed u-boot is
booted
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
Offset in NAND of direct boot kernel image to use in SPL
CONFIG_SYS_SPL_ARGS_ADDR
Address where the kernel boot arguments are expected - this is
normaly RAM-begin + 0x100
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
This implements booting of Linux from NAND in SPL
Related config parameters:
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
Offset in NAND of direct boot kernel image to use in SPL
CONFIG_SYS_SPL_ARGS_ADDR
Address where the kernel boot arguments are expected - this is
normally RAM-start + 0x100 (on ARM)
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
Change the parent UART clock to be PLL2, so that U-boot can also boot
a Freescale 2.6.35 kernel for mx53.
FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid
conflicts with IPU clocks, so that the video resolution can be changed
without affecting the UART clock.
On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded
and this patch fixes this problem.
Tested on a mx53loco board booting a FSL kernel and also a mainline kernel.
Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Instead of hardcoding the mx6 silicon revision, read it in run-time.
Also, besides the silicon version print the mx6 variant type: quad,dual/solo
or solo-lite.
Tested on a mx6qsabrelite, where it shows:
CPU: Freescale i.MX6Q rev1.0 at 792 MHz
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <r64343@freescale.com>
Instead of compiling the function and using the result as a constant, simply use
the constant.
NOTE: This patch works around bug:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52546
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cut down the VDDIO/VDDA regulator stabilization delays to 500 uS. That should be
enough according to the datasheet and bootlets.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Robert Deliën <robert@delien.nl>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
After booting mx6qsabrelite from POR the following is reported:
CPU: Freescale i.MX61 family rev1.0 at 792 MHz
Reset cause: unknown reset
This is because both the POR and WDOG bits are set after reset.
Fix this by also checking both bits in the POR case.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Enables all fourteen address lines for DRAM
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Tested-by: Marek Vasut <marek.vasut@gmail.com>
IxEthAcc.c: In function ‘ixEthAccInit’:
IxEthAcc.c:105:21: warning: comparison between ‘IxEthDBStatus’ and ‘enum <anonymous>’ [-Wenum-compare]
IxEthDBAPISupport.c: In function ‘ixEthDBPortAddressSet’:
IxEthDBAPISupport.c:633:18: warning: variable ‘ackPortAddressLock’ set but not used [-Wunused-but-set-variable]
IxQMgrDispatcher.c: In function ‘ixQMgrLLPShow’:
IxQMgrDispatcher.c:1194:18: warning: variable ‘q’ set but not used [-Wunused-but-set-variable]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
Add -EB flag to LD to switch endianness of the linker. This should make armeb
targets buildable again. Also, make use of U-Boot's internal libgcc instead of
toolchain's one, this works around the use of libraries from GCC, which might be
little endian.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
Adds support for loading U-Boot from UART using YMODEM protocol.
If YMODEM support is enabled in SPL and the romcode indicates
that SPL loaded via UART then SPL will wait for start of a
YMODEM transfer via the console port.
Signed-off-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
This patch fixes erroneous 32-bit access to registers
hw_clkctrl_frac0 and hw_clkctrl_frac1.
Signed-off-by: Robert Delien <robert@delien.nl>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
This patch renames mx28_register to mx28_register_32 in order to
prepare for the introduction of an 8-bit register, mx28_register_8.
Signed-off-by: Robert Delien <robert@delien.nl>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
This patch replaces the use of magice numbers for scratch register
addresses with earlier defined register definitions.
Signed-off-by: Robert Delien <robert@delien.nl>
Common code has a mdelay() func, so use that instead of the usb-specific
wait_ms() func. This also fixes the build errors:
ohci-hcd.c: In function 'submit_common_msg':
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1519:9: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1816:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1827:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1844:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1563:11: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1583:9: sorry, unimplemented: called from here
make[1]: *** [ohci-hcd.o] Error 1
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Marek Vasut <marex@denx.de>
All boards are using the gen_atmel_mci driver now, so no need
to carry the old driver around.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Boards can select either the 'built-in' parser or the hush parser. We
should not call builtin_run_command() if we are using the hush parser.
We use run_command() instead, since it knows how to call the correct
parser.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
The current run_command() is only one of the parsing options - the other
is hush. We should not call run_command() when the hush parser is being
used. So we rename this function to better explain its purpose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Mainline kernel for OMAP3 doesn't enable L2 cache
It expects L2$ to be enabled by ROM-code/bootloader.
Leaving L2$ enabled can be troublesome in cases where
the L2 cache is not under CP15 control, such as in
Cortex-A9. This problem is explained in detail in
the commit dc7100f408
However, this problem doesn't apply to Cortex-A8
because L2$ in Cortex-A8 is under CP15 control and
hence the generic armv7 maintenance opertions work
for it.
As such we can make an exception for OMAP3 and
leave the L2$ enabled when we jump to kernel. This
is done by removing the strongly-linked implementation
of v7_outer_cache_disable() and allowing it to fall
back to the weakly linked implementation that doesn't
do anything.
Signed-off-by: Aneesh V <aneesh@ti.com>
In commit 2d575e4685 a separate header
file was introduced for the DM6467T EVM, include/configs/davinci_dm6467Tevm.h.
The substantial difference between the davinci_dm6467evm and the
davinci_dm6467Tevm configuration is a single bit in the hardware revision
that is passed to the Linux kernel and davinci_dm6467evm has
REFCLK_FREQ = 27000000 where as davinci_dm6467Tevm.h has a
REFCLK_FREQ = 33000000.
This patch removes include/configs/davinci_dm6467Tevm.h. Instead the
include/configs/davinci_dm6467evm.h configuration is used for DM6467T EVMs and
renamed CFG_REFCLK_FREQ to CONFIG_REFCLK_FREQ and CONFIG_REFCLK_FREQ is defined
in boards.cfg.
Signed-off-by: Prabhakar Lad <prabhakar.csengg@gmail.com>
Cc: Tom Rini <trini@ti.com>
check for the return status for eth_getenv_enetaddr_by_index()
and eth_setenv_enetaddr() functions and print appropriate message
on failure.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
get_reset_cause() function is only used inside print_cpuinfo(), so let it be
defined only when CONFIG_DISPLAY_CPUINFO is selected.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
