This patch sync with Brian's patch on Linux in nand_flash_detect_onfi()
commit b7b1a29d94c17e4341856381bccb4d17495bea60
Author: Brian Norris <computersforpeace@gmail.com>
Date: Sun Dec 12 00:23:33 2010 -0800
mtd: nand: rearrange ONFI revision checking, add ONFI 2.3
In checking for the ONFI revision, the first conditional (for checking
"unsupported" ONFI) seems unnecessary. All ONFI revisions should be
backwards-compatible; even if this is not the case on some newer ONFI
revision, it should simply fail the second version-checking if-else block
(i.e., the bit-fields for 1.0, 2.0, etc. would not be set to 1). Thus, we
move our "unsupported" condition after having checked each bit field.
Also, it's simple enough to add a condition for ONFI revision 2.3. Note
that this does *NOT* mean we handle all new features of ONFI versions
above 1.0.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Florian Fainelli <ffainelli@freebox.fr>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
This patch sync with David's patch on Linux in nand_flash_detect_onfi()
commit 4ccb3b4497ce01fab4933704fe21581e30fda1a5
Author: David Woodhouse <David.Woodhouse@intel.com>
Date: Fri Dec 3 16:36:34 2010 +0000
mtd: nand: Fix integer overflow in ONFI detection of chips >= 4GiB
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
The omap24xx driver only seems to support devices that have a single subaddress
byte. With these types of devices, the first access in a bus transaction is
usually a write (writes the subaddress) followed by either a read or write to
access the devices registers.
Many such devices will respond to a read as the first access, but there are at
least some that will NACK such a read. (e.g. ADV7180.)
The probe function attempts to detect a devices ACK to a read access only and
fails to find devices that NACK a read.
This commit modifies the probe function to start a write instead. This detects
devices that respond to reads (since they must also respond to writes) as well
as those that only respond to writes. The bus is immediately set to idle after a
(N)ACK avoiding actually writing anything to the device.
Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Commit 6ee1416e81 (mtd, cfi: introduce
void flash_protect_default(void)) introduced a bug which resulted in
boards that define CONFIG_SYS_FLASH_AUTOPROTECT_LIST not compiling with
the the following errors and warning:
ptyser@petert u-boot $ make -s xpedite520x
Configuring for xpedite520x board...
cfi_flash.c: In function 'flash_protect_default':
cfi_flash.c:2118: error: 'i' undeclared (first use in this function)
cfi_flash.c:2118: error: (Each undeclared identifier is reported only once
cfi_flash.c:2118: error: for each function it appears in.)
cfi_flash.c:2118: error: 'apl' undeclared (first use in this function)
cfi_flash.c:2118: error: invalid application of 'sizeof' to incomplete type 'struct apl_s'
cfi_flash.c: In function 'flash_init':
cfi_flash.c:2137: warning: unused variable 'apl'
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Reported-by: Kumar Gala <galak@kernel.crashing.org>
Cc: Heiko Schocher <hs@denx.de>
Hi Terry,
> So I guess:
> mmc_init calls mmc_send_op_cond that set high_capacity,
> than it calls mmc_startup, that, with MMC_CMD_SEND_CSD command, set
> the capacity, using values in CSD register.
> So I guess that mmc_change_freq should not recalculate high_capacity.
>
> It seems better, isn't it?
>
> Regards,
> Raffaele
>
Finally I think that it is enough to apply the following patch in order
to fix the issue.
Regards,
Raffaele
Signed-off-by: Andy Fleming <afleming@freescale.com>
Defining CONFIG_MMC_TRACE in the include board file it is possible to activate
a tracing support.
This code helps in case of eMMC hw failure or to investigate possible eMMC
initialization issues.
Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The first SEND_OP_COND (CMD1) command added is used to ask card capabilities.
After it an AND operation is done between card capabilities and host
capabilities (at the moment only for the voltage field).
Finally the correct value is sent to the MMC, waiting that the card
exits from busy state.
Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
Signed-off-by: Andy Fleming <afleming@freescale.com>
It is recommended to check card status after these kind of commands.
This is done using CMD13 (SEND_STATUS) JEDEC command until
the card is ready.
In case of error the card status field is displayed.
Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This patch supports mmc/sd card with spi interface. It is based on
the generic mmc framework. It works with SDHC and supports multi
blocks read/write.
The crc checksum on data packet is enabled with the def,
There is a subcomamnd "mmc_spi" to setup spi bus and cs at run time.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Andy Fleming <afleming@freescale.com>
These local vars need not be writable nor exported.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
As DATA_ERROR includes the value IRQSTAT_DTOE, a timeout error
would yield the first error return instead of TIMEOUT.
By swapping the test TIMEOUTs are reported as such
An alternate solution would be to remove the IRQSTAT_DTOE from the DATA_ERROR define
but as that one might be less desired I've opted for the simplest solution
Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This patch adds CONFIG_SPI_IDLE_VAL to cf_spi.c
The default setting is 0x0 to behave same as current version, in case
CONFIG_SPI_MMC is set, the value is set to 0xFFFF (all ones). In either
case, the value can be overwritten by board configuration.
Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The maximum blocks value was hardcoded to 65535 due to a 16 bit
register length. The value can change for different platforms.
This patch makes the default the current value of 65535, but it
is configurable for other platforms.
Signed-off-by: Matt Waddel <matt.waddel@linaro.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
1. Move header to include/faraday
2. Fix include path in ftwdt010_wdt.c
3. Fix function prototype and declaration to
- ftwdt010_wdt_settimeout
- ftwdt010_wdt_reset
- ftwdt010_wdt_disable
4. Add "#if definde (CONFIG_HW_WATCHDOG)" let user have flexibilty
to choose which better to his product.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
This patch adds a new member to struct spi_flash (u16 sector_size)
and updates the spi flash drivers to start populating it.
This parameter can be used by spi flash commands that need to round
up units of operation to the flash's sector_size.
Having this number in one place also allows duplicated code to be
further collapsed into one common location (such as erase parameter
and the detected message).
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The AT45 flashes are completely different (at the command set and
status register level) from all other SPI flashes, so we can't unify
their logic with common code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Faraday ftwdt010 watchdog is an architecture independant
watchdog. It is usually used in SoC chip design.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Add Intel E1000 82574L PCIe card support. Test on MPC8544DS
and MPC8572 board.
Add the missing contact information for future support.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
This patch fixes ea20 after 8ef583a035 where
the u-boot custom PHY_ macros were replaced with those of linux/mii.h MII_
definitions except in the RMII support for davinci_emac. Probably also due to
the merge path of changes in 2010.12.
Signed-off-by: Ben Gardiner<bengardiner@nanometrics.ca>
CC: Mike Frysinger <vapier@gentoo.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
All of the spi flash drivers implement the status register polling for
detecting the device ready state, so unify them all in a new helper
function -- spi_flash_wait_ready.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
level register description has been changed:
9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Don't forget to count full data size for the multiblock operation request.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The timer register is 32bits, not 16bit, so 0xFFFF won't fill it.
Write out -1 to make sure to fill the whole thing.
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
collect code which protects default sectors in a function, called
flash_protect_default. So boardspecific code can call it too.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
P1021 has some QE pins which need to be set in pmuxcr register before
using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and
UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to
be released after MII access because QE12 pin is muxed with LBCTL signal.
Also added relevant QE support defines unique to P1021.
The P1021 QE is shared on P1012, P1016, and P1025.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add ULI1575 EHCI controller to the list of the supported devices.
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW
entries consider them good and mark them used.
In the NAND SPL case we skip re-initializing based on the law_table
since the SPL phase already did that.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
FSL PCIe controller v2.1:
- New MSI inbound window
- Same Inbound windows address as PCIe controller v1.x
Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window
FSL PCIe controller v2.2 and v2.3:
- Different addresses for PCIe inbound window 3,2,1
- Exposed PCIe inbound window 0
- New PCIe interrupt status register
Added new Interrupt Status register to struct ccsr_pci & updated pit_t array
size to reflect the 4 inbound windows.
To maintain backward compatiblilty, on V2.2 or greater controllers we
start with inbound window 1 and leave inbound 0 with its default value
(which maps to CCSRBAR).
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch adds support for the PI7C9X442SL PCIe EHCI host controller
from Pericom.
Tested at P4080DS eval board from Freescale.
Signed-off-by: Ralf Trübenbach <ralf.truebenbach@men.de>
Cc: Remy Bohmer <linux@bohmer.net>
The anomaly workarounds we need for older silicon might break things
if used on newer versions where the anomalies don't exist. So check
the silicon rev at runtime too.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
