mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-30 08:30:50 +09:00
b6ccd2c9de
FSL PCIe controller v2.1: - New MSI inbound window - Same Inbound windows address as PCIe controller v1.x Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window FSL PCIe controller v2.2 and v2.3: - Different addresses for PCIe inbound window 3,2,1 - Exposed PCIe inbound window 0 - New PCIe interrupt status register Added new Interrupt Status register to struct ccsr_pci & updated pit_t array size to reflect the 4 inbound windows. To maintain backward compatiblilty, on V2.2 or greater controllers we start with inbound window 1 and leave inbound 0 with its default value (which maps to CCSRBAR). Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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| .. | ||
| bios_emulator | ||
| block | ||
| dma | ||
| fpga | ||
| gpio | ||
| hwmon | ||
| i2c | ||
| input | ||
| misc | ||
| mmc | ||
| mtd | ||
| net | ||
| pci | ||
| pcmcia | ||
| power | ||
| qe | ||
| rtc | ||
| serial | ||
| spi | ||
| twserial | ||
| usb | ||
| video | ||
| watchdog | ||