Commit Graph

1181 Commits

Author SHA1 Message Date
Tom Rini
d024236e5a Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:48 -04:00
Bin Meng
ca5eb0c5fb bios: vesa: Guard setting vesa mode with CONFIG_FRAMEBUFFER_SET_VESA_MODE
If CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set, don't switch
graphics card to VESA mode. This applies to both native mode
and emulator mode of running the VGA BIOS.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-16 22:38:35 +08:00
Bin Meng
45519924a0 x86: Rename e820entry to e820_entry
This changes 'struct e820entry' to 'struct e820_entry' to conform
with the coding style.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-04-16 16:54:51 +08:00
Bin Meng
87af71c2ea x86: Use 'unsigned int' in install_e820_map() functions
This fixes the following checkpatch warning:

  warning: Prefer 'unsigned int' to bare use of 'unsigned'

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-04-16 16:54:51 +08:00
Lukasz Majewski
014d7b13ae x86: Update the io.h file to use {out|in}_{be|le}X macros
The commit 3f70a6f577 ("x86: Add clr/setbits functions")
introduced the {read|write}_ macros to manipulate data.

Those macros are not used by any code in the u-boot project (despite the
io.h itself). Other architectures use io.h with {in|out}_* macros.

This commit brings some unification across u-boot supported architectures.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-04-16 16:54:51 +08:00
Ivan Gorinov
53cabe3d8e x86: Add 64-bit memory-mapped I/O functions
Add readq() and writeq() definitions for x86.

Please note: in 32-bit code readq/writeq will generate two 32-bit
memory access instructions instead of one atomic 64-bit operation.

Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-04-16 16:54:51 +08:00
Heinrich Schuchardt
f4cf153a48 efi_loader: correctly set the machine type in the PE header
The portable executable header has a field describing the machine type.
The machine type should match the binary. So on i386 we should use
IMAGE_FILE_MACHINE_I386 and on x86_64 we should use
IMAGE_FILE_MACHINE_AMD64. The actual value is issued by the objcopy
command invoked in scripts/Makefile.lib in depdendence of the value of
EFI_TARGET.

The value is used both for EFI_STUB and for EFI_LOADER.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-09 10:20:59 +02:00
Ivan Gorinov
5d73292cf8 x86: zImage: Pass working device tree data to the kernel
On x86 platforms, U-Boot does not pass Device Tree data to the kernel.
This prevents the kernel from using FDT loaded by U-Boot.

Read the working FDT address from the "fdtaddr" environment variable
and add a copy of the FDT data to the kernel setup_data list.

Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add #include <linux/libfdt.h> to zimage.c to fix build error]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-03-30 16:06:58 +08:00
Patrick Delaunay
b8aa55cb64 common: move init_helpers.h prototypes in init.h
Merge init_helpers.h in the new file init.h
with only prototypes for init_cache_f_r
used in common/board_f.c

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-16 14:56:59 -04:00
Masahiro Yamada
b08c8c4870 libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.

This commit moves the header code:
  include/libfdt.h         -> include/linux/libfdt.h
  include/libfdt_env.h     -> include/linux/libfdt_env.h

and replaces include directives:
  #include <libfdt.h>      -> #include <linux/libfdt.h>
  #include <libfdt_env.h>  -> #include <linux/libfdt_env.h>

Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-05 10:16:28 -05:00
Alexey Brodkin
4280342adb fdt: Implement weak arch_fixup_fdt()
Only ARM and in some configs MIPS really implement arch_fixup_fdt().
Others just use the same boilerplate which is not good by itself,
but what's worse if we try to build with disabled CONFIG_CMD_BOOTM
and enabled CONFIG_OF_LIBFDT we'll hit an unknown symbol which was
apparently implemented in arch/xxx/lib/bootm.c.

Now with weak arch_fixup_fdt() right in image-fdt.c where it is
used we get both items highlighted above fixed.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-02-18 12:53:38 -07:00
Tom Rini
d0c0752add x86: quark: Fix unused warnings
The variable t_rfc is never used, so drop it.  The variables ddr_wctl
and ddr_wcmd are only used in certain manual instances, so guard their
declaration by the same check as their use.

Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2018-01-30 22:34:38 +08:00
Bin Meng
45410da714 x86: acpi: Use an API to get the ACPI RSDP table address
At present the acpi_rsdp_addr variable is directly referenced in
setup_zimage(). This changes to use an API for better encapsulation
and extension.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-01-30 22:34:37 +08:00
Andy Shevchenko
3469bf4274 x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parameters
New field acpi_rsdp_addr, which has been introduced in boot protocol
v2.14 [1], in boot parameters tells kernel the exact address of RDSP
ACPI table. Knowing it increases robustness of the kernel by avoiding
in some cases traversal through a part of physical memory.
It will slightly reduce boot time by the same reason.

[1] See Linux kernel commit

  2f74cbf ("x86/boot: Add the ACPI RSDP address to struct setup_header::acpi_rdsp_addr")
  @ https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=2f74cbf

for the details.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: updated the kernel commit git URL and fixed one style issue]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-01-30 14:29:07 +08:00
Andy Shevchenko
378960d8c2 x86: zImage: Move subarch assignment out of cmd_line check
The commit

  20bfac0599 ("x86: zImage: add Intel MID platforms support")

introduced an assignment of subarch field in boot parameters, though
missed the right place of doing that. It doesn't matter if we have or
not a kernel command line supplied, we just set that field. Although
guard it by protocol version which supports it.

Fixes: 20bfac0599 ("x86: zImage: add Intel MID platforms support")
Cc: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-01-30 14:29:07 +08:00
Andy Shevchenko
7b36dbdec7 x86: Fix reference to QEMU variant of write_acpi_tables()
The commit

  eece493a7a ("cmd: qfw: bring ACPI generation code into qfw core")

moves ACPI related code to another file and missed an update of
references in acpi_table.c.

Do it now.

Fixes: eece493a7a ("cmd: qfw: bring ACPI generation code into qfw core")
Cc: Miao Yan <yanmiaobest@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-01-30 14:29:07 +08:00
Andy Shevchenko
3ffb33d636 x86: tangier: Make _CRS for BTH0 Serialized to avoid warning
ASL compiler warns:

  ASL     board/intel/edison/dsdt.asl
  board/intel/edison/dsdt.asl.tmp    238:             Method (_CRS, 0, NotSerialized)
  Remark   2120 -      Control Method should be made Serialized ^  (due to creation of named objects within)

Do as suggested by ASL compiler.

Fixes: 5d8c4ebd95 ("x86: tangier: Add Bluetooth to ACPI table")
Reported-by: Ferry Toth <fntoth@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-01-30 14:29:07 +08:00
Andy Shevchenko
5d8c4ebd95 x86: tangier: Add Bluetooth to ACPI table
As defined on reference board followed by Intel Edison a Bluetooth
device is attached to HSU0, i.e. PCI 0000:04.1.

Describe it in ACPI accordingly.

Note, we use BCM2E95 ID here as one most suitable for such device based
on the description in commit message of commit 89ab37b489d1
	("Bluetooth: hci_bcm: Add support for BCM2E95 and BCM2E96")
in the Linux kernel source tree.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-08 16:52:25 +08:00
Andy Shevchenko
d08953e045 x86: tangier: Use actual GPIO hardware numbers
The recent commit 03c4749dd6c7
  ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation")
in the Linux kernel reveals the issue we have in ACPI tables here,
i.e. we must use hardware numbers for GPIO resources and,
taking into consideration that GPIO and pin control are *different* IPs
on Intel Tangier, we need to supply numbers properly.

Besides that, it improves user experience since the official documentation
for Intel Edison board is referring to GPIO hardware numbering scheme.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-08 16:52:25 +08:00
Tom Rini
8e18f34c28 x86: Move commands from under arch/x86 to cmd/x86/
We only need to compile and link these files when building for full
U-Boot.  Move them to under cmd/x86/ to make sure they aren't linked in
and undiscarded due to u_boot_list_2_cmd_* being included).

Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-01-08 16:52:22 +08:00
Andy Shevchenko
1602d215b5 x86: tangier: Use official ACPI HID for FLIS IP
FLIS IP since now gets its own ACPI ID.
Drop PRP0001 workaround in favour of official ACPI HID.

Corresponding kernel commit dabd4bc6de2b

	pinctrl: intel: merrifield: Introduce ACPI device table

in the pin control subsystem tree [1] targeting v4.16.

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/commit/?h=for-next&id=dabd4bc6de2b

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-12-21 09:18:05 +08:00
Tuomas Tynkkynen
9fd95ef0d3 ata: Migrate CONFIG_SCSI_AHCI to Kconfig
And use 'imply' liberally.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2017-12-12 18:13:19 -05:00
Stefan Roese
aa7839b39c x86: lib: Implement standalone __udivdi3 etc instead of libgcc ones
This patch removes the inclusion of the libgcc math functions and
replaces them by functions coded in C, taken from the coreboot
project. This makes U-Boot building more independent from the toolchain
installed / available on the build system.

The code taken from coreboot is authored from Vadim Bendebury
<vbendeb@chromium.org> on 2014-11-28 and committed with commit
ID e63990ef [libpayload: provide basic 64bit division implementation]
(coreboot git repository located here [1]).

I modified the code so that its checkpatch clean without any
functional changes.

[1] git://github.com/coreboot/coreboot.git

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30 13:50:17 +08:00
Anatolij Gustschin
254752494a Revert "x86: bootm: Fix FIT image booting on x86"
This reverts commit 13c531e52a.

The error message with FIT style image mentioned in the above commit
only happens when booting using FIT image containing bzImage kernel
and without setup node (setup.bin). The current documentation for
x86 FIT support in doc/uImage.FIT/x86-fit-boot.txt mentions that
kernel's setup.bin file is required for building x86 FIT images.
The above commit breaks FIT images generated as described in the
documentation. Revert it to allow booting with images built in the
documented way.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30 13:50:17 +08:00
Heinrich Schuchardt
39670c341f x86: don't compare pointers to 0
x86_vendor_name is defined as

static const char *const x86_vendor_name[]

So its elements should not be compared to 0.

Remove superfluous paranthesis.

Problem identified with Coccinelle.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30 13:50:17 +08:00
Anton Gerasimov
80f3425c57 x86: qemu: Move Cache-As-RAM memory from area mapped to ROM
ROM has been made read-only in qemu recently (namely commit 208fa0e4:
"pc: make 'pc.rom' readonly when machine has PCI enabled"). So this
patch restores compatibility between U-Boot and qemu.

Signed-off-by: Anton Gerasimov <anton@advancedtelematic.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: mention qemu commit title in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30 13:50:17 +08:00
Masahiro Yamada
d6a0c78a4e pylibfdt: compile pylibfdt only when dtoc/binman is necessary
Currently, pylibfdt is always compiled if swig is installed on your
machine.  It is really annoying because most of targets (excepts
x86, sunxi, rockchip) do not use dtoc or binman.

"checkbinman" and "checkdtoc" are wrong.  It is odd that the final
build stage checks if we have built necessary tools.  If your platform
depends on dtoc/binman, you must be able to build pylibfdt.  If swig
is not installed, it should fail immediately.

I added PYLIBFDT, DTOC, BINMAN entries to Kconfig.  They should be
property select:ed by platforms that need them.  Kbuild will descend
into scripts/dtc/pylibfdt/ only when CONFIG_PYLIBFDT is enabled.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-17 07:43:32 -05:00
Bin Meng
411898dc87 x86: acpi: Put sleepstates.asl to the common place
The supported sleep states are generic on Intel processors. Move the
ASL definition to the common place.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
dc80d3b230 x86: fsp: graphics: Add some notes about the graphics info hob
On some platforms (eg: Braswell), the FSP will not produce the
graphics info HOB unless you plug some cables to the display
interface (eg: HDMI) on the board. Add such notes in the FSP
video driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
4c9f4c5ee4 x86: braswell: cherryhill: Update dts for SPI lock down
Intel Braswell FSP requires SPI controller settings to be locked down,
let's do this in the chrryhill.dts and remove previous Kconfig option.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
fb2c53091f Revert "x86: fsp: Configure SPI opcode registers before SPI is locked down"
This reverts commit 1e6ebee667.

It's not appropriate to call the Intel SPI driver specific stuff in
the FSP codes. We may add a simple DTS property "intel,spi-lock-down"
and let the Intel SPI driver call these stuff instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-27 15:13:47 +08:00
Bin Meng
aa9c5956c9 x86: Fix ACPI resume dependency to MRC cache
In an S3 resume path, MRC cache is mandatory. Enforce the dependency
in the Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
3a856473fd env: x86: braswell: Set ENV_IS_IN_SPI_FLASH as default
Imply does not work for a Kconfig choice. Update ENV_IS_IN_SPI_FLASH
to be the default one for Intel Braswell.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
4a5a7fcac2 x86: braswell: Fix unexpected crash during Linux kernel boot
It was observed that when booting Linux kernel on Intel Cherry Hill
board, unexpected crash happens quite randomly. Sometimes kernel
just oops, while sometimes kernel throws MCE errors and hangs:

  mce: [Hardware Error]: Machine check events logged
  mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 4: c400000000010151
  mce: [Hardware Error]: TSC 0 ADDR 130f3f2c0
  mce: [Hardware Error]: PROCESSOR 0:406c3 TIME 1508160686 SOCKET 0 APIC 0 microcode 363

This looks like a hardware error per mcelog. After debugging, it
seems turning off turbo mode on the processor does not expose this
behavior, although U-Boot runs OK with turbo mode on. Suspect it is
related to an errata of Braswell processor.

To fix this, remove the Braswell cpu driver which does the turbo
mode configuration, and switch to use the generic cpu-x86 driver.
Also there is a configuration option in the FSP that turns on the
turbo mode and that has been turned off too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Bin Meng
83262f99cd x86: baytrail: fsp: Move Azalia update codes to board
Azalia configuration may be different across boards, hence it's not
appropriate to do that in the SoC level. Instead, let's make the
SoC update_fsp_azalia_configs() routine as a weak version, and do
the actual work in the board codes.

So far it seems only som-db5800-som-6867 board enables the Azalia.
Move the original codes into som-db5800-som-6867.c.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
Bin Meng
f6859558ca x86: baytrail: fsp: Use a function to update the Azalia config pointer
At present we directly pass the Azalia config pointer to the FSP UPD.
This updates to use a function to do the stuff, like Braswell does.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
Bin Meng
abddcd52ab x86: fsp: Consolidate Azalia header file
So far there are two copies of Azalia struct defines with one in
baytrail and the other one in braswell. This consolidates these
two into one, put it in the common place, and remove the prefix
pch_ to these structs to make their names more generic.

This also corrects reset_wait_timer from us to ms.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
Bin Meng
3322a8e1a3 x86: Turn off running VGA ROM during S3 resume
This is only needed when graphics console is used. For kernel with
native graphics driver, this can be turned off to speed up.

Change this option's default to n in the Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
Bin Meng
febdfaabc7 x86: baytrail: Fix unstable ACPI S3 resume
It was observed that when booting a Ubuntu 16.04 kernel, doing ACPI
S3 suspend/resume sometimes causes the Ubuntu kernel hang forever.
The issue is however not reproduced with a kernel built from i386/
x86_64 defconfig configuration.

The unstability is actually caused by unexpected interrupts being
generated during the S3 resume. For some unknown reason, FSP (gold4)
for BayTrail configures the GPIO DFX5 PAD to enable level interrupt
(bit 24 and 25). As this pin keeps generating interrupts during an
S3 resume, and there is no IRQ requester in the kernel to handle it,
the kernel seems to hang and does not continue resuming.

Clear the mysterious interrupt bits for this pin.

Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-10-19 11:37:51 +08:00
Andy Shevchenko
39665beed6 x86: tangier: Enable ACPI support for Intel Tangier
Intel Tangier SoC is a part of Intel Merrifield platform which doesn't
utilize ACPI by default. Here is an attempt to unleash ACPI flexibility
power on Intel Merrifield based platforms.

The change brings minimum support of the devices that found on
Intel Merrifield based end user device.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-10-07 15:07:59 +08:00
Masahiro Yamada
9b643e312d treewide: replace with error() with pr_err()
U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// <smpl>
@@@@
-error
+pr_err
 (...)
// </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-04 11:59:44 -04:00
Paul Burton
6f01316f36 x86: Use asm-generic/io.h
Convert the x86 architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for x86 this is primarily a matter of moving code.

This has only been build-tested, feedback from architecture maintainers
is welcome.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-02 21:52:22 -04:00
Heinrich Schuchardt
8a1c44271c x86: ivybridge: remove unused variables
legacy_hole_base_k and legacy_hole_size_k are defined but
not used.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16 14:57:44 +08:00
Simon Glass
2ff50f5fa4 dm: x86: Allow TSC timer to be used before DM is ready
With bootstage we need access to the timer before driver model is set up.
To handle this, put the required state in global_data and provide a new
function to set up the device, separate from the driver's probe() method.

This will be used by the 'early' timer also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-09-16 14:57:44 +08:00
Bin Meng
eb45787b39 x86: Support Intel Cherry Hill board
This adds support to Intel Cherry Hill board, a board based on
Intel Braswell SoC. The following devices are validated:

- serial port as the serial console
- on-board Realtek 8169 ethernet controller
- SATA AHCI controller
- EMMC/SDHC controller
- USB 3.0 xHCI controller
- PCIe x1 slot with a graphics card
- ICH SPI controller with an 8MB Macronix SPI flash
- Integrated graphics device as the video console

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
507f1024b8 x86: braswell: Disable PUNIT power configuration for B0 stepping
FSP's built-in UPD configuration enables PUNIT power configuration,
but on B0 stepping, this causes CPU hangs in fsp_init(). Disable it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
fffad9264a x86: braswell: Add FSP configuration
Add FSP related configuration for Braswell.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
e61a2687b3 x86: braswell: Add microcode for B0/C0/D0 stepping SoC
This adds microcode device tree fragment for Braswell B0 (406C2),
C0 (406C3) and D0 (406C4) stepping SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
de9ac9a1b9 x86: Add Intel Braswell SoC support
This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.

Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
Bin Meng
b3fd2126dc x86: fsp: Update fsp command to show spec 1.1 header
FSP spec 1.1 adds 3 new APIs and their offsets are in the header.
Update the 'fsp hdr' command to show these new entries.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00