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https://github.com/brain-hackers/u-boot-brain
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x86: tangier: Enable ACPI support for Intel Tangier
Intel Tangier SoC is a part of Intel Merrifield platform which doesn't utilize ACPI by default. Here is an attempt to unleash ACPI flexibility power on Intel Merrifield based platforms. The change brings minimum support of the devices that found on Intel Merrifield based end user device. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Andy Shevchenko
Bin Meng
parent
b6519b777d
commit
39665beed6
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@ -5,3 +5,4 @@
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#
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obj-y += car.o tangier.o sdram.o
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obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
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87
arch/x86/cpu/tangier/acpi.c
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87
arch/x86/cpu/tangier/acpi.c
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@ -0,0 +1,87 @@
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/*
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* Copyright (c) 2017 Intel Corporation
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*
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* Partially based on acpi.c for other x86 platforms
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <dm/uclass-internal.h>
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#include <asm/acpi_table.h>
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#include <asm/ioapic.h>
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#include <asm/mpspec.h>
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#include <asm/tables.h>
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#include <asm/arch/global_nvs.h>
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void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
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void *dsdt)
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{
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struct acpi_table_header *header = &(fadt->header);
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memset((void *)fadt, 0, sizeof(struct acpi_fadt));
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acpi_fill_header(header, "FACP");
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header->length = sizeof(struct acpi_fadt);
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header->revision = 6;
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fadt->firmware_ctrl = (u32)facs;
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fadt->dsdt = (u32)dsdt;
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fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
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fadt->iapc_boot_arch = ACPI_FADT_VGA_NOT_PRESENT |
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ACPI_FADT_NO_PCIE_ASPM_CONTROL;
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fadt->flags =
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ACPI_FADT_WBINVD |
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ACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON |
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ACPI_FADT_SEALED_CASE | ACPI_FADT_HEADLESS |
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ACPI_FADT_HW_REDUCED_ACPI;
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fadt->minor_revision = 2;
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fadt->x_firmware_ctl_l = (u32)facs;
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fadt->x_firmware_ctl_h = 0;
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fadt->x_dsdt_l = (u32)dsdt;
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fadt->x_dsdt_h = 0;
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header->checksum = table_compute_checksum(fadt, header->length);
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}
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u32 acpi_fill_madt(u32 current)
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{
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current += acpi_create_madt_lapics(current);
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current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
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io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
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return current;
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}
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u32 acpi_fill_mcfg(u32 current)
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{
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/* TODO: Derive parameters from SFI MCFG table */
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current += acpi_create_mcfg_mmconfig
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((struct acpi_mcfg_mmconfig *)current,
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0x3f500000, 0x0, 0x0, 0x0);
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return current;
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}
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void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
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{
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struct udevice *dev;
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int ret;
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/* at least we have one processor */
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gnvs->pcnt = 1;
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/* override the processor count with actual number */
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ret = uclass_find_first_device(UCLASS_CPU, &dev);
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if (ret == 0 && dev != NULL) {
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ret = cpu_get_count(dev);
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if (ret > 0)
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gnvs->pcnt = ret;
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}
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}
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16
arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl
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16
arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl
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@ -0,0 +1,16 @@
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/*
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* Copyright (c) 2017 Intel Corporation
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*
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* Partially based on global_nvs.asl for other x86 platforms
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/acpi/global_nvs.h>
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OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
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Field(GNVS, ByteAcc, NoLock, Preserve)
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{
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Offset (0x00),
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PCNT, 8, /* processor count */
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}
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31
arch/x86/include/asm/arch-tangier/acpi/platform.asl
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31
arch/x86/include/asm/arch-tangier/acpi/platform.asl
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/*
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* Copyright (c) 2017 Intel Corporation
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*
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* Partially based on platform.asl for other x86 platforms
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/acpi/statdef.asl>
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/*
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* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0.
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*/
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Method(_PTS, 1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK, 1)
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{
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Return (Package() {0, 0})
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}
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/* ACPI global NVS */
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#include "global_nvs.asl"
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Scope (\_SB)
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{
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#include "southcluster.asl"
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}
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298
arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
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298
arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
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@ -0,0 +1,298 @@
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/*
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* Copyright (c) 2017 Intel Corporation
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*
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* Partially based on southcluster.asl for other x86 platforms
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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Device (PCI0)
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{
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Name (_HID, EISAID("PNP0A08")) /* PCIe */
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Name (_CID, EISAID("PNP0A03")) /* PCI */
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Name (_ADR, 0)
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Name (_BBN, 0)
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Name (MCRS, ResourceTemplate()
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{
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/* Bus Numbers */
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WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
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/* IO Region 0 */
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
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/* PCI Config Space */
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IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
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/* IO Region 1 */
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
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/* GPIO Low Memory Region */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000ddcc0, 0x000ddccf, 0x00000000,
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0x00000010, , , GP00)
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/* PSH Memory Region 0 */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x04819000, 0x04898fff, 0x00000000,
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0x00080000, , , PSH0)
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/* PSH Memory Region 1 */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x04919000, 0x04920fff, 0x00000000,
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0x00008000, , , PSH1)
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/* SST Memory Region */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x05e00000, 0x05ffffff, 0x00000000,
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0x00200000, , , SST0)
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/* PCI Memory Region */
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x80000000, 0xffffffff, 0x00000000,
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0x80000000, , , PMEM)
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})
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Method (_CRS, 0, Serialized)
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{
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Return (MCRS)
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}
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Method (_OSC, 4)
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{
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/* Check for proper GUID */
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If (LEqual(Arg0, ToUUID("33db4d5b-1ff7-401c-9657-7441c03dd766"))) {
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/* Let OS control everything */
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Return (Arg3)
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} Else {
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/* Unrecognized UUID */
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CreateDWordField(Arg3, 0, CDW1)
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Or(CDW1, 4, CDW1)
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Return (Arg3)
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}
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}
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Device (SDHC)
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{
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Name (_ADR, 0x00010003)
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Name (_DEP, Package (0x01)
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{
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GPIO
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})
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Name (PSTS, Zero)
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Method (_STA)
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{
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Return (STA_VISIBLE)
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}
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Method (_PS3, 0, NotSerialized)
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{
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}
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Method (_PS0, 0, NotSerialized)
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{
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If (PSTS == Zero)
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{
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If (^^GPIO.AVBL == One)
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{
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^^GPIO.WFD3 = One
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PSTS = One
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}
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}
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}
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/* BCM43340 */
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Device (BRC1)
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{
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Name (_ADR, 0x01)
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Name (_DEP, Package (0x01)
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{
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GPIO
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})
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Method (_STA)
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{
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Return (STA_VISIBLE)
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}
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Method (_RMV, 0, NotSerialized)
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{
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Return (Zero)
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}
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Method (_PS3, 0, NotSerialized)
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{
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If (^^^GPIO.AVBL == One)
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{
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^^^GPIO.WFD3 = Zero
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PSTS = Zero
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}
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}
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Method (_PS0, 0, NotSerialized)
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{
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If (PSTS == Zero)
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{
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If (^^^GPIO.AVBL == One)
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{
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^^^GPIO.WFD3 = One
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PSTS = One
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}
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}
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}
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}
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Device (BRC2)
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{
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Name (_ADR, 0x02)
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Method (_STA, 0, NotSerialized)
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{
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Return (STA_VISIBLE)
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}
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Method (_RMV, 0, NotSerialized)
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{
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Return (Zero)
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}
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}
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}
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Device (SPI5)
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{
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Name (_ADR, 0x00070001)
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Name (RBUF, ResourceTemplate()
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{
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GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,
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"\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 91 }
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GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,
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"\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 92 }
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GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,
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"\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 93 }
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GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,
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"\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 94 }
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})
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Method (_CRS, 0, NotSerialized)
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{
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Return (RBUF)
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}
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/*
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* See
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* http://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt
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* for more information about GPIO bindings.
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*/
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Name (_DSD, Package () {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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Package () {
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"cs-gpios", Package () {
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^SPI5, 0, 0, 0,
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^SPI5, 1, 0, 0,
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^SPI5, 2, 0, 0,
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^SPI5, 3, 0, 0,
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},
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},
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}
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})
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Method (_STA, 0, NotSerialized)
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{
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Return (STA_VISIBLE)
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}
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}
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Device (I2C1)
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{
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Name (_ADR, 0x00080000)
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Method (_STA, 0, NotSerialized)
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{
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Return (STA_VISIBLE)
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}
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}
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Device (GPIO)
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{
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Name (_ADR, 0x000c0000)
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Method (_STA)
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{
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Return (STA_VISIBLE)
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}
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Name (AVBL, Zero)
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Method (_REG, 2, NotSerialized)
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{
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If (Arg0 == 0x08)
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{
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AVBL = Arg1
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}
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}
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OperationRegion (GPOP, GeneralPurposeIo, 0, 1)
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Field (GPOP, ByteAcc, NoLock, Preserve)
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{
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Connection (
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GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
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"\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 56 }
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),
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WFD3, 1,
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}
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}
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Device (PWM0)
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{
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Name (_ADR, 0x00170000)
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Method (_STA, 0, NotSerialized)
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{
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Return (STA_VISIBLE)
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}
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}
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}
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Device (FLIS)
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{
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Name (_HID, "PRP0001")
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Name (_DDN, "Intel Merrifield Family-Level Interface Shim")
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Name (RBUF, ResourceTemplate()
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{
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Memory32Fixed(ReadWrite, 0xFF0C0000, 0x00008000, )
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PinGroup("spi5", ResourceProducer, ) { 90, 91, 92, 93, 94, 95, 96 }
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PinGroup("uart0", ResourceProducer, ) { 115, 116, 117, 118 }
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PinGroup("uart1", ResourceProducer, ) { 119, 120, 121, 122 }
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PinGroup("uart2", ResourceProducer, ) { 123, 124, 125, 126 }
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PinGroup("pwm0", ResourceProducer, ) { 144 }
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PinGroup("pwm1", ResourceProducer, ) { 145 }
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PinGroup("pwm2", ResourceProducer, ) { 132 }
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PinGroup("pwm3", ResourceProducer, ) { 133 }
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})
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Method (_CRS, 0, NotSerialized)
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{
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Return (RBUF)
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}
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Name (_DSD, Package () {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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Package () {"compatible", "intel,merrifield-pinctrl"},
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}
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})
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Method (_STA, 0, NotSerialized)
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{
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Return (STA_VISIBLE)
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}
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}
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22
arch/x86/include/asm/arch-tangier/global_nvs.h
Normal file
22
arch/x86/include/asm/arch-tangier/global_nvs.h
Normal file
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@ -0,0 +1,22 @@
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/*
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* Copyright (c) 2017 Intel Corporation
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*
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* Partially based on global_nvs.h for other x86 platforms
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _GLOBAL_NVS_H_
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#define _GLOBAL_NVS_H_
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struct __packed acpi_global_nvs {
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u8 pcnt; /* processor count */
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/*
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* Add padding so sizeof(struct acpi_global_nvs) == 0x100.
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* This must match the size defined in the global_nvs.asl.
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*/
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u8 rsvd[255];
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};
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#endif /* _GLOBAL_NVS_H_ */
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