Commit Graph

36967 Commits

Author SHA1 Message Date
Marek Vasut
85f76628a0 ddr: altera: Staticize global variables
Just staticize global variables in sequencer, since there is no
point in having these symbols available outside of the DDR code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:45 +02:00
Marek Vasut
ea9aa2414e ddr: altera: Make DLEVEL behavior inclusive
Originally, the DLEVEL selects the debug level within the sequencer code,
but only displays the messages on that particular debug level. Tweak the
handling such that for particular debug level, debug messages on that
level and lower are displayed. This allows better regulation of debug
message verbosity.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:45 +02:00
Marek Vasut
70ed80af46 ddr: altera: Zero DM IN delay in scc_mgr_zero_group()
This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:45 +02:00
Marek Vasut
f3f777cdf0 ddr: altera: Remove unnecessary ODT mode config
There is no point in resetting the ODT setting if the write test
failed, since the code will always retry the calibration and thus
reconfigure the ODT anyway OR the code will fail calibration and
halt.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:44 +02:00
Marek Vasut
f5f8c411de ddr: altera: Remove unnecessary update of the SCC
Every invocation of the scc_mgr_set_dqs_en_delay_all_ranks() is
followed by SCC manager update. Moreover, only this function
triggers the SCC manager update internally. Thus, remove the
internal invocation to avoid triggering the update twice.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:44 +02:00
Marek Vasut
164eb23f49 ddr: altera: Fix DRAM end value in protection rule
The hi address bitfield in the protection rule must be set to
the last address in the region which the rule represents. The
behavior is now in-line with code generated by Quartus 15.1 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:44 +02:00
Marek Vasut
8e9e62c946 ddr: altera: Fix scc_mgr_set() argument order
The code should be setting registers to zero, not one register to value.
Swap the order of arguments to correct the behavior. The behavior is now
in-line with code generated by Quartus 15.1 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:44 +02:00
Marek Vasut
bba7711092 ddr: altera: Tweak DQS tracking enable handling
In the most unlikely case the DQS tracking was to be disabled,
make sure we do not errornously re-enable it. Note that DQS
tracking is enabled on all systems observed thus far.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:44 +02:00
Marek Vasut
abaf83619c ddr: altera: Replace ad-hoc constant with macro
The bit 22 is in fact DQS tracking enable bit (dqstrken) and there
is a macro for this bit already, so use it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:43 +02:00
Stephen Warren
108f841859 ARM: rpi: fix 64-bit CONFIG_SYS_TEXT_BASE
The Pi firmware has changed the default "kernel" load address for 64-bit
mode. The authors have confirmed that this is a deliberate and long-term
change. Adapt U-Boot to the new value.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2016-04-16 09:02:17 -04:00
Tom Rini
7e019daf7a drivers/tpm/tpm_tis_sandbox.c: Fix uninitialized variable use
In rollback_space_kernel we were not initializing the reserved fields
which should be for safety sake, and doing memset here means we don't
need to set the version field specifically either.

Reported-by: Coverity (CID: 143917)
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-04-15 08:14:37 -06:00
Stephen Warren
43c4d44e33 fdt: implement dev_get_addr_name()
This function parses the reg property based on an index found in the
reg-names property. This is required for bindings that are written
using reg-names rather than hard-coding indices in reg.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-04-15 08:14:37 -06:00
Tom Rini
690d8a92c1 sandbox: Enable many more commands
- Set CONFIG_SYS_CACHELINE_SIZE to ARCH_DMA_MINALIGN as that should be
  good enough.
- Make <asm/io.h> include <asm/types.h> like other arches do
- Enable many many more drivers in sandbox_defconfig so that we can get
  more build-time testing on this platform.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-04-15 08:14:37 -06:00
Tom Rini
f09144a220 test/dm/core.c: Make pre-reloc test use pre-reloc struct
LLVM 3.5 noted:
test/dm/core.c:41:35: warning: unused variable 'test_pdata_pre_reloc' [-Wunused-const-variable]
static const struct dm_test_pdata test_pdata_pre_reloc = {

And the correct fix here is that the driver_info_pre_reloc test should
use the test_pdata_pre_reloc not test_pdata_manual variable

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-04-14 11:51:39 -06:00
Jagan Teki
7b3dc45ea5 board: README.sandbox: Update dm test command
Update dm test command with pytest instead of ./test/dm/test-dm.sh

Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-04-14 11:51:39 -06:00
Jagan Teki
e57f9c8eef doc: driver-model: Update dm tests run using test.py
Since all the tests are implemented in pytest infrastructure,
So update the dm tests with the same instead of ./test/dm/test-dm.sh

Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-04-14 11:51:39 -06:00
Stefan Roese
770eb30ed9 dm: device.c: Minor coding-style fix
Fix multi-line comment indentation in device_bind()

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-04-14 11:51:39 -06:00
Nishanth Menon
2ae67aec5e dm: part: fix missing driver name in debug print
Fixes the following warning with PART_DEBUG enabled:
disk/part.c: In function ‘get_partition_info’:
disk/part.c:372:3: warning: format ‘%s’ expects a matching ‘char *’ argument [-Wformat]

Signed-off-by: Nishanth Menon <nm@ti.com>
2016-04-14 11:51:39 -06:00
Peng Fan
c3ab985362 dm: core: device: set pinctrl state for pinctrl device
We may have pinmux settings for pinctrl device, like the following
example:
"
&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog_1>;
	imx6ul-evk {
		pinctrl_hog_1: hoggrp-1 {
			fsl,pins = <
				MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059 /* SD1 CD */
				MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT	0x17059 /* SD1 VSELECT */
				MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
				MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x80000000
			>;
		};
	[......]
};
"

We should not only select pinctrl state for non pinctrl devices, we
need also to handle pin mux settings such as pinctrl_log for pinctrl
devices.

So at the end of probing process of pinctrl device, select the default
state of pinctrl device.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-14 11:51:39 -06:00
Tom Rini
ff6552e8cc xpress: Update <usb/ehci-fsl.h> include
This has been renamed to <usb/ehci-ci.h> some time ago but was missed
here.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-04-13 15:45:50 -04:00
Tom Rini
541c9be880 Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze 2016-04-13 12:53:11 -04:00
Michal Simek
58ed7f6693 ARM64: zynqmp: Use i2c cadence DM driver
Use i2c cadence DM driver for all zynqmp targets except ZCU102
because I2C muxes and PCA953x are not supported in the tree yet.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2016-04-13 18:29:07 +02:00
Moritz Fischer
fdec2d21ef dm: i2c: Add driver for Cadence I2C IP
This is a possible drop in replacement for drivers/i2c/zynq-i2c.c

Since this is cadence IP it has been renamed to cdns-i2c,
to make sense with the compatible string.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:07 +02:00
Moritz Fischer
17573c2791 i2c: Describe Cadence I2C devicetree bindings
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:07 +02:00
Michal Simek
ff9bd8e9ca ARM64: zynqmp: Enable pca953x driver for zcu102
zcu102 has two pca953x on i2c bus 0. Chips 0x20 and 0x21.
Enable option to work with these two chips.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:06 +02:00
Michal Simek
01b2a69907 GPIO: pca953x: Remove compilation warnings on arm64
Warnings:
w+../drivers/gpio/pca953x.c: In function ‘do_pca953x’:
w+../drivers/gpio/pca953x.c:220:5: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
w+../drivers/gpio/pca953x.c:233:10: warning: cast from pointer to
integer of different size [-Wpointer-to-int-cast]

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:06 +02:00
Michal Simek
f746b4cfd0 ARM64: zynqmp: Enable CMD_GPIO and DM_GPIO for ep108
Enable missing GPIO options.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:06 +02:00
Siva Durga Prasad Paladugu
251ab06d26 zynqmp: Kconfig: Enable ZYNQ_GPIO for ZynqMP
Enable ZYNQ_GPIO for ZynqMP using Kconfig. It enables the GPIO
driver support for ZynqMP.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:06 +02:00
Siva Durga Prasad Paladugu
404a00c7c9 gpio: zynqmp: Add GPIO driver support for ZynqMP
Add GPIO driver support for ZynqMP platform

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:06 +02:00
Siva Durga Prasad Paladugu
f17abcaedb gpio: zynq: Move the definitions to driver file
Move all the gpio definitions to driver file as
there is no use of them in other files.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:06 +02:00
Siva Durga Prasad Paladugu
de77a03bf2 gpio: zynq: Remove non driver model code
Remove non driver model support as it moved
to driver model. Dont need non driver model
anymore.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:06 +02:00
Siva Durga Prasad Paladugu
2978ae23fa gpio: Kconfig: Enable Zynq GPIO driver using kconfig
Enable DM GPIO and ZYNQ GPIO using kconfig instead of the board
config file.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:06 +02:00
Siva Durga Prasad Paladugu
68c7026e8d gpio: zynq: Convert Zynq GPIO to driver model
Convert Zynq GPIO driver to driver model

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:06 +02:00
Michal Simek
08afaf1b40 ARM64: zynqmp: Clean header after moving stuff to Kconfig
Moving stuff to Kconfig by script is keep some empty lines
or comment in the file. Remove them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:06 +02:00
Michal Simek
6c0c958de8 ARM64: zynqmp: Add support for zc1751 with DC cards
Support ZynqMP zc1751 with DC cards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:06 +02:00
Michal Simek
da81db61d5 ARM64: zynqmp: Add defconfig for zcu102 revB board
Support natively revB board. Till now support for revB was done via
zcu102 defconfig where device-tree was changed to revB.
This patch is adding direct defconfig for RevB.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:05 +02:00
Michal Simek
1f4f3d33c7 ARM64: zynqmp: Add support for ZCU102 platform
Add new board support.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:05 +02:00
Michal Simek
52be5c05a0 ARM64: zynqmp: Remove netdev.h from board file
Including netdev.h is causing compilation warning:
+ int fecmxc_register_mii_postcall(struct eth_device *dev, int
(*cb)(int));
+                                         ^
w+In file included from ../board/xilinx/zynqmp/zynqmp.c:9:0:
w+../include/netdev.h:204:41: warning: ‘struct eth_device’ declared
inside parameter list [enabled by default]
w+../include/netdev.h:204:41: warning: its scope is only this definition
or declaration, which is probably not what you want [enabled by default]

This patch removes it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:05 +02:00
Michal Simek
658b3a5639 ARM64: zynqmp: Make DDR detection code work on 32bit system
Define u64 types to be usable on 32bit system because of 64bit address
and size cells and 32bit shifts in the code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:05 +02:00
Michal Simek
aa5b52f56c ARM64: zynqmp: Extend early malloc space to be able to run DM drivers
DM drivers need more malloc space for early DM models allocation.
Use 4k instead of 1k.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:05 +02:00
Michal Simek
885581a56b ARM64: zynqmp: Do not setup DM_ETH/GPIO/MMC by default for all boards
There are mini configurations which need to be fit to OCM that's why
these options shouldn't be enabled by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:05 +02:00
Punnaiah Choudary Kalluri
4521202760 ARM64: zynqmp: Add missing nand node for ep108
Add missing nand node for ep108.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:05 +02:00
Anurag Kumar Vulisha
ac8f6913c4 ARM64: zynqmp: Added OOB timing settings in zynqmp-ep108.dts
This patch adds the sata port phy OOB timing values in the sata
device-tree node.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:05 +02:00
Michal Simek
85d1142eb6 ARM64: zynqmp: Use 64bit size cell format for memory node
Enable option to support more then 4GB memories in single size block.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:05 +02:00
Michal Simek
a84de48e75 ARM64: zynqmp: Fix DWC3 binding with the kernel
Use the same binding as is used in mainline Linux kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:05 +02:00
Michal Simek
786db82bd5 ARM64: zynqmp: Add serdes address space dp driver
For run time serdes adjustment.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00
Michal Simek
c588d15444 ARM64: zynqmp: Align register description
Separate register space and put it on more lines.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00
Hyun Kwon
939cfeafec ARM64: zynqmp: dp: Add default properties to zynqmp.dtsi
Add some default properties to zynqmp.dtsi.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00
Hyun Kwon
695d75a122 ARM64: zynqmp: Use correct addresses in node names
Reflect actual silicon addresses in DT node names.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00
Michal Simek
4e31d27b9c ARM64: zynqmp: Align node address with parent node for dpdma
Use right addresses for channel names

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:04 +02:00