2 Commits

Author	SHA1	Message	Date
Bin Meng	85c714d8dc	riscv: Adjust board_get_usable_ram_top() for 32-bit ... When testing QEMU RISC-V 'virt' machine with a 2 GiB memory configuration, it was discovered gd->ram_top is assigned to value zero in setup_dest_addr(). While gd->ram_top should not be declared as type `unsigned long`, which will be updated in a future patch, the current logic in board_get_usable_ram_top() can be updated to cover both 64-bit and 32-bit RISC-V. Signed-off-by: Bin Meng <bin.meng@windriver.com>	2021-02-03 03:38:41 -07:00
Pragnesh Patel	7c45fc9870	riscv: cpu: fu540: Add support for cpu fu540 ... Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>	2020-06-04 09:44:09 +08:00