At present this is only used on ARM and sandbox, but it is just as
applicable to other architectures. Move the function prototype into the
generic SPL header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Create a few public APIs which rely on secure world ROM/HAL
APIs for their implementation. These are intended to be used
to reserve a portion of the EMIF memory and configure hardware
firewalls around that region to prevent public code from
manipulating or interfering with that memory.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
rockchip platform have a protocol to pass the the kernel reboot mode to bootloader
by some special registers when system reboot. In bootloader we should read it and take action.
We can only setup boot_mode in board_late_init becasue "setenv" need env setuped.
So add CONFIG_BOARD_LATE_INIT to common header and use a entry "rk_board_late_init"
to replace "board_late_init" in board file.
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reference to kernel source code, rockchip pwm has three
type, we are using v2 for rk3288 and rk3399, so let's
update the register to sync with pwm_data_v2 in kernel.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Update PPLL to 676MHz and PMU_PCLK to 48MHz, because:
1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz
can not,
2. We think 48MHz is fast enough for pmu pclk and it is lower power cost
than 99MHz,
3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using
internally for kernel,it suppose not to change the bus clock like pmu_pclk
in kernel, so we want to change it in uboot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
A future patch will implement a clock uclass driver for Tegra. That driver
will call into Tegra's existing clock code to simplify the transition;
this avoids tieing the clock uclass patches into significant refactoring
of the existing custom clock API implementation.
Some of the Tegra clock APIs that manipulate peripheral clocks require
both the peripheral clock ID and parent clock ID to be passed in together.
However, the clock uclass API does not require any such "parent"
parameter, so the clock driver must determine this information itself.
This patch implements new Tegra- specific clock API
clock_get_periph_parent() for this purpose.
The new API is implemented in the core Tegra clock code rather than SoC-
specific clock code. The implementation uses various SoC-/clock-specific
data. That data is only available in SoC-specific clock code.
Consequently, two new internal APIs are added that enable the core clock
code to retrieve this information from the SoC-specific clock code. Due to
the structure of the Tegra clock code, this leads to some unfortunate code
duplication. However, this situation predates this patch.
Ideally, future work will de-duplicate the Tegra clock code, and migrate
it into drivers/clk/tegra. However, such refactoring is kept separate from
this series.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Currently, Tegra peripheral drivers control two aspects of their HW module
clock(s):
1) The clock enable/rate for the peripheral clock itself.
2) The system-level clock tree setup, i.e. the clock parent.
Aspect 1 is reasonable, but aspect 2 is a system-level decision, not
something that an individual peripheral driver should in general know
about or influence. Such system-level knowledge ties the driver to a
specific SoC implementation, even when they use generic APIs for clock
manipulation, since they must have SoC-specific knowledge such as parent
clock IDs. Limited exceptions exist, such as where peripheral HW is
expected to dynamically switch between clock sources at run-time, such
as CPU clock scaling or display clock conflict management in a multi-head
scenario.
This patch enhances the Tegra core code to perform system-level clock
tree setup, in a similar fashion to the Linux kernel Tegra clock driver.
This will allow future patches to simplify peripheral drivers by removing
the clock parent setup logic.
This change is required prior to converting peripheral drivers to use the
standard clock APIs, since:
1) The clock uclass doesn't currently support a set_parent() operation.
Adding one is possible, but not necessary at the moment.
2) The clock APIs retrieve all clock IDs from device tree, and the DT
bindings for almost all peripherals only includes information about the
relevant peripheral clocks, and not any potential parent clocks.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Convert the Tegra MMC driver to DM_MMC. Support for non-DM is removed
to avoid ifdefs in the code. DM_MMC is now enabled for all Tegra builds.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
(swarren, fixed some NULL pointer dereferences, removed extraneous
changes, rebased on various other changes, removed non-DM support etc.)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
struct mmc_host is a Tegra-specific structure, but the name implies it's
something defined by core MMC code, which is confusing. Rename it to
struct tegra_mmc_priv to make its purpose more obvious. The new name is
also more appropriate for a DM driver private data structure, which will
be relevant later in this series.
Nothing needs access to this type except the MMC driver itself. Move the
definition into the driver C file.
Make sure all Tegra MMC functions are named tegra_mmc_*. Even though
they're all static, it's useful to have good naming so that symbol tables
are easy to interpret. A few functions aren't renamed by this patch since
they'll be deleted by a subsequent patch in this series.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
pad_init_mmc() is performing an SoC-specific operation, using registers
within the MMC controller. There's no reason to implement this code
outside the MMC driver, so move it inside the driver.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Instead of using CONFIG_* name space, rename these two macros to
SYS_FSL_* space.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move this config to Kconfig option and clean up existing uses.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Calvin Johnson <calvin.johnson@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move this option to Kconfig and clean up existing uses.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Mingkai Hu <mingkai.hu@nxp.com>
CC: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Unlike Linux, nothing about errno.h is arch-specific in U-Boot.
As you see, all of arch/${ARCH}/include/asm/errno.h is just a
wrapper of <asm-generic/errno.h>. Actually, U-Boot does not
export headers to user-space, so we just have to care about the
consistency in the U-Boot tree.
Now all of include directives for <asm/errno.h> are gone.
Deprecate <asm/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
driver/usb/dwc3/gadget.c need a "sys_proto.h" header file, add a
empty one to make compile success.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a condition to determine the rk3288_sdram_channel size.
This patch fixes read sdram_channel property failed from DT on rk3288
boards, which not enable OF_PLATDATA.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
pmugrf is a module like grf which contain some of the iomux registers
and other registers.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Mode pins can be used as output for reset. Xilinx boards are using
this feature as additional way how to reset USB phys and also others
chips on the boards.
Mode1 is used on all these boards for this feature.
Let SPL toggle reset on this pin by default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ZynqMP provides an option to overwrite bootmode setting which
can change SPL behavior.
For example: boot SPL via JTAG and then SPL loads images from SD.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Linux kernel musb driver expects VBUS to be off while initializing
musb. Having it on results in a repeating string of warnings, followed
by an unusable peripheral. The peripheral is only usable after
physically removing the OTG adapter, letting musb reset its state.
This partially reverts commit c9f8947e66 ("sunxi: usb-phy: Never
power off the usb ports")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
A few boards define this in a header file which is incorrect. It means that
Kconfig options that rely on this cannot be used. Move it.
Signed-off-by: Simon Glass <sjg@chromium.org>
A few boards define this in a header file which is incorrect. It means that
Kconfig options that rely on this cannot be used. Move it.
Note that quite a few boards defined this options but do not appear to
actually use SPL:
BSC9132QDS_NOR_DDRCLK100_SECURE
BSC9132QDS_NOR_DDRCLK133_SECURE
BSC9132QDS_SDCARD_DDRCLK100_SECURE
BSC9132QDS_SDCARD_DDRCLK133_SECURE
BSC9132QDS_SPIFLASH_DDRCLK100_SECURE
BSC9132QDS_SPIFLASH_DDRCLK133_SECURE
C29XPCIE_NOR_SECBOOT
P1010RDB-PA_36BIT_NAND_SECBOOT
P1010RDB-PA_36BIT_SPIFLASH_SECBOOT
P1010RDB-PA_NAND_SECBOOT
P1010RDB-PA_NOR_SECBOOT
P1010RDB-PB_36BIT_NOR_SECBOOT
P1010RDB-PB_36BIT_SPIFLASH_SECBOOT
P1010RDB-PB_NAND_SECBOOT
P1010RDB-PB_NOR_SECBOOT
P3041DS_SECURE_BOOT
P4080DS_SECURE_BOOT
P5020DS_NAND_SECURE_BOOT
P5040DS_SECURE_BOOT
T1023RDB_SECURE_BOOT
T1024QDS_DDR4_SECURE_BOOT
T1024QDS_SECURE_BOOT
T1024RDB_SECURE_BOOT
T1040RDB_SECURE_BOOT
T1042D4RDB_SECURE_BOOT
T1042RDB_SECURE_BOOT
T2080QDS_SECURE_BOOT
T2080RDB_SECURE_BOOT
T4160QDS_SECURE_BOOT
T4240QDS_SECURE_BOOT
ls1021aqds_nor_SECURE_BOOT
ls1021atwr_nor_SECURE_BOOT
ls1043ardb_SECURE_BOOT
For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since
they apparently don't have an SPL, this should not matter.
Signed-off-by: Simon Glass <sjg@chromium.org>
The secure boot header files incorrectly define SPL options only if
CONFIG_SPL_BUILD is defined. This means that the options are only enabled
in an SPL build, and not with a normal 'make xxx_defconfig'. This means
that moveconfig.py cannot work, since it sees the options as disabled even
when they may be manually enabled in an SPL build.
Fix this by changing the order.
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x80300000 by default.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This general MMDC driver adds basic support for Freescale MMDC
(Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8
LS1012A SoC for DDR3L, there will be a update to this driver to
support more flexible configuration if new features (DDR4, multiple
controllers/chip selections, etc) are implimented in future.
Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/
LS1012AFRDM.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds definitions of all the regesters necessary for
system sleep.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The v7_flush_dcache_all function will be called by ls102xa platform system
suspend, it is necessary to make it a public call instead of a local one, but
changing the LENTRY to ENTRY isn't enough, because there is another one using
the same name, so this one gets a psci_ prefix.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Up to now, the function is_serdes_configed() doesn't check if the map
of serdes protocol is initialized before accessing it. The function
is_serdes_configed() will get wrong result when it was called before
the serdes protocol maps initialized. As the first element of the map
isn't used for any device, so use it as the flag to indicate if the
map has been initialized.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As part of Secure Boot Chain of trust, PPA image must be validated
before the image is started.
The code for the same has been added.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
On all TI platforms the ROM defines a "downloaded image" area at or near
the start of SRAM which is followed by a reserved area. As it is at
best bad form and at worst possibly harmful in corner cases to write in
this reserved area, we stop doing that by adding in the define
NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image
area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this.
At current we define the end of scratch space at 0x228 bytes past the
start of scratch space this this gives us a lot of room to grow. As
these scratch uses are non-optional today, all targets are modified to
respect this boundary.
Tested on OMAP4 Pandaboard, OMAP3 Beagle xM
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Paul Kocialkowski <contact@paulk.fr>
Cc: Enric Balletbo i Serra <eballetbo@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Thomas Weber <weber@corscience.de>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: "B, Ravi" <ravibabu@ti.com>
Cc: "Matwey V. Kornilov" <matwey.kornilov@gmail.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: "Kipisz, Steven" <s-kipisz2@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Ladislav Michl <ladis@linux-mips.org>
Remove the device definition from board file, update the driver with
the new compatible property and update config with necessary options.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
