Kever Yang 8389dcbf98 rockchip: rk3399: update PPLL and pmu_pclk frequency ... Update PPLL to 676MHz and PMU_PCLK to 48MHz, because: 1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz can not, 2. We think 48MHz is fast enough for pmu pclk and it is lower power cost than 99MHz, 3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using internally for kernel,it suppose not to change the bus clock like pmu_pclk in kernel, so we want to change it in uboot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>		2016-10-01 18:35:01 -06:00
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asm	rockchip: rk3399: update PPLL and pmu_pclk frequency	2016-10-01 18:35:01 -06:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00