Commit Graph

8515 Commits

Author SHA1 Message Date
Simon Glass
788cd90864 x86: ivybridge: Move lpc_early_init() to probe()
Move this code to the LPC's probe() method so that it will happen
automatically when the LPC is probed before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:19 +08:00
Simon Glass
4acc83d437 x86: ivybridge: Set up the LPC device using driver model
Find the LPC device in arch_cpu_init_dm() as a first step to converting
this code to use driver model. Probing the LPC will probe its parent (the
PCH) automatically, so make sure that probing the PCH does nothing before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:19 +08:00
Simon Glass
0bdce0751b dm: x86: Drop the weak cpu_irq_init() function
There are no callers now. Platforms which need to set up interrupts their
own way can implement an interrupt driver. Drop this function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
0ac8b1f437 dm: x86: queensbay: Add an interrupt driver
Add a driver for interrupts on queensbay and move the code currently in
cpu_irq_init() into its probe() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
117bfc7fbe dm: x86: quark: Add an interrupt driver
Add a driver for interrupts on quark and move the code currently in
cpu_irq_init() into its probe() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
b565d66d2c x86: Use the IRQ device when setting up the mptable
Instead of searching for the device tree node, use the IRQ device which has
a record of it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
d3b884b294 dm: x86: Add a common PIRQ init function
Most x86 interrupt drivers will want to use the standard PIRQ routing and
table setup. Put this code in a common function so it can be used by those
drivers that want it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
12d6929e1f dm: x86: Set up interrupt routing from interrupt_init()
At present interrupt routing is set up from arch_misc_init(). We can do it
a little later instead, in interrupt_init().

This removes the manual pirq_init() call. Where the platform does not have
an interrupt router defined in its device tree, no error is generated. Some
platforms do not have this.

Drop pirq_init() since it is no-longer used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
e76187a355 dm: x86: Create a driver for x86 interrupts
It seems likely that at some point we will want a generic interrupt uclass.
But this is a big undertaking as it involves unifying code across multiple
architectures.

As a first step, create a simple IRQ uclass and a driver for x86. This can
be generalised later as required.

Adjust pirq_init() to probe this driver, which has the effect of creating
routing tables and setting up the interrupt routing. This is a start
towards making interrupts fit better with driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:18 +08:00
Simon Glass
f2b85ab5e6 dm: x86: spi: Convert ICH SPI driver to driver model PCI API
At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.

In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.

While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.

Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.

This patch includes Bin's fix-up patch from here:

   https://patchwork.ozlabs.org/patch/569478/

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:17 +08:00
Simon Glass
ca831f4933 dm: Expand the uclass for Platform Controller Hubs (PCH)
A Platform Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. The chip is typically
found on the first PCI bus and integrates multiple devices.

We have a very simple uclass to support PCHs. Add a few operations, such as
setting up the devices on the PCH and finding the SPI controller base
address. Also move it into drivers/pch/ since we will be adding a few PCH
drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:17 +08:00
Simon Glass
7c1058fadc rockchip: Add support for Raxda Rock 2
This board includes an RK3288 SoC on a SOM. It can be mounted on a
base-board which provides a wide range of peripherals.

So far this is verified to boot to a prompt from a microSD card. The serial
console works as well as HDMI.

Thanks to Tom Cubie for sending me a board.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
cf629bb2ba rockchip: rock2: dts: Make changes for U-Boot
Add the required pre-relocation tags and SDRAM init information for U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
68b08c4077 rockchip: rock2: Bring in device tree files from Linux
Bring in the current device tree files for rock2 from linux/next commit
719d6c1. Hopefully this is the latest one.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
6406f45354 rockchip: dts: Sync up SPDIF node with Linux
This has been added and we have references to it in the rock2 board. Add
this node.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
74336f7daa rockchip: jerry: Enable EDP and HDMI video output
Enable these devices using the VOPL video output device. We explicitly
disable VOPB in the device tree to avoid it taking over. Since this device
has an LCD display this comes up by default. If the display fails for some
reason then it will attempt to use HDMI. It is possible to force it to fail
(and thus fall back to HDMI) by puting 'return -EPERM' at the top of
rk_edp_probe(). For now there is no easy way to select between the two.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
dae594f210 rockchip: spl: Support full-speed CPU in SPL
Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
4f14d135f9 rockchip: jerry: Fix the SDRAM timing
There is a minor error in the SDRAM timing. It does not seem to affect
anything so far. Fix it just in case.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
f23cf909ee rockchip: spl: Drop MMC support code when not needed
When the board does not use MMC SPL this code is a waste of space. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
affd4a9fa0 rockchip: Tidy up the register-access macros
These work reasonable well, but there are a few errors:

- Brackets should be used to avoid unexpected side-effects
- When setting bits, the corresponding upper 16 bits should be set also

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
2460d18c33 rockchip: sdram: Use syscon_get_first_range() where possible
This is a shortcut to obtaining a register address. Use it where possible, to
simplify the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
9368104d2f rockchip: sdram: Tidy up a few comments
Fix spaces in two comments in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
74e53e0e9b rockchip: Add a simple 'clock' command
Add a command that displays the PLLs and their current rate.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
ad443b7290 rockchip: Don't skip low-level init
At present the low-level init is skipped on rockchip. Among other things
this means that the instruction cache is left disabled. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
7b7ad5c31c rockchip: video: Add a video-output driver
Some rockchip SoCs include video output (VOP). Add a driver to support this.
It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and
eDP are supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
5852d539ea rockchip: video: Add a display driver for rockchip eDP
Some Rockchip SoCs support embedded DisplayPort output. Add a display driver
for this so that these displays can be used on supported boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
c253948341 rockchip: video: Add a display driver for rockchip HDMI
Some Rockchip SoCs support HDMI output. Add a display driver for this so
that these displays can be used on supported boards.

Unfortunately this driver is not fully functional. It cannot reliably read
EDID information over HDMI. This seems to be due to the clocks being
incorrect - the I2C bus speed appears to be up to 100x slower than the
clock settings indicate. The root cause may be in the clock logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
009741fbae rockchip: Rename the CRU_MODE_CON fields
These should match the datasheet naming. Adjust them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
0e23fd81a5 pwm: rockchip: Add a PWM driver for Rockchip SoCs
Add a simple driver which implements the standard PWM uclass interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
27a1961d0b rockchip: jerry: Enable the Chrome OS EC
Turn on the EC and enable the keyboard.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
5ddf5d7705 rockchip: clk: Make rkclk_get_clk() SoC-specific
The current method assumes that clocks are numbered from 0 and we can
determine a clock by its number. It is safer to use an ID in the clock's
platform data to avoid the situation where another clock is bound before
the one we expect.

Move the existing code into rk3036 since it still works there. Add a new
implementation for rk3288.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:35 -07:00
Simon Glass
a49dc0a914 rockchip: reset: Use the rk_clr/setreg() interface
Use this function in preference to the macro.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:35 -07:00
Simon Glass
0906995bf3 rockchip: sdram: Use the rk_clr/setreg() interface
Use this function in preference to the macro.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:35 -07:00
Simon Glass
64b7faa7f9 rockchip: clock: Add a function to find a clock by ID
The current approach of using uclass_get_device() is error-prone. Another
clock (for example a fixed-clock) may cause it to break. Add a function that
does a proper search.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:34 -07:00
Simon Glass
f4adc9a504 rockchip: jerry: Disable pmic-int-1 setup to avoid a hang
This hangs when activated (by probing the PMIC). Disable it for now until we
understand the root cause.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:34 -07:00
Simon Glass
79d020ee74 rockchip: Use pwrseq for MMC start-up on jerry
This is defined in the device tree in Linux. Copy over the settings so that
this can be used instead of hard-coding the reset line.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:34 -07:00
Simon Glass
a4275f5e52 rockchip: Convert the PMU IOMUX registers into an array
This is easier to deal with when using generic code since it allows us to
use a register index instead of naming each register.

Adjust it, adding an enum to improve readability.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:34 -07:00
Simon Glass
1e724f8ea8 rockchip: Avoid using MMC code when not booting from MMC
This saves some code space in SPL which is useful on jerry.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:34 -07:00
Jeffy Chen
f7ee071a22 ARM: bootm: Try to use relocated ramdisk
After boot_ramdisk_high(), ramdisk would be relocated to
initrd_start & initrd_end, so use them instead of rd_start & rd_end.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-21 20:03:59 -07:00
Tom Rini
6905f4d3c7 Merge git://git.denx.de/u-boot-dm 2016-01-21 11:49:49 -05:00
Tom Rini
45fe3809b9 Merge branch 'master' of git://git.denx.de/u-boot-i2c; branch 'master' of git://git.denx.de/u-boot-nds32 2016-01-21 09:12:22 -05:00
Jelle van der Waa
9d0826879e sunxi: Add support for the I2C controller which is part of the PRCM
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: Minor cleanups]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

applied with fixing 2 checkpatch warnings:
WARNING: please, no space before tabs

Signed-off-by: Heiko Schocher <hs@denx.de>
2016-01-21 07:30:01 +01:00
rick
b19cc6bf21 nds32: Fix compile error.
Fix compile error with gcc 4.9.3

Signed-off-by: rick <rick@andestech.com>
Cc: Andes <uboot@andestech.com>
2016-01-21 10:41:43 +08:00
Simon Glass
3c97c4fb52 dm: video: test: Add tests for the video uclass
Add tests that check that the video console is working correcty. Also check
that text output produces the expected result. Test coverage includes
character output, wrapping and scrolling.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
2016-01-20 19:10:16 -07:00
Simon Glass
3ade5bc4dc dm: video: sandbox: Convert sandbox to use driver model for video
Now that driver model support is available, convert sandbox over to use it.
We can remove a few of the special hooks that sandbox currently has.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
2016-01-20 19:10:16 -07:00
Bin Meng
665ac00c98 arm: ls1021atwr: Enable driver model lpuart serial driver
Convert ls1021atwr_nor_lpuart to driver model support. As a start,
enable lpuart serial port driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Tested-by: Alison Wang <alison.wang@nxp.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:10:15 -07:00
Bin Meng
8b67761437 arm: ls1021atwr: Split off board device tree
Move /chosen node out of the board device tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:10:14 -07:00
Bin Meng
f833cd6279 arm: ls1021atwr: Convert to driver model and enable serial support
Convert ls1021atwr_nor to driver model support. As a start, enable
ns16550 serial port driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-01-20 19:10:14 -07:00
Mugunthan V N
87a2127f9f arm: dts: dra7-evm: add tick-timer to chosen node
Specify timer2 to be used as tick-timer in chosen node.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-20 19:06:22 -07:00
Mugunthan V N
6c3401ad86 arm: dts: dra72-evm: add tick-timer to chosen node
Specify timer2 to be used as tick-timer in chosen node.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-20 19:06:22 -07:00