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dm: x86: queensbay: Add an interrupt driver

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Add a driver for interrupts on queensbay and move the code currently in
cpu_irq_init() into its probe() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2016-01-19 21:32:31 -07:00 committed by Bin Meng
parent 117bfc7fbe
commit 0ac8b1f437
4 changed files with 67 additions and 39 deletions
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2
arch/x86/cpu/queensbay/Makefile
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@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += fsp_configs.o
obj-y += fsp_configs.o irq.o
obj-y += tnc.o topcliff.o

65
arch/x86/cpu/queensbay/irq.c Normal file
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@ -0,0 +1,65 @@
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
* Copyright (C) 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pci.h>
#include <asm/arch/device.h>
#include <asm/arch/tnc.h>
int queensbay_irq_router_probe(struct udevice *dev)
{
struct tnc_rcba *rcba;
u32 base;
base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
base &= ~MEM_BAR_EN;
rcba = (struct tnc_rcba *)base;
/* Make sure all internal PCI devices are using INTA */
writel(INTA, &rcba->d02ip);
writel(INTA, &rcba->d03ip);
writel(INTA, &rcba->d27ip);
writel(INTA, &rcba->d31ip);
writel(INTA, &rcba->d23ip);
writel(INTA, &rcba->d24ip);
writel(INTA, &rcba->d25ip);
writel(INTA, &rcba->d26ip);
/*
* Route TunnelCreek PCI device interrupt pin to PIRQ
*
* Since PCIe downstream ports received INTx are routed to PIRQ
* A/B/C/D directly and not configurable, we have to route PCIe
* root ports' INTx to PIRQ A/B/C/D as well. For other devices
* on TunneCreek, route them to PIRQ E/F/G/H.
*/
writew(PIRQE, &rcba->d02ir);
writew(PIRQF, &rcba->d03ir);
writew(PIRQG, &rcba->d27ir);
writew(PIRQH, &rcba->d31ir);
writew(PIRQA, &rcba->d23ir);
writew(PIRQB, &rcba->d24ir);
writew(PIRQC, &rcba->d25ir);
writew(PIRQD, &rcba->d26ir);
return irq_router_common_init(dev);
}
static const struct udevice_id queensbay_irq_router_ids[] = {
{ .compatible = "intel,queensbay-irq-router" },
{ }
};
U_BOOT_DRIVER(queensbay_irq_router_drv) = {
.name = "queensbay_intel_irq",
.id = UCLASS_IRQ,
.of_match = queensbay_irq_router_ids,
.probe = queensbay_irq_router_probe,
};

37
arch/x86/cpu/queensbay/tnc.c
View File

@ -69,43 +69,6 @@ int arch_early_init_r(void)
return 0;
}
void cpu_irq_init(void)
{
struct tnc_rcba *rcba;
u32 base;
base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
base &= ~MEM_BAR_EN;
rcba = (struct tnc_rcba *)base;
/* Make sure all internal PCI devices are using INTA */
writel(INTA, &rcba->d02ip);
writel(INTA, &rcba->d03ip);
writel(INTA, &rcba->d27ip);
writel(INTA, &rcba->d31ip);
writel(INTA, &rcba->d23ip);
writel(INTA, &rcba->d24ip);
writel(INTA, &rcba->d25ip);
writel(INTA, &rcba->d26ip);
/*
* Route TunnelCreek PCI device interrupt pin to PIRQ
*
* Since PCIe downstream ports received INTx are routed to PIRQ
* A/B/C/D directly and not configurable, we have to route PCIe
* root ports' INTx to PIRQ A/B/C/D as well. For other devices
* on TunneCreek, route them to PIRQ E/F/G/H.
*/
writew(PIRQE, &rcba->d02ir);
writew(PIRQF, &rcba->d03ir);
writew(PIRQG, &rcba->d27ir);
writew(PIRQH, &rcba->d31ir);
writew(PIRQA, &rcba->d23ir);
writew(PIRQB, &rcba->d24ir);
writew(PIRQC, &rcba->d25ir);
writew(PIRQD, &rcba->d26ir);
}
int arch_misc_init(void)
{
unprotect_spi_flash();

2
arch/x86/dts/crownbay.dts
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@ -164,7 +164,7 @@
compatible = "intel,pch7";
irq-router {
compatible = "intel,irq-router";
compatible = "intel,queensbay-irq-router";
intel,pirq-config = "pci";
intel,pirq-link = <0x60 8>;
intel,pirq-mask = <0xcee0>;