DRA7/AM57xx devices can be operated in many different configurations.
When the SoC is supposed to support a configuration where low power mode
state may involve the SoC completely powered off and DDR is in self
refresh, SoC EMIF controller should not be the master of the reset
signal and an external entity might be in control of things.
The default configuration of Linux on TI evms involve not powering off
the voltage rails (due to various reasons including reliability concerns)
and must not allow DDR reset to be controlled by EMIF. On platforms
where external entity might control the reset signal, this configuration
will be a "dont care".
Fixes: 536d874708 ("ARM: DRA7: Update DDR IO registers")
Tested-by: Keerthy <j-keerthy@ti.com>
Acked-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The get_max_arm_speed() and get_max_dev_speed() used wrong register
fields to get the maximum speeds. This commit fixes the bug.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently on sun6i after a "reset" the prompt returns and the user can
even type stuff until the watchdog triggers and does the actual reset.
This is somewhat unexpected behavior for the "reset" command, this
commit adds an endless loop to wait for the watchdog to trigger so that
we do not return to the prompt.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Vision Systems's Baltos is based on AM335x SoC
from Texas Instruments. This patch adds support
such Industrial PCs in mainline u-boot.
[ balbi@ti.com: updated original patch to current u-boot ]
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after
warm reset, emif needs to be configured to bring it back to a known
state. So configure EMIF during warm reset.
Reported-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Now all the AVR32 boards have been converted into Generic Board.
Select it in Kconfig and clean up defines in header files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
The recent changes for hw leveling on am33xx were not intended for
DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config
value to check against. This lets us pass in the value we would use to
configure, when we have not yet configured the board yet. In other cases
update the call to be as functional as before and check an already
programmed value in.
Tested-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
On AM57xx evm I2C5 is used to detect the LCD board by reading the
EEPROM present on the bus.
Enable i2c5 clocks to help that.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
SMP-enabled Linux kernels read the CBAR register in CP15 to find
the address of the SCU registers. After remapping internal
registers, also update the CBAR so the kernel can find them.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
L2 cache may still be enabled by the BootROM. We need to first disable
it before enabling d-cache support.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Now all manual mode configurations are done as part of
IO delay recalibration sequence, remove the hack done for
CPSW.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
In addition to the regular mux configuration, certain pins of DRA7
require to have "manual mode" also programmed, when predefined
delay characteristics cannot be used for the interface.
struct iodelay_cfg_entry is introduced for populating
manual mode IO timings.
For configuring manual mode, along with the normal pad
configuration do the following steps:
- Select MODESELECT field of each assocaited PAD.
CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux)
- Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL.
And pass the offset of the CFG_XXX register in iodelay_cfg_entry.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
On DRA7, in addition to the regular muxing of pins, an additional
hardware module called IODelay which is also expected to be
configured. This "IODelay" module has it's own register space that is
independent of the control module.
It is advocated strongly in TI's official documentation considering
the existing design of the DRA7 family of processors during mux or
IODelay recalibration, there is a potential for a significant glitch
which may cause functional impairment to certain hardware. It is
hence recommended to do muxing as part of IOdelay recalibration.
IODELAY recalibration sequence:
- Complete AVS voltage change on VDD_CORE_L
- Unlock IODLAY config registers.
- Perform IO delay calibration with predefined values.
- Isolate all the IOs
- Update the delay mechanism for each IO with new calibrated values.
- Configure PAD configuration registers
- De-isolate all the IOs.
- Relock IODELAY config registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
In addition to the regular mux configuration, certain pins of DRA7
require to have "virtual mode" also programmed.
This allows for predefined delay characteristics to be used by the SoC
to meet timing characterstics needed for the interface.
Provide easy to use macro to do the same.
For configuring virtual mode, along with normal pad configuration add
the following two steps:
- Select MODESELECT field of each assocaited PAD.
CTRL_CORE_PAD_XXX[8]:MODESELECT = 1
- DELAYMODE filed should be configured with value given in DATA Manual.
CTRL_CORE_PAD_XXX[7:4]:DELAYMODE =[0-15] (as given in DATA manual).
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Adopting the pinctrl register definitions from Linux kernel
to be consistent.
Old definitions will be removed once all the pinctrl data
is adapted to new definitions.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
do_set_mux32() is redefined in dra7xx and beagle_x15 boards.
IO delay recalibration sequence also needs this.
Making it generic to avoid duplication.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
When DLL_CALIB_INTERVAL is set, an extra delay is added
which is not required and it consumes EMIF bandwidth.
So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
DDRIO_2 and LPDDR2CH1_1 registers are not present
for DRA7. So not configuring these registers for DRA7xx
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
A generic is_dra72x cpu check is useful for grouping
all the revisions under that. This is used in the
subsequent patches.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Updating EMIF registers to enable HW leveling
on DRA72-evm.
Also updating the timing registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
DRA7 EMIF supports Full leveling for DDR3.
Adding support for the Full leveling sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
We plan to enable device tree in SPL by default. Before doing this,
explicitly disable it for all boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
The 4KB padding doesn't seem necessary since we don't normally adjust the
control device tree file within U-Boot. Also drop the memory table space.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is used before jumping to U-Boot, but in that case we don't
always want to disable caches.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Somehow this change was dropped in the various merges. I noticed when I
came to turn off the non-driver-model support for Tegra. We need to make
this change (and deal with any problems) before going further.
Change-Id: Ib9389a0d41008014eb0df0df98c27be65bc79ce6
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
This fixes ethernet no longer working on boards which use a gpio to enable
the phy.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This commit cleanup MAX77686 regulator node by:
- remove the sub-nodes of unconnected regulators
- remove the "regulator-compatible" properties of all regulators
This prevents printing init errors for the regulators,
with duplicated name strings.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
With the rename the MAINTAINER file was not updated. Fix it and the
'Chrombook' typo in Kconfig.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a hook to allows boards to add their own init to board_init().
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is required in order to avoid instability when running from caches
after the kernel starts.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A harmless but confusing warning is displayed when looking up the
DisplayPort PLL. Correct this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Enable the EC and keyboard, using the SPI bus.
The EC driver requires a particular format and a deactivation delay. Also
U-Boot does not support interrupts.
For now, adjust the device tree to comply. At some point we should tidy
this up to support interrupts and make tegra and exynos use the same setup.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for
adding gadget support to usbarmory, but it's a property common the the
entire SoC family - may as well make it available to all MX5 boards
Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too
Signed-off-by: Chris Kuethe <chris.kuethe@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Matthew Starr <mstarr@hedonline.com>
Cc: Andrej Rosano <andrej@inversepath.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Chris Kuethe <chris.kuethe@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
After that change it would be possible to call samsung_get_base_usb3_phy()
function to get proper base address
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Add IOMUX for the pad used as USB pen. This needs to be driven low for
the Iris and Viola boards where it is pulled up high by default. This is
required for the USB host functionality to work on these boards. Use the
board specific weak initialisation function, to drive the pin low which
would be called on "usb start".
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Add device tree files for Freescale Vybrid platform and
Toradex Colibri VF50, VF61 modules.
Device tree files are taken from upstream Kernel.
Removed the stuff which are not used/supported yet in U-Boot.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Inorder to use the pins as GPIO, apart from setting the alt-function,
pinmuxing need to be done, this patch adds pinmux entries of
few GPIOs.
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Add and use a proper dts for the ga10h a33 based tablet, as
submitted upstream.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2 ,
this gives us a proper dtsi file for the A33 rather then abusing
sun8i-a23.dtsi for this.
And this replaces our minimal (dummy) sun7i-a20-mk808c and
sun8i-a33-astar-mid756 dts files with proper ones.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Mele A1000G-quad and the Mele M9 have the same PCB, sofar we've been
using the same defconfig (and dts on the kernel side) for both models.
Unfortunately this does not work for the otg controller, on the M9 this
is routed to a micro-usb connector on the outside, while as on the
A1000G-quad it is connected to an usb to sata bridge.
This commit adds a new defconfig for the Mele-A1000G-quad to allow using
different otg controller settings on the 2 boards.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Before this commit the code for determining the disconnect threshold was
checking for sun4i or sun6i assuming that those where the exception and
that newer SoCs use a disconnect threshold of 2 like sun7i does.
But it turns out that newer SoCs actually use a disconnect threshold of 3
and sun5i and sun7i are the exceptions, so check for those instead.
Here are the settings from the various Allwinner SDK sources:
sun4i-a10: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun5i-a13: USBC_Phy_Write(usbc_no, 0x2a, 2, 2);
sun6i-a31: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun7i-a20: USBC_Phy_Write(usbc_no, 0x2a, 2, 2);
sun8i-a23: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun8i-h3: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun9i-a80: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
Note this commit makes no functional changes for sun4i - sun7i, and
changes the disconnect threshold for sun8i to match what Allwinner uses.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
A conflict between the PMIC and unit test work means that the sandbox test
device tree file is no-longer built. Fix this.
Series-to: u-boot
Series-cc: joe, prz
Change-Id: I6616428e05713e5306f848e7dd0a645dedf0934e
Signed-off-by: Simon Glass <sjg@chromium.org>
These were lost when the PMIC series was applied. Add them back so that the
tests pass again.
Reported-by: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
There are some core test nodes near the beginning of the file which should
be grouped together. But for other nodes, let's sort them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
For some reason 'u-boot -D' does not restore the terminal correctly when
the 'reset' command is used. Call the terminal restore function explicitly
in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Simon Glass <sjg@chromium.org>
Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF
and additional SDRAM is mapped from 0x100000000 and up. There is a
physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses.
Because of this, PCI region 3 should only try to use up to the amount of
SDRAM or 0x80000000, which ever is less.
Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Support QEMU PIRQ routing via device tree on both i440fx and q35
platforms. With this commit, Linux booting on QEMU from U-Boot
has working ATA/SATA, USB and ethernet.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree "u-boot,no-apm-finalize" under /config node if we don't want
to do that.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Although the two qemu-x86 targets (i440fx and q35) share a lot in
common, they still have something that cannot easily handled in one
single device tree). Split to create two dedicated device tree files
and make the i440fx be the default build target.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
As VGA option rom needs to run at C segment, although QEMU PAM emulation
seems to only guard E/F segments, for correctness, move VGA initialization
after PAM decode C/D/E/F segments.
Also since we already tested QEMU targets to differentiate I440FX and Q35
platforms, change to locate the VGA device via hardcoded b.d.f instead of
dynamic search for its vendor id & device id pair.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix
driver does sanity check to see whether legacy ports decode is turned on.
To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
By default the legacy segments C/D/E/F do not decode to system RAM.
Turn on the decode via Programmable Attribute Map (PAM) registers
so that we can write configuration tables in the F segment.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
High mem starts at 4 GiB.
Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
If pirq_routing_table points to NULL, that means U-Boot fails to
generate the table before in create_pirq_routing_table(), so we
test it against NULL before actually writing it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
It turns out that QEMU x86 emulated graphic card has a built-in
option ROM which can be run perfectly with native mode by U-Boot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
CONFIG_FRAMEBUFFER_SET_VESA_MODE and CONFIG_FRAMEBUFFER_VESA_MODE
are not x86-specific, so move them to drivers/video/Kconfig and
make them depend on VIDEO_VESA driver. Some cosmetic fixes are
applied to the Kconfig help text as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Now that we have QEMU support, make it the default vendor in the
'make menuconfig' screen.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This commit introduces the initial U-Boot support for QEMU x86 targets.
U-Boot can boot from coreboot as a payload, or directly without coreboot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig
https://patchwork.ozlabs.org/patch/479745/
In case the DC-DC is already enabled mxs_enable_4p2_dcdc_input() returns
without reenabling brown out detection. So fix this issue by
moving the return before brown out deactivation.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Marek Vasut <marex@denx.de>
This updates r8a7790 QoS to revision 0.973.
This commit can changed from KConfig to fit contents of the QoS.
Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The chip select 1 of the NAND controller is available if you want to
use, although the pins are shared with UART port 2.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
PH1-Pro5 includes a newer version of DDR PHY IP. Some registers
have been added to the reserved areas.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
One disadvantage of commit a26cd04920 (arch: Make board selection
choices optional) is that Kconfig could create such an insane
.config file that no board is selected.
As PH1-Pro4 is the main stream of UniPhier SoC family, rip off the
"optional" again in favor of PH1-Pro4 as the default SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>