The SPL and U-Boot proper may use different initial stack
locations, which are configured via CONFIG_SPL_STACK and
CONFIG_SYS_INIT_SP_ADDR defines. The lowlevel_init.S
code needs to handle this in the same way as crt0.S
Without this fix, setting the U-Boot stack location to some
place, which is not safely accessible by the SPL (such as
the DRAM), causes a very early SPL deadlock.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rather than having a global variable, pass the spl_image as a parameter.
This avoids BSS use, and makes it clearer what the function is actually
doing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add a linker list declaration for this method and remove the explicit
switch() code. Update existing users.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
At present some spl_xxx_load_image() functions take a parameter and some
don't. Of those that do, most take an integer but one takes a string.
Convert this parameter into a struct so that we can pass all functions the
same thing. This will allow us to use a common function signature.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move this option to Kconfig and tidy up existing uses. Also add a function
comment to the header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Instead of using the global spl_image variable, pass the required struct in
as an argument.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Instead of using the global spl_image variable, pass the required struct in
as an argument.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
At present this is only used on ARM and sandbox, but it is just as
applicable to other architectures. Move the function prototype into the
generic SPL header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move DDR3, DDR4 and related config options to Kconfig and clean up
existing uses.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move DDR3, DDR4 and realted options to Kconfig and clean up existing
uses.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move this option to Kconfig and clean up existing uses.
NUM_DDR_CONTROLLERS is also used by PowerPC SoCs.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move this option to Kconfig and clean up existing uses.
This option is also used by PowerPC SoCs.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This
option is used by Freescale Layerscape SoCs.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move these options to Kconfig and create a sub-menu to avoid name
conflict with other architectures.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some config options should not have prompt. They are selected by choosing
target.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
SYSCLK is used as a reference clock for USB. When the USB controller
is used, SYSCLK must meet the additional requirement of 100 MHz.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Pin mux logic has 2 options in priority order, one is through RCW_SRC
and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic
takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT
to control the SPI muxing. But actually those are DSPI controller's
pads instead of QSPI controller's, so this workaround allows RCW
fields SPI_BASE and SPI_EXT to control relevant pads muxing.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
Following commits 217f92b and 1544698, these two config
CPU_V7_HAS_NONSEC and CPU_V7_HAS_VIRT are moved to Kconfig,
for correctly select ARMV7_PSCI.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
The core position is not continuous for some SoCs. For example,
valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some
registers (including boot release register) only count existing
cores. Current implementation of cpu_mask() complies with the
continuous numbering. However, command "cpu status" queries the
spin table with actual core position. Add functions to calculate
core position from core number, to correctly calculate offsets.
Tested on LS2080ARDB and LS1043ARDB.
Signed-off-by: York Sun <york.sun@nxp.com>
The exact SoC revsion number can be recognized from U-Boot log.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and
ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First
stage of u-boot can run faster after that. There is a description
about skip lowlevel init in board/freescale/ls1021atwr/README.
Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
The default values for Port Phy2Cfg register and
Port Phy3Cfg register are better, no need to overwrite them.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This format can be flashed directly at address 0 of
the NAND FLASH, as it contains all necessary headers.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
>From TO1.1, SNVS adds internal pull up control for POR_B,
the register filed is GPBIT[1:0], after system boot up,
it can be set to 2b'01 to disable internal pull up.
It can save about 30uA power in SNVS mode.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
For i.MX6, the mux width is 4, not 3. So enlarge the width.
IOMUX_CONFIG_LPSR is changed from 0x8 to 0x20 to not use bit 3 of mux.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Currently the bmode "usb" uses BOOT_CFG1 to 0x01, -which means
BOOT_CFG1[7:4] is set to b0000. According to Table 8-7 Boot
Device Selection this is NOR/OneNAND and not Reserved.
Use 0x10 which leads to b0001, which is a Reserved boot device.
With that the SoC reliably falls back to the serial loader.
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Troy Kisky <troy.kisky@boundarydevices.com>
Add i.MX6ULL EVK board support:
Add device tree file, which is copied from NXP Linux.
Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR.
The uart iomux settings are still keeped in board file.
Boot Log:
U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800)
CPU: Freescale i.MX6ULL rev1.0 at 396MHz
CPU: Commercial temperature grade (0C to 95C) at 15C
Reset cause: POR
Model: Freescale i.MX6 ULL 14x14 EVK Board
Board: MX6ULL 14x14 EVK
DRAM: 512 MiB
MMC: initialized IMX pinctrl driver
FSL_SDHC: 0, FSL_SDHC: 1
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
=> mmc dev 1
switch to partitions #0, OK
mmc1 is current device
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add pinctrl defines for NXP i.MX 6ULL.
Since i.MX6ULL reuses some definitions of i.MX6UL,
also add i.MX6UL pinctrl defines from linux kernel commit (29b4817d401).
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
not in IOMUXC, so correct the related registers' offset.
Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
them from iomuxc pins.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com>
Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage
is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop
MISC0 bit[6:4]) setting to 2b'110.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Since the mx6ull adds the AIPS3, so enable its initialization.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Update memory map address for mx6ull.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Update Clock settings and CCM register map for i.MX6ULL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Update misc SOC related settings for i.MX6ULL, such as FEC mac address,
cpu speed grading and mmdc channel mask clearing.
Also update s_init to skip pfd reset.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Since MX6ULL select MX6UL, we can not use IS_ENABLED(CONFIG_MX6UL) here,
because this piece code is only for i.MX6UL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Rom already initialized clock at 396M and 132M for arm core and ahb,
so skip setting them again in U-Boot.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
i.MX6ULL is derivative from i.MX6UL, so select MX6UL for MX6ULL.
If need to differenate MX6ULL from MX6UL, use CONFIG_MX6ULL
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add i.MX6ULL major cpu type.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
The CPU detection macro is_mx6dq returns 0 on an i.MX6DQP, so we need to
check for it explicitly in order to correctly initialize the pads when
CONFIG_MX6QDL is defined.
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Like OMAP54xx and AM43xx family SoCs, AM33xx based SoCs have high
security enabled models. Allow AM33xx devices to be built with
HS Device Type Support.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
The option SPL_SPI_SUPPORT is used to enable support in SPL for loading
images from SPI flash, it should not be used to determine the build type
of the SPL image itself. The ability to read images from SPI flash does
not imply the SPL will be booted from SPI flash.
Unconditionally build SPI flash compatible SPL images.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Depending on the boot media, different images are needed
for secure devices. The build generates u-boot*_HS_* files
as appropriate for the different boot modes.
For AM33xx devices additional image types are needed for
various SPL boot modes as the ROM checks for the name of
the boot mode in the file it loads.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
The config option AM33XX is used in several boards and should be
defined as a stand-alone option for this SOC. We break this out
from target boards that use this SoC and common headers then enable
AM33XX on in all the boards that used these targets to eliminate any
functional change with this patch.
This is similar to what has already been done in
9de852642cae ("arm: Kconfig: Add support for AM43xx SoC specific Kconfig")
and is done for the same reasons.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds a secure dram reservation fixup for secure
devices, when a region in the emif has been set aside
for secure world use. The size is defined by the
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE config option.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
After EMIF DRAM is configured, but before it is used,
calls are made on secure devices to reserve any configured
memory region needed by the secure world and then to lock the
EMIF firewall configuration. If any other firewall
configuration needs to be applied, it must happen before the
lock call.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Create a few public APIs which rely on secure world ROM/HAL
APIs for their implementation. These are intended to be used
to reserve a portion of the EMIF memory and configure hardware
firewalls around that region to prevent public code from
manipulating or interfering with that memory.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds start address and size config options for setting aside
a portion of the EMIF memory space for usage by security software
(like a secure OS/TEE). There are two sizes, a total size and a
protected size. The region is divided into protected (secure) and
unprotected (public) regions, that are contiguous and start at the
start address given. If the start address is zero, the intention
is that the region will be automatically placed at the end of the
available external DRAM space.
Signed-off-by: Daniel Allred <d-allred@ti.com>
rockchip platform have a protocol to pass the the kernel reboot mode to bootloader
by some special registers when system reboot. In bootloader we should read it and take action.
We can only setup boot_mode in board_late_init becasue "setenv" need env setuped.
So add CONFIG_BOARD_LATE_INIT to common header and use a entry "rk_board_late_init"
to replace "board_late_init" in board file.
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
The latest rk3288-miniarm board doesn't have eMMC device, so remove it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a regulator-init-microvolt for vdd_center regulator
so that we can get a init value for driver probe.
Not like pmic regulator, the PWM regulator do not have a
known default output value, so we would like to init the
regulator when driver probe.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reference to kernel source code, rockchip pwm has three
type, we are using v2 for rk3288 and rk3399, so let's
update the register to sync with pwm_data_v2 in kernel.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Update PPLL to 676MHz and PMU_PCLK to 48MHz, because:
1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz
can not,
2. We think 48MHz is fast enough for pmu pclk and it is lower power cost
than 99MHz,
3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using
internally for kernel,it suppose not to change the bus clock like pmu_pclk
in kernel, so we want to change it in uboot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Default SPL_MMC_SUPPORT to false when ROCKCHIP_SPL_BACK_TO_BROM is enabled.
Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Sandy Patterson <apatterson@sightlogix.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move back_to_bootrom() call later in SPL init so that the console is
initialized and printouts happen.
Currently when ROCKCHIP_SPL_BACK_TO_BROM is enabled there is no console
output from the SPL init stages.
I wasn't sure exactly where this should happen, so if we are set to do
run spl_board_init, then go back to bootrom there after
preloader_console_init(). Otherwise fall back to old behavior of doing
it in board_init_f.
Signed-off-by: Sandy Patterson <apatterson@sightlogix.com>
Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
The all current Rockchip SoCs supporting 4GB of ram have problems
accessing the memory region 0xfe000000~0xff000000. Actually, some IP
controller can't address to, so let's limit the available range.
This patch fixes a bug which found in miniarm-rk3288-4GB board. The
U-Boot was relocated to 0xfef72000, and .bss variants was also
relocated, such as do_fat_read_at_block. Once eMMC controller transfer
data to do_fat_read_at_block via DMA, DMAC can't access more than
0xfe000000. So that DMAC didn't work sane.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Given that boot monitor image is being generated to a specific target location
depending on the SoC and U-boot relies on addr_mon env variable to be aligned
with boot monitor target location. When ever the target address gets updated in
boot monitor, it is difficult to sync between u-boot and boot monitor and also
there is no way to update user that boot monitor image is updated.
To avoid this problem, boot monitor image is being generated with mkimage
header. Adding support in mon_install command for parsing this header.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Creating multiple entries of "config FOO" often gives us bad
experiences. In this case, we should specify "default X86"
as platforms that want this keyboard by default.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Once we migrate to DM-based drivers, we cannot go back to legacy
ones, i.e. config options like DM_* are not user-configurable.
Make SANDBOX and X86 select DM_KEYBOARD like other platforms do.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy
offset are set to enable the initial setting of Usb Phy for P1010.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Modifies erratum implementation due to the fact that P3041,
P5020, and P5040 are all big endian for the USB PHY registers, but
they were specified little endian.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
On Tegra186, it is necessary to perform an SMC to fully flush all caches;
flushing/cleaning by set/way is not enough. Implement the required hook
to make this happen.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Commit ce02a71c23 "tegra: dts: Sync tegra20 device tree files with
Linux" enabled the ULPI USB port on Ventana, but made no attempt to ensure
that U-Boot code could handle this. In practice, various code is missing,
and various configuration options are not enabled, which causes U-Boot to
hang when attempting to initialize this USB port. This patch enables ULPI
PHY support on Ventana, and adds the required pinmux setup for the port to
operate. Note that Ventana is so similar to Seaboard that this change is
made in the Seaboard board file, which is shared with Ventana.
Seaboard also has the ULPI USB port wired up in hardware, although to an
internal port that often doesn't have anything attached to it. However,
the DT nodes for the USB controller and PHY had different status property
values, so the port was not initialized by U-Boot. Fix this inconsistency,
and enable the ULPI port, just like in the Linux kernel DT. This likewise
requires enabling ULPI support in the Seaboard defconfig.
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Some boards have a different set of USB controllers enabled in DT than
the set referenced by /alias entries. This patch fixes that. For
example, this avoids the following message while booting on Ventana,
which is caused by the fact that the USB0 controller had no alias, and
defaulted to wanting a sequence number of 0, which was later explicitly
requested by the alias for USB controller 2.
USB2: Device 'usb@c5008000': seq 0 is in use by 'usb@c5000000'
This didn't affect USB operation in any way though.
Related, there's no need for the USB controller aliases to have an order
that's different from the HW order, so re-order any aliases to match the
HW ordering. This has the benefit that since USB controller 0 is the only
one that supports device-mode in HW, and U-Boot only supports enabling
device move on controller 0, there's now good synergy in the ordering! For
Tegra20, that's not relevant at present since USB device mode doesn't work
correctly on that SoC, but it will save some head-scratching later.
This patch doesn't fix the colibri_t20 board, even though it has the same
issue, since Marcel already sent a patch for that.
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Harmony and Ventana
USB ULPI PHY reset signals are typically active low. Consequently, they
should be marked as GPIO_ACTIVE_LOW in device tree, and indeed they are in
the Linux kernel DTs, and in DT properties that U-Boot doesn't yet use.
However, in DT properties that U-Boot does use, the value has been set to
0 (== GPIO_ACTIVE_HIGH) to work around a bug in U-Boot.
This change fixes the DT to correctly represent the HW, and fixes the
Tegra USB driver to cope with the fact that dm_gpio_set_value() internally
handles any inversions implied by the DT value GPIO_ACTIVE_LOW.
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Implementations of the standard clock and reset APIs are available on all
Tegra SoCs now, so enable compilation of those uclasses.
Enable the Tegra CAR drivers for all SoCs prior to the BPMP being
available. This provides an implementation of those APIs everywhere.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Make clock_get_periph_rate() return the correct value for UART clocks.
This change needs to be applied before the patches that enable CONFIG_CLK
for Tegra SoCs before Tegra186, since enabling that option causes
ns16550_serial_ofdata_to_platdata() to rely on clk_get_rate() for UART
clocks, and clk_get_rate() eventually calls clock_get_periph_rate().
This change is a rather horrible hack, as explained in the comment added
to the clock driver. I've tried fixing this correctly for all clocks as
described in that comment, but there's too much fallout elsewhere. I
believe the clock driver has a number of bugs which all cancel each-other
out, and unravelling that chain is too complex at present. This change is
the smallest change that fixes clock_get_periph_rate() for UART clocks
while guaranteeing no change in behaviour for any other clock, which
avoids other regressions.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A future patch will implement a clock uclass driver for Tegra. That driver
will call into Tegra's existing clock code to simplify the transition;
this avoids tieing the clock uclass patches into significant refactoring
of the existing custom clock API implementation.
Some of the Tegra clock APIs that manipulate peripheral clocks require
both the peripheral clock ID and parent clock ID to be passed in together.
However, the clock uclass API does not require any such "parent"
parameter, so the clock driver must determine this information itself.
This patch implements new Tegra- specific clock API
clock_get_periph_parent() for this purpose.
The new API is implemented in the core Tegra clock code rather than SoC-
specific clock code. The implementation uses various SoC-/clock-specific
data. That data is only available in SoC-specific clock code.
Consequently, two new internal APIs are added that enable the core clock
code to retrieve this information from the SoC-specific clock code. Due to
the structure of the Tegra clock code, this leads to some unfortunate code
duplication. However, this situation predates this patch.
Ideally, future work will de-duplicate the Tegra clock code, and migrate
it into drivers/clk/tegra. However, such refactoring is kept separate from
this series.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Currently, Tegra peripheral drivers control two aspects of their HW module
clock(s):
1) The clock enable/rate for the peripheral clock itself.
2) The system-level clock tree setup, i.e. the clock parent.
Aspect 1 is reasonable, but aspect 2 is a system-level decision, not
something that an individual peripheral driver should in general know
about or influence. Such system-level knowledge ties the driver to a
specific SoC implementation, even when they use generic APIs for clock
manipulation, since they must have SoC-specific knowledge such as parent
clock IDs. Limited exceptions exist, such as where peripheral HW is
expected to dynamically switch between clock sources at run-time, such
as CPU clock scaling or display clock conflict management in a multi-head
scenario.
This patch enhances the Tegra core code to perform system-level clock
tree setup, in a similar fashion to the Linux kernel Tegra clock driver.
This will allow future patches to simplify peripheral drivers by removing
the clock parent setup logic.
This change is required prior to converting peripheral drivers to use the
standard clock APIs, since:
1) The clock uclass doesn't currently support a set_parent() operation.
Adding one is possible, but not necessary at the moment.
2) The clock APIs retrieve all clock IDs from device tree, and the DT
bindings for almost all peripherals only includes information about the
relevant peripheral clocks, and not any potential parent clocks.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.
Main changes:
* Brought in the correct Tegra210 CAR binding; the old file in U-Boot
appears to be a renamed version of the Tegra124 bindings rather than
the real Tegra210 version.
* Conversion of SPI and UART nodes to standard DMA bindings. U-Boot
doesn't use DMA so isn't affected.
* Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all
information required by U-Boot, so U-Boot is not affected.
* Conversion of many magic numbers to named defines.
* Addition of many nodes not used by U-Boot, including separation of the
Tegra LIC (Legacy IRQ controller) and GIC.
* Node sort order fixes.
Remaining deltas relative to the Linux DT:
* U-Boot has enabled PCIe for Tegra210, but the kernel hasn't yet.
* The GPIO node compatible value in the kernel explicitly includes
Tegra124 values whereas U-Boot does not. I'll send a kernel patch to
correct this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.
Main changes:
* USB phy_type property is aligned with the kernel, so board files are
updated so the final DT content doesn't change. I'm not convinved that
Nyan uses HSIC phy_type. However, I'd rather this change be a no-op,
and any DT bug-fixes be separate.
* Sync misc changes from the kernel: missing DT content, minor compatible
value fixes, typos.
Remaining deltas relative to the Linux DT:
* U-Boot uses #address-cells/#size-cells of 1 whereas the kernel uses 2.
I believe U-Boot's DT parsing currently assumes that these values match
the physical address size, so I didn't synchronize this part of the DT.
* U-Boot uses the original XUSB PHY DT binding, wherease the kernel DT
has moved to a newer version. Thus, XUSB client nodes include properties
names phys and phy-names that do not appear in the kernel, and don't
include pad definitions in the padctl node.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.
Main changes:
* Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use
DMA so isn't affected.
* Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all
information required by U-Boot, so U-Boot is not affected.
* Boards need to define the clk32k_in clock that feeds the Tegra PMC.
* Addition of tegra114-mc.h since tegra114.dtsi now includes it.
* Conversion of many magic numbers to named defines.
* Addition of many nodes not used by U-Boot.
* Node sort order fixes.
Remaining deltas relative to the Linux DT:
* USB node compatible values in U-Boot explicitly list Tegra114 values
whereas the kernel does not. I'll send a kernel patch to correct this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.
Main changes:
* Modification of PCIe memory region addresses. The HW memory layout is
programmable, so this should work fine, and Beaver PCIe was tested
without issue.
* Removal of pcie_xclk from the PCIe node and clock binding header. This
clock doesn't exist and isn't used; only a reset with this ID exists.
* Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use
DMA so isn't affected.
* Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all
information required by U-Boot, so U-Boot is not affected.
* Changed the phy_type value for the second USB port. This required board
DTs to be updated to keep the same configuration.
* Boards need to define the clk32k_in clock that feeds the Tegra PMC.
* Addition of tegra30-mc.h since tegra30.dtsi now includes it.
* Conversion of many magic numbers to named defines.
* Addition of many nodes not used by U-Boot.
* Node sort order fixes.
Remaining deltas relative to the Linux DT:
* None.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This brings in a few minor fixes since the last sync. The largest change
is the removal of the definition for TEGRA20_CLK_PCIE_XCLK. This clock
doesn't actually exist.
Remaining deltas:
* Addition of u-boot,dm-pre-reloc property to a couple of nodes.
* Addition of the NAND controller, which Linux doesn't yet support.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Apparently the unit address in a DT node name is now supposed to be a
single integer value, rather than a comma-separated list of individual
cell values. Fix the U-Boot DTs to comply with this naming convention.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Convert the Tegra MMC driver to DM_MMC. Support for non-DM is removed
to avoid ifdefs in the code. DM_MMC is now enabled for all Tegra builds.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
(swarren, fixed some NULL pointer dereferences, removed extraneous
changes, rebased on various other changes, removed non-DM support etc.)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Most other pin mux is configured in this function. This removes the
need to do it in an MMC-specific initialization function, which is good
since that function is going away later in this series.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
struct mmc_host is a Tegra-specific structure, but the name implies it's
something defined by core MMC code, which is confusing. Rename it to
struct tegra_mmc_priv to make its purpose more obvious. The new name is
also more appropriate for a DM driver private data structure, which will
be relevant later in this series.
Nothing needs access to this type except the MMC driver itself. Move the
definition into the driver C file.
Make sure all Tegra MMC functions are named tegra_mmc_*. Even though
they're all static, it's useful to have good naming so that symbol tables
are easy to interpret. A few functions aren't renamed by this patch since
they'll be deleted by a subsequent patch in this series.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
pad_init_mmc() is performing an SoC-specific operation, using registers
within the MMC controller. There's no reason to implement this code
outside the MMC driver, so move it inside the driver.
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
