Linker script is not able find start.o binary. So add its absolute path in
u-boot-spl.lds. This change is similar to u-boot-nand.lds
common/Makefile: Avoid compiling unnecssary files
fsl_ifc_spl.c : It is is responsible for reading u-boot binary from
NAND flash and copying into DDR. It also transfer control from NAND SPL
to u-boot image present in DDR.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or
no NOR boot, do not compile its workaround.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
To avoid sign extension problem, use explicit casting to cast
the SDRAM size to type phys_size_t, or else, if the SDRAM size
is 2G(0x80000000), it will be extended to 0xffffffff80000000
when phys_size_t is type 'unsigned long long'.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Accidentally applied an earlier version of the patch, which set
the compatible to "fsl,qoriq-clockgen-2", lacking the final
".0".
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
move uart soft reset code to common place and call
this function from board code, instead of copy and paste
this code for every board.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Tom Rini <trini@ti.com>
[trini: Fix igep0033 build, remove 'regval' on pcm051]
Signed-off-by: Tom Rini <trini@ti.com>
upcoming support for siemens boards switches mpu pll clk in board
code. So make this configurable.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
move rtc32k_enable() to common place so all am33xx boards can use it.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Small conflict over DRA7XX updates and adding SRAM_SCRATCH_SPACE_ADDR
Conflicts:
arch/arm/include/asm/arch-omap5/omap.h
Signed-off-by: Tom Rini <trini@ti.com>
This patch does the folowing
1. change the data types for unsigned int variable to unsigned
2. change the tmu_base type to struct exynos5_tmu_reg *
3. Add timer functionality for get_cur_temp()
4. error handling in the get_tmu_fdt_values()
5. Add check for curr_temp reading
6. some cosmotic changes.
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch initialises the local variable 'shift' to zero.
The uninitialised local variable 'shift' had garbage value and was
resulting in unwnated results in the functions exynos5_get_mmc_clk()
and exynos4_get_mmc_clk().
Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds FDT support for DWMMC, by reading the DWMMC node data
from the device tree and initialising DWMMC channels as per data
obtained from the node.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds DWMMC device node data for exynos5.
This patch also adds binding file for DWMMC device node.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
PXA270 CPU has turbo mode. The mode is 2.5 times faster than the
default run mode. Activating the mode early significantly speeds
up boot process.
Signed-off-by: Sergey Yanovich <ynvich@gmail.com>
C99's strict aliasing rules are insane to use in low-level code such as a
bootloader, but as Wolfgang has rejected -fno-strict-aliasing in the
past, add a union so that 16-bit accesses can be performed.
Compile-tested only.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Move pinmux configurations for the DA830 SoCs from board file
to the arch tree so that it can be used for all da830 based devices.
Also, avoids duplicate pinmuxing in case of NAND.
Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
auxclk0 and auxclk1 are utilized on some OMAP5 boards.
Define the infrastructure needed for accessing them
without using magic numbers.
Also remove unrelated TPS62361 defines from clocks.h
Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
The omap2420H4 was the only mainline omap24xx board. Prior to being
fixed by Jon Hunter in time for v2013.04 it had been functionally broken
for a very long time. Remove this board as there's not been interest in
it in U-Boot for quite a long time.
Signed-off-by: Tom Rini <trini@ti.com>
DRA7 EVM board has the below configuration. Adding the
settings for the same here.
2Gb_1_35V_DDR3L part * 2 on EMIF1
2Gb_1_35V_DDR3L part * 4 on EMIF2
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
NON SECURE SRAM is 512KB in DRA7xx devices.
So fixing it here.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The sys_clk on the dra evm board is 20MHZ.
Changing the configuration for the same.
And also moving V_SCLK, V_OSCK defines to
arch/clock.h for OMAP4+ boards.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Slew rate compensation cells are not present for DRA7xx
Soc's. So return from function srcomp_enable() if soc is not
OMAP54xx.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
DRA752 now uses AVS Class 0 voltages which are voltages in efuse.
This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.
This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
In DRA7xx Soc's voltage scaling is done using GPI2C.
So i2c_init should happen before scaling. I2C driver
uses __udelay which needs timer to be initialized.
So moving timer_init just before voltage scaling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
TPS659038 is the power IC used in DRA7XX boards.
Adding support for this and also adding pmic data
for DRA7XX boards.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The registers that are used for device identification
are changed from OMAP5 to DRA7xx.
Using the correct registers for DRA7xx.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Voltage scaling can be done in two ways:
-> Using SR I2C
-> Using GP I2C
In order to support both, have a function pointer in pmic_data
so that we can call as per our requirement.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
SGX clocks should be enabled only for OMAP5 ES1.0.
So this can be removed.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The newly introduced function setup_warmreset_time(), called
from within prcm_init(), tries to write to the prm_rsttime
OMAP5 register. The struct member holding this register's
address is however initialized for OMAP5 ES2.0 only. On ES1.0
devices this uninitialized value causes a second (warm) reset
at startup.
Add .prm_rsttime address init to the ES1.0 struct.
Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
Acked-by: Tom Rini <trini@ti.com>
Patch adds a call of abb_setup() function, and proper registers
definitions needed for ABB setup sequence. ABB is initialized
for MPU voltage domain.
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Adaptive Body Biasing (ABB) modulates transistor bias voltages
dynamically in order to optimize switching speed versus leakage.
Adaptive Body-Bias ldos are present for some voltage domains
starting with OMAP3630. There are three modes of operation:
* Bypass - the default, it just follows the vdd voltage
* Foward Body-Bias - applies voltage bias to increase transistor
performance at the cost of power. Used to operate safely at high
OPPs.
* Reverse Body-Bias - applies voltage bias to decrease leakage and
save power. Used to save power at lower OPPs.
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
This fixes several warnings like
In file included from ./u-boot/include/linux/mtd/mtd.h:13:0,
from env_onenand.c:37:
./u-boot/build/vct_platinumavc_onenand_small/include2/asm/errno.h:52:0: warning: "ENOMSG" redefined [enabled by default]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The purpose of the __raw* IO accessors is to provide
IO access in native-endian order. However in the current
MIPS implementation, the 16 and 32 bit variants of the
__raw accessors are swapping the values on big-endian
systems if the CONFIG_SWAP_IO_SPACE option is enabled.
The patch changes the IO accessor macros to fix this
broken behaviour.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
The non-SPL build of U-Boot on Tegra only runs on a single CPU, and
hence there is no need to enable the SCU when running U-Boot. If an
SMP OS is booted, and it needs the SCU enabled, it will enable the SCU
itself. U-Boot doing so is redundant.
The one exception is Tegra20, where an enabled SCU is required for some
aspects of PCIe to work correctly.
Some Tegra SoCs contain CPUs without a software-controlled SCU. In this
case, attempting to turn it on actively causes problems. This is the case
for Tegra114. For example, when running Linux, the first (or at least
some very early) user-space process will trigger the following kernel
message:
Unhandled fault: imprecise external abort (0x406) at 0x00000000
This is typically accompanied by that process receving a fatal signal,
and exiting. Since this process is usually pid 1, this causes total
system boot failure.
Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, fleshed out description, ported to upstream chipid APIs]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The location of valid scratch space is dependent on SoC, so move that
there. On OMAP4+ we continue to use SRAM_SCRATCH_SPACE_ADDR. On
am33xx/ti814x we want to use what the ROM defines as "public stack"
which is the area after our defined download image space. Correct the
comment about and location of CONFIG_SPL_TEXT_BASE.
Signed-off-by: Tom Rini <trini@ti.com>
We need to call the save_omap_boot_params function on am33xx/ti81xx and
other newer TI SoCs, so move the function to boot-common. Only OMAP4+
has the omap_hw_init_context function so add ifdefs to not call it on
am33xx/ti81xx. Call save_omap_boot_params from s_init on am33xx/ti81xx
boards.
Reviewed-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Prior to Sricharan's cleanup of the boot parameter saving code, we
did not make use of NON_SECURE_SRAM_START on am33xx, so it wasn't a
problem that the address was pointing to the middle of our running SPL.
Correct to point to the base location of the download image area.
Increase CONFIG_SPL_TEXT_BASE to account for this scratch area being
used. As part of correcting these tests, make use of the fact that
we've always been placing our stack outside of the download image area
(which is fine, once the downloaded image is run, ROM is gone) so
correct the max size test to be the ROM defined top of the download area
to where we link/load at.
Signed-off-by: Tom Rini <trini@ti.com>
---
Changes in v2:
- Fix typo noted by Peter Korsgaard
This requires that cpu_is_exynos4/5 should be made available before tzpc_init.
Hence this patch also makes necessary changes to have cpu_info in spl and
invokes arch_cpu_init before tzpc_init in low_level_init.S for smdk5250.
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
tzpc_init is common for all exynos5 boards, hence move it to
armv7/exynos so that all other boards can use it.
Also update the smdk5250 Makefile and config file.
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The vectoring table has to be placed at 0x0, but U-Boot on MX23/MX28
starts from RAM, so the vectoring table at 0x0 is not present. Craft
code that will be placed at 0x0 and will redirect interrupt vectoring
to proper location of the U-Boot in RAM.
Signed-off-by: Marek Vasut <marex@denx.de>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
This patch adds generic codes to support Freescale's Vybrid VF610 CPU.
It aligns Vybrid VF610 platform with i.MX platform. As there are
some differences between VF610 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/vf610 directory.
Signed-off-by: Alison Wang <b18965@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This patch adds the IOMUX support for Vybrid VF610 platform.
There is a little difference for IOMUXC module between VF610 and i.MX
platform, the muxmode and pad configuration share one 32bit register on
VF610, but they are two independent registers on I.MX platform. A
CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.
Signed-off-by: Alison Wang <b18965@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Replace all relocate_code routines from ARM start.S files
with a single instance in file arch/arm/lib/relocate.S.
For PXA, this requires moving the dcache unlocking code
from within relocate_code into c_runtime_cpu_setup.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
Then we can get rid of the #ifdef CONFIG_TEGRA guard in cpu_init_crit.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
cpu_init_crit() can be skipped, but the code is still enabled requiring a
platform to supply lowlevel_init().
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Make U-Boot aware of the Tegra20 SKU 7, and treat it identically
to any other Tegra20.
My Whistler board has a SoC with this SKU.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Make U-Boot aware of the Tegra114 SKU 1, and treat it identically
to any other Tegra114.
This value is used on (at least some) Dalmore boards with a production
rather than engineering chip. Such boards are in the hands of some
partners who want to use upstream U-Boot.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
When adjusting peripheral clocks always use find_best_divider()
instead of clk_get_divider() even when a secondary divider is not
available. In the case where is requested clock is too slow to be
derived from the parent clock this allows a best effort to get close
to the requested clock.
This comes up for commands like "sf" where the user can pass a clock
speed on the command line or "sspi" where the clock is hardcoded to
1MHz, but the Tegra114 SPI controller can't go that low.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
dcbi instruction has been used to clear D-cache lock. However, the cache
lock is persistent for e6500 core. Use dcblc to clear the lock explicitly.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Boot ROM code creates TLB entries for 3.5G space before entering
the u-boot. Earlier we were deleting these entries after early
initialization of CPU. In recent past, code has been added
to invalidate all these entries before relocation of u-boot code.
So this code to delete TLB entries after CPU initialization
is no longer required.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Acked-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify
the defines.
- Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere.
- defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G.
Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Allow DDR clock runs faster than SPD specifes. This may cause memory
failure, but the user should know what is going to happen when using
higher than expected DDR clock.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
To align with chassis generation 2 spec, all cores are numbered in sequence.
The cores may reside across multiple clusters. Each cluster has zero to four
cores. The first available core is numbered as core 0. The second available
core is numbered as core 1 and so on.
Core clocks are generated by each clusters. To identify the cluster of each
core, topology registers are examined.
Cluster clock registers are reorganized to be easily indexed.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
T1040 and variants have e5500 cores and are compliant to QorIQ Chassis
Generation 2. The major difference between T1040 and its variants is the
number of cores and the number of L2 switch ports.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify
the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
"cpu <num> status" should check if core is disabled before printing
the spin table location.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
While other architectures have enabled these gcc / ld options for some
time on U-Boot itself, ARM has only been doing this on SPL. Enable this
on full U-Boot as well now.
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@ti.com>
According to the latest exynos5 user manual, the equation for
calculating PLL output was changed to
FOUT= MDIV x FIN/(PDIV x 2^SDIV)
earlier it was
FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
So updating the clock code accordingly.
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add sama5d3xek support with following feature
- boot from NAND flash, PMECC support, 4bit ECC @ 512 bytes sector
- boot from SPI flash support
- boot from SD card support
- LCD support
- EMAC support
- USB OHCI support
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The Freescale MPC8220 Power Architecture processors have long reached
EOL; Freescale does not even list these any more on their web site.
Remove the code to avoid wasting maitaining efforts on dead stuff.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
This gives boards flexibility to assign other than default addresses to each
DDR controller. For example, DDR controler 2 can have 0 as the base and DDR
controller 1 has higher memory.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The workaround has been updated to use a slightly different magic number.
Change from 0x00003000 to 0x30003000.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY
initialization can be reused in kernel without “usb start” command.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Removed unused declare serdes_get_prtcl() which was no longer needed.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address settings.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not
be initialized, and QMAN will have a wrong frequency display.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Protocols are constants. Fix arrays with const prefix.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The PIR parsing algorithm we used is not only for E6500. It applies to all
SoCs with chassis 2.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Use decimal and hexadecimal for protocol numbers. It helps to match with
SoC user manual.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
T4240 internal UTMI phy is different comparing to previous UTMI PHY
in P3041.
This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for
T4240.
The phy timing is very sensitive and moving the phy enable code to
cpu_init.c will not work.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Missing nodes of crypto, pme, etc in device tree is not a fatal error.
Setting up the qman portal should skip the missing node and continue
to finish the rest.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Should check if interleaving is enabled before using interleaving mode.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Lane H on SerDes4 should be SATA2 instead of SATA1
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The L1 D-cache on e6500 is write-through. This means that it's not
considered a good idea to have the L1 up and running if the L2 is
disabled. We don't actually *use* the L1 until after the L2 is
brought up on e6500, so go ahead and move the L1 enablement after
that code is done.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse
status register.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Makes it a bit easier to see if we've properly set them. While
we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually
use those definitions.
Signed-off-by: Andy Fleming <afleming@freescale.com>
The bit positions for FMAN1 freq in RCW is different for B4860.
Also addded a case when FMAN1 frewuency is equal to systembus.
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Sparc only really sets up the ramdisk, but we should still use
image_setup_linux() so that setup is common across all architectures
that use the FDT.
Cover-letter
Introduce a common image_setup_linux() function
This series continues the work to tidy up the image code. Each
architecture has its own code for setting up ready for booting linux.
An attempt is made here to unify these in a single image_setup_linux()
function.
The part of the image code that deals with FDT is split into image-fdt.c
and a few tweaks are added to make FIT images more viable in SPL.
END
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than having similar code in m68k, use image_setup_linux() which
should be common across all architectures that use the FDT.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than having similar code in powerpc, use image_setup_linux() which
should be common across all architectures that use the FDT.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use the common FDT setup function that is now available in image. Move
the FDT-specific code to a new bootm-fdt.c and remove unused headers
from bootm.c.
Signed-off-by: Simon Glass <sjg@chromium.org>
With fewer #ifdefs the code is more readable and more of the code is
compiled for all boards. Add defines in the header file to control
what features are enabled, and then use if() instead of #ifdef.
Signed-off-by: Simon Glass <sjg@chromium.org>
Coreboot provides a lot of useful timing information. Provide a facility
to add this to bootstage on start-up.
Signed-off-by: Simon Glass <sjg@chromium.org>
While we don't want PCAT timers for timing, we want timer 2 so that we can
still make a beep. Re-purpose the PCAT driver for this, and enable it in
coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is no longer used since we prefer the more accurate TSC timer, so
remove the dead code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
Tidy up some old broken and unneeded implementations. These are not used
by coreboot or anything else now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Michael Spang <spang@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
This timer runs at a rate that can be calculated, well over 100MHz. It is
ideal for accurate timing and does not need interrupt servicing.
Tidy up some old broken and unneeded implementations at the same time.
To provide a consistent view of boot time, we use the same time
base as coreboot. Use the base timestamp supplied by coreboot
as U-Boot's base time.
Signed-off-by: Simon Glass <sjg@chromium.org>base
Signed-off-by: Simon Glass <sjg@chromium.org>
The 'Starting linux' message appears twice in the code, but both call
through the same place. Unify these and add calls to bootstage to
mark the occasion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Michael Spang <spang@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
panic_puts() can be called in early boot to display a message. It might
help with early debugging.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
Several files use the global_data pointer without declaring it. This works
because the declaration is currently a NOP. But still it is better to
fix this so that x86 lines up with other archs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since we use CONFIG_SYS_GENERIC_BOARD on x86, we don't need this anymore.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
Since we don't have real-mode code now, we can remove this chunk of the link
script.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
Graeme Russ pointed out that this code is no longer used. Remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
Commit 1865286466 (Introduce generic link
section.h symbol files) changed the __bss_end symbol type from char[] to
ulong. This led to wrong relocation parameters which ended up in a not working
u-boot. Unfortunately this is not clear to see cause due to RAM aliasing we
may get a 'half-working' u-boot then.
Fix this by dereferencing the __bss_end symbol where needed.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The gpio spec for bf54x and bf60x differ a lot from the old gpio driver for bf5xx.
A lot of machine macros are used to accomodate both code in one gpio driver.
This patch split the old gpio driver and move new gpio2 support to the generic
gpio driver folder.
- To enable gpio2 driver, macro CONFIG_ADI_GPIO2 should be defined in the board's
config header file.
- The gpio2 driver supports bf54x, bf60x and future ADI processors, while the
older gpio driver supports bf50x, bf51x, bf52x, bf53x and bf561.
- All blackfin specific gpio function names are replaced by the generic gpio APIs.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
- Add comments for watchdog event initialization.
- Make sure the writting operation to MMRs are finished.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
- Move blackfin serial driver to the generic driver folder.
- Move blackfin serial headers to blackfin arch head folder.
- Update the include path to blackfin serial header in start up code.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Remove blackfin specific implementation of the generic serial API when
early print macro is defined.
In BFIN_BOOT_BYPASS mode, don't call generic serial_puts, because
early print in bypass mode is running before code binary is relocated
to the link address.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Add softswitch_output command for bf609-ezkit to enable softswitches.
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
The early serial should not be configured again in initcode() for BYPASS
boot mode and in start() for the other LDR boot modes.
In BYPASS boot mode, the start up code is located in Nor flash address other
than the DRAM address defined in link script. The code embedded string can't
be addressed by its compile time symbol. Calculate it according to the flash
offset.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Calculate the early uart clock from the system clock registers set by
the bootrom other than the predefine uboot clock macros.
Split the early baudrate setting function and the normal baudrate
setting one.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Define core 1 L1 code sram start address.
Add function to enable core 1 for BF609 and BF561.
Add config macro to allow customer to run core 1 in uboot init code on core 0.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Newer gcc versions will sometimes use a Preg when "r" constraints, but
that'll fail if we use an Ireg in the assignment. So force the code
to always use a Dreg.
This also fixes early boot crashes for older Blackfin parts when compiled
with gcc-4.5. This version ends up selecting the same register for the
input and output variables which corrupts the output assignment triggering
an exception.
P2 = 0xffe02008; /* EVT2 */
R0 = RETS;
CALL 1f;
RTN;
1: P2 = RETS; <-- BAD
RETS = R0;
[P2] = P2; <-- BAD
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Add support for following features:
- nand boot, with PMECC 2bit ECC for 512 bytes sector
- SPI flash boot
- SD card boot
- LCD support
Signed-off-by: Josh Wu <josh.wu@atmel.com>
[fix -Wimplicit-function-declaration for at91_lcd_hw_init()]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Since at91sam9n12 is a subset of at91sam9x5, so put all at91sam9n12
definitions in at91sam9x5 head file.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The boot parameters passed from SPL to UBOOT
must be saved as a part of uboot's gd data
as early as possible, before we will inadvertently
overwrite it. So adding a arch_cpu_init for the required
Socs to save it.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
[trini: Add igep0033 hunk]
Signed-off-by: Tom Rini <trini@ti.com>
The boot parameters are read from individual variables
assigned for each of them. This been corrected and now
they are stored as a part of the global data 'gd'
structure. So read them from 'gd' instead.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
[trini: Add igep0033 hunk]
Signed-off-by: Tom Rini <trini@ti.com>
Currently save_boot_params saves the boot parameters passed
from romcode. But this is not stored in a writable location
consistently. So the current code would not work for a
'XIP' boot. Change this by saving the boot parameters in
'gd' which is always writable. Also add a 'C' function
instead of an assembly code that is more readable.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
These defines are same across OMAP4/5. So move them to
omap_common.h. This is required for the patches that
follow.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
omap_boot_parameters is same and defined for each
soc. So move this to a common place to reuse it
across socs.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
The arm_freq and ddr_freq variables are unused, so remove. Fixup
whitespace slightly while in here.
Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Tom Rini <trini@ti.com>
these variables are curently defined in several config files but the
driver doesn't use them and defaults to hardcoded values in
nand_defs.h
It's interesting to be able to change this hardcoded valude when the
hardware is not using the default adress signals to drive ALE and CLE
and two configuration defines already exist for this purpose so use
them.
Signed-off-by: Eric Bénard <eric@eukrea.com>
this is needed to bring UART0 out of reset but this function
currently only exists for dm644x/355/365/646x when da850 (at
least am1808 also need it).
Signed-off-by: Eric Bénard <eric@eukrea.com>
Warm reset on OMAP5 freezes when USB cable is connected.
Fix requires PRM_RSTTIME.RSTTIME1 to be programmed
with the time for which reset should be held low for the
voltages and the oscillator to reach stable state.
There are 3 parameters to be considered for calculating
the time, which are mostly board and PMIC dependent.
-1- Time taken by the Oscillator to shut + restart
-2- PMIC OTP times
-3- Voltage rail ramp times, which inturn depends on the
PMIC slew rate and value of the voltage ramp needed.
In order to keep the code in u-boot simple, have a way
for boards to specify a pre computed time directly using
the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC'
option. If boards fail to specify the time, use a default
as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead.
Using the default value translates into some ~22ms and should work in
all cases.
However in order to avoid this large delay hiding other bugs,
its recommended that all boards look at their respective data
sheets and specify a pre computed and optimal value using
'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC'
In order to help future board additions to compute this
config option value, add a README at doc/README.omap-reset-time
which explains how to compute the value. Also update the toplevel
README with the additional option and pointers to
doc/README.omap-reset-time.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[rnayak@ti.com: Updated changelog and added the README]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
USB TLL clocks do not support 'explicit_en', only 'hw_auto'
control (R. Sricharan). cm_l3init_hsusbtll_clkctrl has to be
moved to the clk_modules_hw_auto_essential[] array in order
to make the clock work.
This fix is needed (but not sufficient) for USB EHCI operation
in U-Boot.
Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
EMIF supports a global warm reset mode, during which the
EMIF keeps the SDRAM content. But if leveling is enabled
at the time of warm reset for DDR3, the following steps
needs to be done after warm reset:
1) Keep EMIF in self refresh mode.
2) Reset PHY to bring back the PHY to a known state.
3) Start Levelling procedure.
Doing the same.
And also enabling DLL lock and code output after warm reset.
Tested on OMAP5432 ES2.0
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
In order to be able to select one of these buses however, I2C_BUS_MAX
has to be set to 5; do this here.
Please note that for working bus selection, a fix to the i2c driver
is required as well (subject of a separate patch).
Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
The I2C4 and I2C5 base addresses were however not defined; do this
here.
Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
