Commit Graph

34336 Commits

Author SHA1 Message Date
Peng Fan
53cc647dc6 imx: mx7dsabresd: Add QSPI support
Support qspi flashes for mx7dsabresd
1. introduce pin mux settings
2. enable qspi clock
3. introduce related macro definitions

Default QSPI is not enabled, since we need hardware rework to use QSPI,
see SPF-28590, page 9:
"
QSPI signals are muxed with EPDC_D[7:0]
When using QSPI: de-populate R388-R391, R396-R399
populate R392-R395, R299, R300
"

After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi
flashes can be deteced and read/erase/write. Log info:
"
=> sf probe
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB
=> sf read 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
=> sf erase 0 0x4000000
SF: 67108864 bytes @ 0x0 Erased: OK
=> sf write 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Written: OK
"

Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-12-11 22:12:23 +05:30
Jagan Teki
cd337da21e spi: ti_qspi: Fix SPI_3WIRE checking using mode
SPI_3WIRE is spi mode not spi flags, so this patch fixed
the spi-3wire checking throgh mode instead of flags.

Cc: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:23 +05:30
Jagan Teki
379b49d82e spi: Get spi-3wire from dts
spi-3wire is used when SI/SO signals shared so get
the same from dts node and assign to mode on slave
plat->mode.

Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-12-11 22:12:23 +05:30
Bin Meng
789fa275b3 x86: Remove HAVE_ACPI_RESUME
These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:56 +08:00
Bin Meng
d475d59020 x86: Remove CPU_INTEL_SOCKET_RPGA989
This Kconfig option name indicates it has something to do with cpu
socket, however it is actually not the case. Remove it and move
options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:54 +08:00
Bin Meng
efe2d80cca x86: Clean up ivybridge/chrome Kconfig options
There are some options which are never used, and also some options
which are selected by others but have never been a Kconfg option.
Clean these up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:52 +08:00
Bin Meng
9bf76c21e0 x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE
NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:50 +08:00
Bin Meng
2317cf0970 common: Remove timer_init() call for x86
With driver model timer support, there should not be an explict
call to timer_init(). Remove this call for x86.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:49 +08:00
Bin Meng
4932443d26 x86: Move i8254_init() to x86_cpu_init_f()
Right now i8254_init() is called from timer_init() in the tsc timer
driver. But actually i8254 and tsc are completely different things.
Since tsc timer has been converted to driver model, we should find
a new place that is appropriate for U-Boot to call i8254_init(),
which is now x86_cpu_init_f().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:44 +08:00
Bin Meng
c5c5c201fe x86: Fix PCI UART compatible string for crownbay and galileo
With recent ns16550 driver changes, we only changed the legacy UART
(at I/O port 0x3f8) compatible string, but forgot to change the PCI
UART compatible string. Now fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-09 17:44:41 +08:00
Bin Meng
a0ae380b3c fdt: Change OF_BAD_ADDR to FDT_ADDR_T_NONE
Currently OF_BAD_ADDR is always -1ULL. When using OF_BAD_ADDR as the
return value of dev_get_addr(), it creates potential size mismatch
as dev_get_addr() uses FDT_ADDR_T_NONE as the return value which can
be either -1U or -1ULL depending on CONFIG_PHYS_64BIT. Now we change
OF_BAD_ADDR to FDT_ADDR_T_NONE to avoid such case.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-12-09 17:44:36 +08:00
Alexey Brodkin
8555dd88cd axs10x: add support of generic EHCI USB 2.0 controller
This commit adds support of USB 2.0 storage media on AXS10x boards.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2015-12-08 17:29:56 +03:00
Tom Rini
8356431bf8 Prepare v2016.01-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-12-07 14:23:45 -05:00
Marek Vasut
3463314125 mkimage: Fix warning from fix for generating multi and script images again
Seems 6ae6e160 broke creating images in certain cases, there
are two problems with that patch.

First is that the expression "!x == 4 || !x == 6" is ambiguous.  The
intention here was "!(x == 4) || !(x == 6)" based on reading further in
the file, where this was borrowed from.  This however is interpreted by
gcc as "(!x) == 4 || (!x) == 6" and always false.  gcc-5.x will warn
about this case.

The second problem is that we do not want to test for the case of "(NOT x
is 4) OR (NOT x is 6)" but instead "(x is not equal to 4) AND (x is not
equal to 6)".  This is because in those two cases we already execute the
code question in another part of the file.  Rewrite the expression and
add parenthesis for clarity.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Philippe De Swert <philippedeswert@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
[trini: Re-word Marek's explanation]
2015-12-07 13:28:09 -05:00
Tom Rini
cbb2df2018 CONFIG_NEEDS_MANUAL_RELOC: Fix warnings when not set
Now that we may compile (but not link) code calling fixup_cmdtable when
this is not set, we need to always have the declaration available.  We
should also make sure that anyone calling the function includes
<command.h> as that's where the function declaration is.

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-12-07 08:35:23 -05:00
Tom Rini
dcf4cb068e Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze 2015-12-07 08:13:02 -05:00
Michal Simek
8bebf03c73 dm: core: Enable SPL_SIMPLE_BUS by default
This option is needed for all SoCs which have nodes on bus. Without
enabling this drivers are not found and probed.
Issue was found on Zynq MMC probe.
Enable this option by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07 10:14:30 +01:00
Michal Simek
d6df048bca dm: cmd: Relocate subcommands when MANUAL_RELOC
Subcommands contain pointers to functions which are not updated when
MANUAL_RELOC is enabled. This patch fix it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07 10:14:30 +01:00
Michal Simek
e4099c8b80 i2c: cmd: Relocate subcommands when MANUAL_RELOC
Subcommands contain pointers to functions which are not updated when
MANUAL_RELOC is enabled. This patch fix it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07 10:14:30 +01:00
Michal Simek
c643f3ef9b serial: zynq: Remove duplicated header
debug_uart.h is included twice.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07 10:14:30 +01:00
Michal Simek
6bf87dacd9 serial: zynq: Fix incorrect reference to s5p driver
Remove this c&p error from s5p driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07 10:14:29 +01:00
Michal Simek
d9ae52c8f0 zynq: sdhci: Move driver to DM
Move driver to DM

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-07 10:14:29 +01:00
Michal Simek
400434537b zynq: sdhci: Remove zynq_sdhci_of_init()
Prepare for using DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 10:14:29 +01:00
Siva Durga Prasad Paladugu
b8a9bebeec zynq: sdhci: Calculate minimum frequency based on max frequency
Calculate the minimum sd clock based on max clock. This will
be done by add_sdhci() if we pass minimum clock as zero.
It also does based on SD host contoller version.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 10:14:29 +01:00
Michal Simek
769afa54c6 ARM: zynq: Remove unused SERIAL macros for serial_zynq
Remove unused macros when driver was moved to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 10:14:29 +01:00
Michal Simek
ec016a171d ARM: zynq: Extend malloc size
SPL DM MMC FAT requires more malloc space(3k fat buffers + dm)
that it is available now. Extend SPL malloc space.

Current OCM layout:
0xffff0000 - 0xfff2000 - Full malloc space
0xffff2000 - 0xffff300 - Stack location
0xfffff300 - CONFIG_SYS_MALLOC_F_LEN - Early malloc space
0xfffffd00 - sizeof(GD) - GD
0xfffffe00 - 0xffffffff - SoC specific boot code

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 10:14:29 +01:00
Michal Simek
83b6464daa ARM: zynq: Fix location of stack and malloc areas
The patch
"board_init: Change the logic to setup malloc_base"
(sha1: 9ac4fc8207)
breaks SPL for Zynq because it puts early alloc area on the stack which
caused that stack was decreased by CONFIG_SYS_MALLOC_F_LEN (0x400)
and there was not enough space for regular stack.

This patch changes memory layout to better utilize the last 64k OCM
block.
0xffff0000 - 0xfff1000 - Full malloc space
0xffff1000 - 0xffff300 - Stack location
0xfffff300 - CONFIG_SYS_MALLOC_F_LEN - Early malloc space
0xfffffd00 - sizeof(GD) - GD
0xfffffe00 - 0xffffffff - SoC specific boot code

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Moritz Fischer <moritz.fischer@ettus.com>
2015-12-07 10:14:29 +01:00
Michal Simek
e92fc6df7a ARM: zynq: Enable debug console for zc702
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 10:14:29 +01:00
Michal Simek
a7159e204b ARM64: zynqmp: Enable FIT config option via Kconfig
Remove configuration options from board file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 10:14:29 +01:00
Michal Simek
b8de29feae net: gem: Enable CTRL+C in wait_for_bit
Enable to break waiting loop at any time.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-12-07 10:14:29 +01:00
Michal Simek
596e5782e7 net: gem: Move gem to Kconfig
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 10:14:28 +01:00
Michal Simek
3cdb1450de net: gem: Read information about interface from DT
Do not set interface via configs. Read information from DT.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 10:14:28 +01:00
Michal Simek
6889ca7198 net: gem: Move driver to DM
- Enable DM_ETH by default for Zynq and ZynqMP
- Remove board_eth_init code
- Change miiphy_read function to return value instead of error code
  based on DM requirement
- Do not enable EMIO DT support by default

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-07 10:14:22 +01:00
Michal Simek
5a9284f7f5 net: gem: Fix miiphy_read name
Sync it with write function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 09:59:05 +01:00
Michal Simek
687d731263 net: gem: Remove zynq_gem_of_init()
This function was used for OF init before DM.
Remove this function as the part of move to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 09:59:05 +01:00
Michal Simek
c8e29271b1 net: gem: Enable MDIO bus earlier
Enable access to MDIO before zynq_gem_init is called.
It enables read information about phy earlier.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:05 +01:00
Michal Simek
90c6f2e21b net: gem: Check if priv->phydev is valid
Check return value.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 09:59:05 +01:00
Michal Simek
68cc3bd8b2 net: gem: Extract phy init code
Move phy init code out of zynq_gem_init. DM drivers are normally calling
this code from probe function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:04 +01:00
Michal Simek
64a7ead64b net: gem: Remove phydev variable
Resort code to use priv->phydev variable directly.
It will simplify move to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:04 +01:00
Michal Simek
f2fc27684f net: gem: Change mii function not to use eth_device structure
Next step to move driver to driver model. Do not use eth_device
structure. Use private structure instead.
Add iobase to private structure to store gem iobase.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:04 +01:00
Michal Simek
3fac27243c net: gem: Change mdio_wait prototype to pass regs
Pass regs instead of dev because this will be chagned by
driver model.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-12-07 09:59:04 +01:00
Michal Simek
b904725a11 net: gem: Do not continue if phy is not found
Add return value for phy detection algorithm to stop init function when
phy is not found.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 09:59:04 +01:00
Michal Simek
3cbbc2574b ARM: zynq: Remove CONFIG_API
CONFIG_API is causing compilation error when DM_ETH is enabled because
eth_get_dev() is not available.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 09:59:04 +01:00
Michal Simek
5df825d490 ARM: zynq: Remove PHYLIB from config to defconfig
Move PHYLIB from board config to defconfig

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-12-07 09:59:04 +01:00
Tom Rini
25ef4bea59 Merge git://git.denx.de/u-boot-nios 2015-12-06 21:53:18 -05:00
Tom Rini
2311335d4c Merge git://git.denx.de/u-boot-usb 2015-12-06 21:52:40 -05:00
Marek Vasut
540fcbca7e arm: socfpga: Enable CONFIG_DM_MMC
Enable driver model MMC support on SoCFPGA.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2015-12-07 00:15:59 +01:00
Marek Vasut
c35ed77a78 mmc: dwmmc: socfpga: Convert to DM
Convert the SoCFPGA shim for registering the DWMMC driver to DM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2015-12-07 00:15:59 +01:00
Marek Vasut
1c75596e68 arm: socfpga: Remove cpu_mmc_init()
This function triggers the registration of the dwmmc driver on SoCFPGA,
but this is not needed in case the driver is correctly probed from DT.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2015-12-07 00:15:59 +01:00
Stefan Roese
ae9996c806 arm: socfpga: Add SoCFPGA SR1500 board
The SR1500 board is a CycloneV based board, similar to the EBV
SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
2015-12-07 00:15:59 +01:00