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3 Commits

Author SHA1 Message Date
Troy Kisky
1482410531 MX53: DDR: Fix ZQHWCTRL field TZQ_CS 
Currently, board files are setting this field to 0x01
which the manual says is a reserved value. Change to
use the default of 0x02 - 128 cycles.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
 2012-04-16 14:53:58 +02:00
Fabio Estevam
9691c5b96d mx53: ddr3: Update DD3 initialization 
Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011:
-change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz)
-change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from
"0x092080b0". This changes write recovery from 8 clocks to 6 clocks
(in line with ESDCFG1[tWR])

Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
 2011-09-04 11:36:11 +02:00
Fabio Estevam
47c3e074ad MX53: Add initial support for MX53ARD 
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
 2011-07-04 10:55:26 +02:00