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MX53: DDR: Fix ZQHWCTRL field TZQ_CS

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Currently, board files are setting this field to 0x01
which the manual says is a reserved value. Change to
use the default of 0x02 - 128 cycles.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Troy Kisky 2012-03-22 12:00:31 +00:00 committed by Albert ARIBAUD
parent 607dfdf568
commit 1482410531
4 changed files with 4 additions and 4 deletions
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2
board/freescale/mx53ard/imximage_dd3.cfg
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@ -91,6 +91,6 @@ DATA 4 0x63fd901c 0x00028039
DATA 4 0x63fd901c 0x05208138
DATA 4 0x63fd901c 0x04008048
DATA 4 0x63fd9020 0x00005800
DATA 4 0x63fd9040 0x04b80003
DATA 4 0x63fd9040 0x05380003
DATA 4 0x63fd9058 0x00022227
DATA 4 0x63fd901C 0x00000000

2
board/freescale/mx53evk/imximage.cfg
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@ -108,5 +108,5 @@ DATA 4 0x63fd901c 0x00448039
DATA 4 0x63fd9020 0x00005800
DATA 4 0x63fd9058 0x00033335
DATA 4 0x63fd901c 0x00000000
DATA 4 0x63fd9040 0x04b80003
DATA 4 0x63fd9040 0x05380003
DATA 4 0x53fa8004 0x00194005

2
board/freescale/mx53loco/imximage.cfg
View File

@ -91,6 +91,6 @@ DATA 4 0x63fd901c 0x00028039
DATA 4 0x63fd901c 0x05208138
DATA 4 0x63fd901c 0x04008048
DATA 4 0x63fd9020 0x00005800
DATA 4 0x63fd9040 0x04b80003
DATA 4 0x63fd9040 0x05380003
DATA 4 0x63fd9058 0x00022227
DATA 4 0x63fd901c 0x00000000

2
board/freescale/mx53smd/imximage.cfg
View File

@ -91,6 +91,6 @@ DATA 4 0x63fd901c 0x00028039
DATA 4 0x63fd901c 0x05208138
DATA 4 0x63fd901c 0x04008048
DATA 4 0x63fd9020 0x00005800
DATA 4 0x63fd9040 0x04b80003
DATA 4 0x63fd9040 0x05380003
DATA 4 0x63fd9058 0x00022227
DATA 4 0x63fd901C 0x00000000