Commit Graph

49241 Commits

Author SHA1 Message Date
Masahiro Yamada
414e2dbbf2 fdt_region: remove unneeded fdt_internal.h inclusion
fdt_region.c does not depend on anything in libfdt_internal.h

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-01 22:19:10 +08:00
Masahiro Yamada
c960a68e20 libfdt: move FDT_RAMDISK_OVERHEAD to image-fdt.c
This macro is locally referenced in common/image-fdt.c

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-01 22:19:10 +08:00
Mario Six
e8d5291824 core: ofnode: Fix translation for #size-cells == 0
Commit 286ede6 ("drivers: core: Add translation in live tree case") made
dev_get_addr always use proper bus translations for addresses read from
the device tree. But this leads to problems with certain busses, e.g.
I2C busses, which run into an error during translation, and hence stop
working.

It turns out that of_translate_address() and fdt_translate_address()
stop the address translation with an error when they're asked to
translate addresses for busses where #size-cells == 0 (comment from
drivers/core/of_addr.c):

 * Note: We consider that crossing any level with #size-cells == 0 to mean
 * that translation is impossible (that is we are not dealing with a value
 * that can be mapped to a cpu physical address). This is not really specified
 * that way, but this is traditionally the way IBM at least do things

To fix this case, we check in both the live-tree and non-live tree-case,
whether the bus of the device whose address is about to be translated
has size-cell size zero. If this is the case, we just read the address
as a plain integer and return it, and only apply bus translations if the
size-cell size if greater than zero.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Reported-by: Martin Fuzzey <mfuzzey@parkeon.com>
Fixes: 286ede6 ("drivers: core: Add translation in live tree case")
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-01 22:19:10 +08:00
Andy Yan
bcfdf055f8 dm: core: make fixed-clock dt scan live dt compatible
dm_scan_fdt_node can't work when live dt is active,
we should use dm_scan_fdt_live instead.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-01 22:15:11 +08:00
Andre Heider
44683170f8 fs: cbfs: fix locating the cbfs header
The value at the end of the rom is not a pointer, it is an offset
relative to the end of rom.

Signed-off-by: Andre Heider <a.heider@gmail.com>
2018-03-31 16:00:03 +08:00
Andre Heider
33222c8a2c cmd: cbfs: fix reading the end_of_rom pointer for 64bit archs
The cast breaks the pointer on 64bit archs, so lets get rid of it.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
2018-03-31 16:00:03 +08:00
Kever Yang
1e656ad08c pinctrl-uclass: convert to use live dt
Use live dt interface for pinctrl_select_state_full()

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-31 15:59:59 +08:00
Kever Yang
d255fade66 core: add uclass_get_device_by_phandle_id() api
Add api for who can not get phandle from a device property.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-31 15:59:59 +08:00
Tom Rini
81cf7c8d45 Merge git://git.denx.de/u-boot-ubi 2018-03-25 12:02:13 -04:00
Tom Rini
2dc5165ee0 Merge git://git.denx.de/u-boot-spi 2018-03-25 12:01:44 -04:00
Tom Rini
f7c9e76fb8 Merge git://git.denx.de/u-boot-i2c 2018-03-25 12:00:48 -04:00
Tom Rini
89a650e0ff Xilinx changes for v2018.05
- Fix mkimage recognition
 - Update all my fragments
 
 ZynqMP:
 - Use clk driver
 - Support loading elfs in el1
 - Various DTS and defconfig changes
 - Enable newer pmufw versions
 - Support more clocks
 - Remove ep108
 - Secure image support
 - Fix memtest setup
 
 Zynq:
 - Enabling watchdog driver
 - Support more clocks
 - defconfig changes
 
 fpga:
 - Simplify error path
 
 net:
 - GMII case update
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iEYEABECAAYFAlq1D5kACgkQykllyylKDCHt5gCaA4AhhC+BPrFvD8cTFKPix7vq
 ctYAnA63Ye8IkvyOhgn3QwBL5+YXbsVP
 =7++x
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2018.05' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.05

- Fix mkimage recognition
- Update all my fragments

ZynqMP:
- Use clk driver
- Support loading elfs in el1
- Various DTS and defconfig changes
- Enable newer pmufw versions
- Support more clocks
- Remove ep108
- Secure image support
- Fix memtest setup

Zynq:
- Enabling watchdog driver
- Support more clocks
- defconfig changes

fpga:
- Simplify error path

net:
- GMII case update
2018-03-25 12:00:00 -04:00
Petr Vorel
c0ce4ceaba Convert CONFIG_UBI_SILENCE_MSG to Kconfig
Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
2018-03-24 06:37:25 +01:00
Petr Vorel
afb6fda2ae Convert CONFIG_UBIFS_SILENCE_MSG to Kconfig
Introduce another difference from upstream (kernel) source in
fs/ubifs/super.c: adding preprocessor condition as y variable in
mount_ubifs() depends on CONFIG_UBIFS_SILENCE_MSG:
fs/ubifs/super.c:1337:15: error: variable ?y? set but not used [-Werror=unused-but-set-variable]
  long long x, y;

Not setting CONFIG_UBIFS_SILENCE_MSG in am335x_igep003x_defconfig and
igep0032_defconfig. Although it was defined in their config headers, it
depends on CMD_UBIFS which is not set for them.

Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Heiko Schocher <hs@denx.de>
2018-03-24 06:37:10 +01:00
Petr Vorel
e995128158 ubifs: Reintroduce using CONFIG_UBIFS_SILENCE_MSG
Use of CONFIG_UBIFS_SILENCE_MSG was added in
147162dac6 ("ubi: ubifs: Turn off verbose prints")

Then it was removed in
ff94bc40af ("mtd, ubi, ubifs: resync with Linux-3.14")

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
2018-03-24 06:36:54 +01:00
Sjoerd Simons
63018a3edd omap3: spi: Correct ti, pindir-d0-out-d1-in parsing
The ti,pindir-d0-out-d1-in property is not expected to have a value
according to the device-tree binding, so treat it as a boolean not a
uint property.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-23 23:03:29 +05:30
Tom Rini
423effc04a Merge git://git.denx.de/u-boot-arc
Alexey:
 1. Significantly rework cache-related functionality.
    In particular that fixes coherency problems in some corner-cases,
    allows us to enable and disable caches in run-time and still
    have properly running system, finally support execution from
    real flash (before we used to run from DDR from the very beginning).

 2. Remove string routines implemented in assembly.
    That allows us to build and run U-Boot on wide range of ARC cores
    with different configurations. I.e. whatever tuning is used on GCC's
    command-line we'll get code for desired flavor of ARC.
    Otherwise for each and every corner-case we would need to add ifdefs
    in assembly code to accommodate missing instructions etc.

 3. Get use of GCC's garbage collector which helps to slim-down resulting image
    quite a bit.

 4. Also now we may disable U-Boot self-relocation for ARC if needed either
    by platform or for debugging purposes.
2018-03-23 09:31:24 -04:00
Eugeniy Paltsev
f665c14f04 ARC: bootm: Refactor GO and PREP subcommands implementation
Refactor GO and PREP subcommands implementation for a simpler
override in the boards platform code.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-03-23 15:57:51 +03:00
Michal Simek
8ae3d0b50c MAINTAINERS: Fix Zynq/ZynqMP and Microblaze fragments
Fix my fragments to list all files in the repo.

Also fix path to for Xilinx Zynq SoC (mach-zynq)
It should be the part of
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f24036)

And cover dts files in board MAINTAINERS files.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:36:15 +01:00
Michal Simek
d28baea078 tools: xilinx: Fix zynq/zynqmp image recognition
There is an issue to recognize zynq or zynqmp image because header
checking is just the same. That's why zynqmp images are recognized as
zynq one.
Check unused fields which are initialized to zero in zynq format
(__reserved1 0x38 and __reserved2 0x44) which are initialized for
zynqmp. This should ensure that images are properly recognized by:
./tools/mkimage -l spl/boot.bin

Also show image type as ZynqMP instead of Zynq which is confusing.

Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Alexander Graf <agraf@suse.de>
2018-03-23 09:36:15 +01:00
Siva Durga Prasad Paladugu
c436bf92f6 arm64: zynqmp: Add support for verifying secure images
This patch adds new command "zynqmp" to handle zynqmp
specific commands like "zynqmp secure". This secure command is
used for verifying zynqmp specific secure images. The secure
image can either be authenticated or encrypted or both encrypted
and authenticated. The secure image is prepared using bootgen
and will be in xilinx specific BOOT.BIN format. The optional
key can be used for decryption of encrypted image if user
key was specified while creation BOOT.BIN.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:36:15 +01:00
Michal Simek
348dbf4368 arm64: zynqmp: Remove ep108 board
ZynqMP Emulation board is no longer tested and there is no reason to
keep maintaining it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:59 +01:00
Siva Durga Prasad Paladugu
83bf2ff03d arm64: zynqmp: Correct EG/EV part detection logic
The vcu disable bit in efuse ipdisable register is valid only
if PL powered up so, consider PL powerup status for determing
EG/EV part. If PL is not powered up, ignore EG/EV part of string.
The PL powerup status will be filled by pmufw based on PL PROGB
status in the 9th bit of version field.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:44 +01:00
Vipul Kumar
a79b590f78 arm64: zynqmp: Print the value of pl clocks and wdt clock using clk dump
This patch print pl clocks (pl0...pl3) and watchdog
clock using clk dump.

Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:44 +01:00
Vipul Kumar
2453c69518 arm64: zynqmp: nand: Fixed NAND erase issue for size 1GiB or more
NAND erase was not happening for size 1GiB or more. Erase
command was executing successfully but in actual, it was not
erasing.
This patch fixed erase issue for 1 GiB or more size nand.

Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:44 +01:00
Michal Simek
2950e0b5a6 arm: zynq: Remove OF_EMBED configuration for zc770 xm011 x16
Use appended dtb which is default option for zynq boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:44 +01:00
Michal Simek
a587b501fa arm: zynq: Setup the same bootcommand as for zc770 xm011 x8
The same command should be used for x16 configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:44 +01:00
Vipul Kumar
fce0a6b521 arm64: zynqmp: Changed scratch address used by the alternate memory test
This patch changed CONFIG_SYS_MEMTEST_SCRATCH address to the
accessible DDR address used by alternate memory test.
Before this, 0xfffc0000 address was used, which is the OCM
address and not enabled in MMU table. So, whenever trying
to access 0xfffc0000 address, got Synchronous Abort exception.

After changing CONFIG_SYS_MEMTEST_SCRATCH address, alternate
memory test is working fine.

Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:44 +01:00
Michal Simek
f5e2943b8b arm: zynq: Enable cadence driver on zc706
Enable watchdog with reset-on-timeout feature.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:43 +01:00
Michal Simek
e6cc3b25d7 arm: zynq: Wire watchdog internals
Watchdog is only enabled in full u-boot. Adoption for SPL should be also
done because that's the right place where watchdog should be enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:43 +01:00
Shreenidhi Shedi
42537ca4c8 watchdog: Add Cadence watchdog driver
This IP can be found on Zynq and ZynqMP devices.
The driver was tested with reset-on-timeout; feature.

Also adding WATCHDOG symbol to Kconfig because it is required.

Signed-off-by: Shreenidhi Shedi <imshedi@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:43 +01:00
Michal Simek
58afff43e3 clk: zynq: Show watchdog clock rate properly
watchdog clock is also connected to cpu 1X clocksource.

Zynq> clk dump
...

Before:
      swdt          4294967290
After:
      swdt           111111110

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:43 +01:00
Michal Simek
1cf6cac4d1 arm64: zynqmp: Enable newer pmufw versions
As of now newer pmufw is keeping old interfaces. That's why permit
u-boot to run on newer version. Recommended version will be setup later.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:43 +01:00
Siva Durga Prasad Paladugu
d77081cf50 net: zynq_gem: Dont run any phy detection logic for GMII case
This patch bypasses phy detection logic for GMII interface
and just depend on phy address received from DT. This patch
is required as phy detection logic is different for some phys
like xilinx phy which can be connected over SGMII and GMII
interface.
This fixes the issue of ethernet failures when xilinx phy is
connected over GMII interface.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-03-23 09:34:42 +01:00
Nitin Jain
51916864b3 arm64: zynqmp: Add support to load an app at EL1
This patch is adding support to switch to EL1 while loading an EL1
application with u-boot running at EL above EL1 in aarch64 mode.

Signed-off-by: Nitin Jain <nitinj@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:42 +01:00
Siva Durga Prasad Paladugu
429f0b9e14 arm: zynq: Enable debug uart on Zedboard
It helps with debugging.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:42 +01:00
Michal Simek
12e6c06921 arm64: zynqmp: Enable ethernet driver for zc1751-dc5
Enable missing driver on this board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:42 +01:00
Michal Simek
cda1e3fb0f fpga: Simplify error path in fpga_add
Check !desc earlier to simplify code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
2018-03-23 09:34:42 +01:00
Michal Simek
734bf172e9 xilinx: Sync defconfigs with latest Kconfig updates
Make defconfigs up2date with current location.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:00 +01:00
Michal Simek
ee4983f73a arm64: zynqmp: Convert board to use zynqmp-clk driver
Use zynqmp clock driver instead of fixed clocks.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:30:44 +01:00
Heinrich Schuchardt
d45c2f392e i2c: lpi2c: remove superfluous assignments
In

	lpi2c_status_t result = A;
	result = B;

the first assignment has no effect. Let's remove it.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-03-23 08:28:49 +01:00
Tom Rini
b0af10443a Merge git://git.denx.de/u-boot-net 2018-03-22 16:35:43 -04:00
Lokesh Vutla
d6d8c4d4cc configs: omapl138: Enable DM and DT
Enable Driver Model and Device-tree support for omapl138 board
in U-Boot. Also enable DM_SERIAL and DM_I2C.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-03-22 16:32:31 -04:00
Lokesh Vutla
459353d43a ARM: dts: da850-lcdk: Sync from Linux 4.16
Sync dts from Linux 4.16 and also add u-boot specific
dtsi for OMAPl138 board.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-03-22 16:32:31 -04:00
Lokesh Vutla
891ab74b1f davinci: Enable DDR_INIT for DA8XX
Commit 6aa4ad8e38 ("Convert CONFIG_SOC_DA8XX et al to Kconfig")
converted SOC_DA8XX to Kconfig but missed enabling DDR_INIT for
SOC_DA8XX, which broke OMAPL138 to boot.

Commit 2e87980580 ("davinci: Fix omapl138_lcdk builds") disabled
DDR_INIT for all DA850 SoCs. This failed all DA850 boards to boot
as ddr is not being initialized.

Enable SYS_DA850_DDR_INIT for DA8XX so that all DA850 and OMAPL138
will have ddr initialized

Fixes: 2e87980580 ("davinci: Fix omapl138_lcdk builds")
Fixes: 6aa4ad8e38 ("Convert CONFIG_SOC_DA8XX et al to Kconfig")
Reported-by: Sekhar Nori <nsekhar@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: David Lechner <david@lechnology.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-03-22 16:32:31 -04:00
Faiz Abbas
5bd1facf5f configs: am335x_evm: Increase SPL_SYS_MALLOC_F_LEN to accomodate gpio_devices
With gpio devices getting created in SPL, the size of the heap is
no longer sufficient. Therefore, increase SPL_SYS_MALLOC_F_LEN
to 0x1000.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-03-22 16:32:31 -04:00
Faiz Abbas
8e14ba7bd5 gpio: omap_gpio: Add DM_FLAG_PRE_RELOC flag
With DM enabled in SPL, DM_FLAG_PRE_RELOC is required for
the omap_gpio driver to be bound to the gpio devices.

Therefore, add DM_FLAG_PRE_RELOC flag to the omap_gpio driver.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-03-22 16:32:30 -04:00
Luca Ceresoli
f69dce5081 scripts/check-config.sh: fix "command not found" error handling
scripts/check-config.sh exits successfully and silently without doing
any checks when the 'comm' command is not found.

The problem triggers from the command around line 39:

  comm -23 ${suspects} ${ok} >${new_adhoc}

This statement fails when 'comm' is not in $PATH, creating an empty
${new_adhoc} file. But the script continues and the following line,
which is supposed to detect an error:

  if [ -s ${new_adhoc} ]; then

will always be false since the file is empty, and the script will exit
successfully as if everything were OK.

The case where 'comm' in not in $PATH is not theoretical. It used to
happen on yocto until a recent fix [0], and still happens on the
current stable branch (rocko).

Fix by setting the errexit flag to exit with error when a statement
fails, so that at least the problem is noticed.

For additional safety also set the nounset flag to detect expansion
errors.

[0] http://git.yoctoproject.org/cgit/cgit.cgi/poky/commit/?id=fe0b4cb5b48580d4a3f3c0eb82bfa6f1b13801e4

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-03-22 16:32:30 -04:00
David Lechner
dc73483a12 davinci: omapl138_lcdk: fix PLL0 frequency
commit 1601dd97ed ("davinci: omapl138_lcdk: increase PLL0 frequency")
changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
block. However, in doing so, it caused the PLLOUT clock to be outside
of the allowable specifications given in the OMAP-L138 data sheet. (It
says PLLOUT must be 600MHz max). It also uses a PLLM value outside of
the range given in the TRM (it says PLLM must in the range 0 to 0x1f).

So here is what we have currently:

PLLOUT = 24 / (0 + 1) * (37 + 1) = 912MHz (out of spec)
         ^     ^         ^
       CLKIN PREDIV    PLLM (out of spec)

input to PLLDIVn = 912 / (1 + 1) = 456MHz (desired result)
                    ^     ^
                 PLLOUT POSTDIV

This changes the PLLM value to 18 and the POSTDIV value to 0 so that
PLLOUT is now within specification but we still get the desired
result.

PLLOUT = 24 / (0 + 1) * (18 + 1) = 456MHz (within spec)
         ^     ^         ^
       CLKIN PREDIV     PLLM

input to PLLDIVn = 456 / (0 + 1) = 456MHz (desired result)
                    ^     ^
                 PLLOUT POSTDIV

Fixes: 1601dd97ed ("davinci: omapl138_lcdk: increase PLL0 frequency")
Signed-off-by: David Lechner <david@lechnology.com>
Reported-by: Sekhar Nori <nsekhar@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
2018-03-22 16:32:24 -04:00
Liam Beguin
7f9b50a27c test/py: add spi_flash tests
Add basic tests for the spi_flash subsystem.

Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2018-03-22 16:32:20 -04:00