This commit adds paired dev info for winbond w25q16jv
(tested w25q16jvssiq with a i.mx6 board)
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add support for the Macronix mx25l1633e nor flash. (Tested on a imx6 board)
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add support for the Gigadevice gd25q16c nor flash. (Tested on a imx6 board)
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit adds the following flashes to the id-table
- W25Q16JV
- W25Q32JV
- W25Q64JV
- W25Q128JV
- W25Q256JV
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The N25Q256(A) datasheet clearly states that this device does have
a Flag Status Register and does update FSR PEC bit 7 during Program
and Erase cycles to indicate the cycle is in progress. Enable the
FSR PEC bit polling on this device to prevent data corruption.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Tom Rini <trini@konsulko.com>
For now, the existing SPL MXS NAND driver only supports to identify
ONFi-compliant NAND chips. In order to allow identifying
non-ONFi-compliant chips add `mxs_flash_full_ident()` which uses the
`nand_get_flash_type()` functionality from `nand_base.c` to lookup
for supported NAND chips in the chip ID list.
For compatibility reason the full identification support is only
available if the config option `CONFIG_SPL_NAND_IDENT` is enabled.
The lookup was tested on a custom i.MX6ULL board with a Toshiba
TC58NVG1S3HTAI0 NAND chip.
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
The existing `mxs_flash_ident()` is limited to identify ONFi compliant
NAND chips only. In order to support non-ONFi NAND chips refactor the
function and rename it to `mxs_flash_onfi_ident()`.
A follow-up patch will add `mxs_flash_full_ident()` which allows to use
the chip ID list to lookup for supported NAND flashs.
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Add the config option `CONFIG_SPL_NAND_IDENT` for using the NAND chip ID list
to identify the NAND flash in SPL.
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
`nand_get_flash_type()` allows identification of supported NAND flashs.
The function is useful in SPL (like mxs_nand_spl.c) to lookup for a NAND
flash (which does not support ONFi) instead of using nand_simple.c and
hard-coding all required NAND parameters.
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Add support for specified ECC strength/size using device tree
properties nand-ecc-strength/nand-ecc-step-size.
This aligns behavior with the mainline driver, such that:
- If fsl,use-minimal-ecc is requested it will use data from
data sheet/ONFI. If this is not available the driver will fail.
- If nand-ecc-strength/nand-ecc-step-size are specified those
value will be used.
- By default maximum possible ECC strength is used
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Support driver data from device tree. Also support fsl,use-minimal-ecc
similar to Linux' GPMI NAND driver.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
In preparation for device tree support separate board init
from controller init similar to other raw NAND drivers.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
This function initializes DMA descriptors so mxs_nand_init_dma is
more precise. It also frees up the rather generic name mxs_nand_init.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Move GPMI and BCH register structs to the driver struct mxs_nand_info
in prepartion for device tree support.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Add support for minimum ECC strength supported by the NAND chip.
This aligns with the behavior when using the fsl,use-minimum-ecc
device tree property in Linux.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Report correct ECC parameters back to the stack. Do not report
bytes as we have it not immeaditly available and the Linux version
also does not report it. It seems to have no aversive effect.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Calculate BCH geometry at start and store the information in
a structure. This avoids recalculation on every page access
and allows to calculate ECC relevant information in one place.
This patch does not change ECC layout or driver behavior in
any way.
The patch aligns the driver somewhat with the Linux GPMI NAND
driver which drives the same IP.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Add config option which allows to enable on flash bad block table
support. This has the same effect as when using the device tree
property "nand-on-flash-bbt" in Linux.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Instead of completing initialization via scan_bbt callback use
NAND self init to initialize the GPMI (MXS) NAND controller.
Suggested-by: Scott Wood <oss@buserror.net>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
In preparation to convert the driver to use NAND self init
provide a new minimal init for SPL builds. As a side effect
this also reduces size of SPL by about 4KiB.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Move the strdup() call so that it is only done when we know we will bind
the device.
Reported-by: Coverity (CID: 131216)
Signed-off-by: Simon Glass <sjg@chromium.org>
I just stumbled over some cluttered UBI messages. It seems some newline
chars are missing in the current U-Boot UBI source. Lets fix this
in U-Boot as well (Linux has those fixes already).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
This flash IC is used in some chromebook models
manufactured by Bitland.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The clean_bar() function resets the SPI NOR BAR register to 0, but
does not set the flash->curr_bar to 0 , therefore those two can get
out of sync, which could ultimatelly result in corrupted flash content.
The simplest test case is this:
=> mw 0x10000000 0x1234abcd 0x4000
=> sf probe
=> sf erase 0x1000000 0x10000
=> sf write 0x10000000 0x1000000 0x10000
=> sf probe ; sf read 0x12000000 0 0x10000 ; md 0x12000000
That is, erase a sector above the 16 MiB boundary and write it with
random pre-configured data. What will actually happen without this
patch is the sector will be erased, but the data will be written to
BAR 0 offset 0x0 in the flash.
This is because the erase command will call write_bar()+clean_bar(),
which will leave flash->bank_curr = 1 while the hardware BAR registers
will be set to 0 through clean_bar(). The subsequent write will also
trigger write_bar()+clean_bar(), but write_bar checks if the target
bank == flash->bank_curr and if so, does NOT reconfigure the BAR in
the SPI NOR. Since flash->bank_curr is still 1 and out of sync with
the HW, the condition matches, BAR programming is skipped and write
ends up at address 0x0, thus corrupting flash content.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
ftsmc020_init is not used anymore.
So it can be removed.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
Since 'commit f82290afc8 ("mtd: ubi: Fix worker handling")',
when booting from NAND, on a fresh NAND just after being flashed (and
only in this case), we got the following log:
ubi0: default fastmap pool size: 200
ubi0: default fastmap WL pool size: 100
ubi0: attaching mtd2
ubi0: scanning is finished
ubi0 error: ubi_update_fastmap: could not find any anchor PEB
ubi0 error: ubi_update_fastmap: could not find any anchor PEB
ubi0 error: ubi_wl_get_peb: Unable to get a free PEB from user WL pool
ubi0 error: autoresize: cannot auto-resize volume 1
UBI error: cannot attach mtd2UBI error: cannot initialize UBI, error
-28UBI init error 28
After analysis, in ubi_wl_init(), when performing schedule_erase(),
thread_enabled flag is not yet set to 1, which forbids ubi_do_worker()
to execute pending works.
This has to effect to not populate ubi->free with free physical
eraseblocks.
Following Richard Weinberger's advice, this patch has been
backported from kernel tree :
'commit 1cb8f9776c7d ("ubi: fastmap: Implement produce_free_peb()")'
Tested-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Heiko Schocher <hs@denx.de>
Added support for is25wp032, is25wp064 and is25wp128.
Signed-off-by: Kimmo Rautkoski <ext-kimmo.rautkoski@vaisala.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
microblaze:
- Align defconfig
zynq:
- Rework fpga initialization and cpuinfo handling
zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING
zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation
mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode
nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params
scsi:
- convert ceva sata to UCLASS_AHCI
timer:
- Add Cadence TTC for ZynqMP r5
watchdog:
- Minor cadence driver cleanup
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Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.07
microblaze:
- Align defconfig
zynq:
- Rework fpga initialization and cpuinfo handling
zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING
zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation
mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode
nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params
scsi:
- convert ceva sata to UCLASS_AHCI
timer:
- Add Cadence TTC for ZynqMP r5
watchdog:
- Minor cadence driver cleanup
Send address cycles as per value read from onfi parameter
page for Read and write commands instead of using a
hard coded value. This may vary for different parts and
hence use it from onfi parameter page value.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds support for 16-bit buswidth by determining
the bus width based on mio configuration.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Tegra NAND driver recently got broken by ongoing driver model resp.
live tree migration work:
NAND: Could not decode nand-flash in device tree
Tegra NAND init failed
0 MiB
A patch for NAND uclass support was proposed about a year ago:
https://patchwork.ozlabs.org/patch/722282/
It was not merged and I do not see on-going work for this.
This commit just provides a driver model probe hook to retrieve further
configuration from the live device tree. As there is no NAND ulass as of
yet (ab)using UCLASS_MTD. Once UCLASS_NAND is supported, it would be
possible to migrate to it.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
As per the IFC hardware manual, Most significant byte in nand_fsr
register is the outcome of NAND READ STATUS command.
So status value need to be shifted as per the nand framework
requirement.
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Number of ECC status registers i.e. (ECCSTATx) has been increased in
IFC version 2.0.0 due to increase in SRAM size. This is causing
eccstat array to over flow.
So, replace eccstat array with u32 variable to make it fail-safe and
independent of number of ECC status registers or SRAM size.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have multiple licenses (in
these cases, dual license) declared in the SPDX-License-Identifier tag.
In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A
or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B"
as per the Linux Kernel style document. Note that parenthesis are
allowed so when they were used before we continue to use them.
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
