As of Linux 4.16, a multiplatform AArch64 kernel with our distro config
takes 26M. The current space reservation leaves only 17M for the kernel
and if it goes over it, the initrd gets overwritten when loading the
kernel from the filesystem.
A similar problem happens on ARMv7 with the DTBs taken from the
downstream Raspberry Pi foundation kernel. I guess they compile them
with DT overlay support enabled which grows them just enough.
Fix both of these problems by rewriting the memory map, which now allows
kernels to be up to 36M and DTBs up to 1M. Also the comment block was
kind of obsolete ever since the introduction of AArch64 support and the
firmware-loaded DTB doesn't get placed at 0x100 anymore either, so that
is fixed as well.
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
The bcm2835 sdhost driver has a problem with "write multiple" commands.
It seems to boil down to the fact that the controller dislikes its FIFO
to get drained at the end of a block when a write multiple blocks command
is in flight.
The easy fix is to simply get rid of all the IRQ driven logic and make
the driver push as much data into the FIFO as it can. That way we never
drain and we never run into the problem.
Reported-by: Jan Leonhardt <jan@cyberdesigner.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Back in the old days, 0x100 was used as the address to pass the device tree
from firmware into the kernel. This has since changed to a more dynamic
location, so using 0x100 actually breaks more things than it helps with.
Let's move the device tree default location for distro boot to a more sane
place that gives us enough head room in low memory.
Reported-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
- Xilinx aarch64 is caught in the general xilinx arm job, exclude from
the general aarch64 job.
- Give the generic aarch64 job a better name
- Re-sort the PowerPC jobs so that we can complete them a bit quicker.
Signed-off-by: Tom Rini <trini@konsulko.com>
Add support for gcc versions 7.3.0, 6.4.0 and 4.9.4.
Also use a regex for matching the tarball names. Some gcc versions
use '-ARCH-' instead of '_ARCH-'.
As part of this, we switch TravisCI to also using these toolchains for
all platforms.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
- spl_board_init is empty on smartweb so drop that function
- When CONFIG_AT91SAM9_WATCHDOG is set we do not disable the watchdog in
SPL and instead let full U-Boot handle it. Instead of an empty
function just do not call a function.
Signed-off-by: Tom Rini <trini@konsulko.com>
For booting Linux in the generic distro mechanism, cmd/pxe.c
retrieves the FDT file name from "fdtfile" environment variable.
Rename "fdt_file" to "fdtfile" for easier migration to distro boot.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Change the phy-mode property to 'internal' that means to use a built-in PHY
implemented on LD11 SoC.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add clock-names and reset-names because this node recognizes multiple
clocks and resets. ("ether", and so on, for each)
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The GIO clock/reset, another MAC clock, and the PHY clock are required
for the ethernet of Pro4 SoC.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add syscon-phy-mode property specifying a phandle of system controller
to each ethernet node.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Drop per-SoC Makefile entries and replace them with one unified entry
now that the PFC tables are gone. Shuffle the Makefile around a bit
to make it more organized.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
All the boards use new modern PFC framework, the old PFC tables
are no longer used, so remove them.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The V2H Blanche port was broken since some time. This patch updates
the V2H Blanche port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Enable the DM capable driver instead of the legacy one.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Enable the DM capable driver instead of the legacy one.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add derivative of the rcar_i2c driver which is capable of
probing itself from DM and uses DT.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Remove the rcar_i2c driver, since it's no longer used by any
board and will be superseded by a DM and DT capable variant.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
devm_zalloc() is already defined in dm/device.h header, so
devm_zalloc can be removed from linux_compact.h beader file.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Switch to DM_USB was done and there is no need to keep !DM_USB code in
tree.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Remove harcoded XHCI lists and detect mode, speed based on DT.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Serial-changes: 2
- Remove also XHCI macros from hardware.h
- Remove additional new line in zcu106
By enabling BLK by default this is the next driver which needs to get
support for DM_USB. Adding generic DWC3 glue logic which only
parse nodes and read device mode. Based on it probe proper
host/peripheral DWC3 drivers for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support to get maximum speed from dt so that usb drivers
makes use of it for DT parsing.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
(rebase and fix errors)
Reviewed-by: Simon Glass <sjg@chromium.org>
The patch is preparing dwc3 core for enabling DM_USB with peripheral
driver with using driver model support.
The driver will be bound by the DWC3 wrapper driver based on the
dr_mode device tree entry.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
(Remove dwc3-omap changes)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds phy tranceiver driver for STM32 USB PHY
Controller (usbphyc) that provides dual port High-Speed
phy for OTG (single port) and EHCI/OHCI host controller
(two ports).
One port of the phy is shared between the two USB controllers
through a UTMI+ switch.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
During file download, it only uses 32bit variable for file size and
it limits maximum file size less than 4GB. Update to support more
than 4GB file with using two 32bit variables for file size as thor
protocol 5.0.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
The thor sender can send filename without null character and it is
used without consideration of overflow. Actually, character array
for filename is assigned with DEFINE_CACHE_ALIGN_BUFFER() and it
is bigger than size of memcpy, so there was no real overflow.
Fix filename overflow for code level integrity.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is
accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch
conditional build in order this file can by shared across other SOCFPGAs.
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add pinmux driver support for Stratix SoC
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add Reset Manager driver support for Stratix SoC
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add Clock Manager driver support for Stratix SoC
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add the base address for watchdog and firewall.
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
According to ARM Cortex-A9 MPCore TRM section 2.2 - SCU registers
Access Control register offset is 0x50.
Signed-off-by: Ben Kalo <ben.h.kalo@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Clock frequency info is required in U-Boot because info would be erased
when transition from SPL to U-Boot.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Enable memory allocation in SPL for preparation to enable FAT
in SPL. Memory allocation is needed by FAT to work properly.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>