Commit Graph

34153 Commits

Author SHA1 Message Date
Bin Meng
1d4c83c248 x86: tsc: Remove legacy timer codes
Now that we have converted all x86 boards to use driver model timer,
remove these legacy timer codes in the tsc driver.

Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option,
as it is not needed with driver model.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:26:35 -07:00
Bin Meng
80af39842e x86: Convert to use driver model timer
Convert all x86 boards to use driver model tsc timer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:26:35 -07:00
Simon Glass
881c124ab8 dm: timer: Avoid using timer before it is ready
At present bootstage will try to read the timer very early after relocation.
When driver model is used to provide the timer, we cannot read it until
driver model is ready. Correct this by adding a separate stage for the
post-relocation bootstage init.

This fixes booting on chromebook_link.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
2015-12-01 06:26:12 -07:00
Bin Meng
4e51fc2351 x86: tsc: Add driver model timer support
This adds driver model timer support to x86 tsc timer driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
2f80fc5035 x86: tsc: Use notrace from <linux/compiler.h>
Replace __attribute__((no_instrument_function)) with notrace from
<linux/compiler.h>.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
0f3176ed68 x86: Remove MIN_PORT80_KCLOCKS_DELAY
This is not referenced anywhere. Remove it, as well as
tsc_base_kclocks and tsc_prev in the global data.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix 'Reomve' typo:
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
9ca07ebbac dm: timer: Support 64-bit counter
There are timers with a 64-bit counter value but current timer
uclass driver assumes a 32-bit one. Modify timer_get_count()
to ask timer driver to always return a 64-bit counter value,
and provide an inline helper function timer_conv_64() to handle
the 32-bit/64-bit conversion automatically.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
f838f12452 timer: sandbox: Use device tree to pass the clock frequency
We should use device tree to pass the clock frequency of the timer
instead of hardcoded in the driver codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
9e360a5c9c timer: altera: Remove the codes to get clock frequency
Since we have timer uclass to get clock frequency for us, remove
the custom version in the altera timer driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
579eb5a0cc dm: timer: Implement pre_probe()
Every timer device needs to have a valid clock frequency and it
can be specified in the device tree. Use pre_probe() to get this
in the timer uclass driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Bin Meng
435ae76edd dm: timer: Fix several nits
This changes 'Timer' to 'timer' at several places.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-12-01 06:23:51 -07:00
Tom Rini
4a421a67b6 Merge branch 'master' of git://git.denx.de/u-boot-atmel 2015-11-30 18:13:10 -05:00
Wenyou Yang
e4677f1ae2 arm: at91/spl: atmel_sfr: move saic redirect to separate file
To make saic redirect code sharing with other SoCs, move the
saic redirect code from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/atmel_sfr.c

Move ATMEL_SFR_AICREDIR_KEY definition to sama5d4.h, because each
SoC has its own value.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-30 22:27:55 +01:00
Wenyou Yang
b5665bf246 arm: at91/spl: matrix: use matrix slave id macros
To make matrix initialization code sharing with others,
use the matrix slave id macros, instead of hard-coding.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-30 22:27:54 +01:00
Wenyou Yang
6f0a51aa68 arm: at91/spl: matrix: remove security peripheral select code
Remove the security peripheral select code, keep the default value
in these registers, that is, the peripheral address space is
configured as "Secured" access, it is suitable for SPL.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-30 22:27:54 +01:00
Wenyou Yang
5906d2aa0c arm: at91/spl: matrix: remove matrix write protection code
On processor reset, the matrix write protection is disabled,
so no need to disable/enable write protection when writing
the matrix registers.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-30 22:27:54 +01:00
Wenyou Yang
5cb9dfa031 arm: at91/spl: matrix: move matrix init to separate file
To make the matrix initialization code sharing with other SoCs,
move it from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/matrix.c

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-30 22:27:53 +01:00
Wenyou Yang
75238f2367 arm: atmel: Add SAMA5D2 Xplained board
The board supports following features:
 - Boot media support: SD card/e.MMC/SPI flash,
 - Support LCD display (optional, disabled by default),
 - Support ethernet,
 - Support USB mass storage.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
[fix checkpatch warnings]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-30 22:27:53 +01:00
Wenyou Yang
2c62c56a86 gpio: atmel: Add the PIO4 driver support
The PIO4 is introduced from SAMA5D2, as a new version
for Atmel PIO controller.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2015-11-30 22:27:52 +01:00
Tom Rini
1670c8c219 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-11-30 15:18:30 -05:00
York Sun
3785f57015 armv8: fsl-layerscape: Fix early MMU table for nand boot
The early MMU table doesn't enable all addresses. Unused addresses
are marked as invalid, as introduced by commit 9979922. An entry
was missing for NAND flash space, causing nand boot failure.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
2015-11-30 09:11:13 -08:00
Alison Wang
1d3a76facc armv8: ls2080a: Define CONFIG_ENV_OVERWRITE to overwrite serial and ethaddr
As the environment variables "serial#" and "ethaddr" need to be
overwriten by the users, CONFIG_ENV_OVERWRITE is defined to disable
the write protection. Anybody can change or delete these parameters.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:13 -08:00
Shaohui Xie
f8642ba6dd net: phy: added aquantia PHY AQR405 support
The phy can share driver with other aquantia PHYs, so we only
add PHY ID.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:13 -08:00
Prabhakar Kushwaha
b401736463 armv8: ls2085a: Add workaround of errata A009635
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.

Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:12 -08:00
Prabhakar Kushwaha
5380335e66 board/ls2080qds: Fix typo in README for QSGMII riser card
DPMACx to PHY mapping for SGMII is mentioned as QSGMII.

So fix typo in README for QSGMII rise card.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Change from ls2085aqds to ls2080aqds]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:12 -08:00
Alison Wang
99fe454171 arm: ls102xa: Update fdt_high and initrd_high for LS1021AQDS board
As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel
fails to access the device tree blob on boot. The reason is that u-boot
relocates the device tree blob into high memory when booting the kernel
and the kernel is unable to access the blob.

To avoid this issue, fdt_high is set to the value of 0xffffffff. The
device tree blob will not get relocated and is still in low memory to
make it accessible to the kernel.

For the same reason, initrd_high is set to the value of 0xffffffff too.

This patch is to update fdt_high and initrd_high for LS1021AQDS board.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:12 -08:00
York Sun
1f6236f06b armv8: fsl-layerscape: Fix "cpu release" command
When one core is released, other cores may not have valid entry
address. Those cores are trapped by "wfe" and wait for further
instruction. When their address is set, they need to be kicked
off by "sev".

Signed-off-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:12 -08:00
York Sun
da305b9f57 drivers/ddr/fsl: Fix typo in BIST test for DDR4
BIST test code has a typo, resulting the binding registers not
maintained as expected. This typo results BIST runs twice on
the covered memory.

Signed-off-by: York Sun <yorksun@freescale.com>
Reported-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2015-11-30 09:11:12 -08:00
Alison Wang
d764129d30 armv8/layerscape: Update MMU table with execute-never bits
For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
2015-11-30 09:11:11 -08:00
York Sun
61bd2f75f5 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Gong Qianyu
7023100971 armv8/ls1043ardb: add USB support
Add support for the third USB controller for LS1043A.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Gong Qianyu
28752cf83b armv8/ls1043ardb: add DSPI support
Use the U-Boot Driver Model. Just enable Freescale DSPI driver
and set DSPI related parameters in dts file.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Gong Qianyu
630532f51f armv8/ls1043aqds: dts: add dtb support
Reuse the dts files from ls1043a linux kernel.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Shaohui Xie
02b5d2ed86 armv8/ls1043aqds: add LS1043AQDS board support
LS1043AQDS Specification:
-------------------------
Memory subsystem:
 * 2GByte DDR4 DIMM
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * Two RGMII ports
 * XFI 10G port
 * SGMII
 * QSGMII with 4x 1G ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
[York Sun: Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Gong Qianyu
e1cecb4d42 armv8/ls1043ardb: dts: add dtb support
Reuse dts files from ls1043a linux kernel. Some parts in dts files
may not be needed by U-Boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Gong Qianyu
18a0d8eb46 armv8/fsl-layerscape: Remove reference to gdata
The global_data pointer (gd) has been set earlier in crt0_64.S.
So there's no need to assign it again. Remove gdata since it is going
away in U-Boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Mingkai Hu
af523a0d56 pci/layerscape: add support for LS1043A PCIe LUT register access
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Prabhakar Kushwaha
06b5301043 armv8: ls2085a: Add support of LS2085A SoC
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
           Dropped #ifdef in cpu.h
           Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:10:47 -08:00
Prabhakar Kushwaha
449372148f armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:04 -08:00
Prabhakar Kushwaha
14480454c7 driver: net: ldpaa: Fix Rx buffer alignment
MC 0.7.1.2 enforces limitation i.e.: "Packets may be corrupted
in several combinations of buffer size and frame offsets.
Workaround: Use buffers that are of size that is a multiple of 256, and
frame offset that is a multiple of 256"

Updating the DPNI Eth driver to comply with the restriction.

Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
5038d3e5f2 driver: net: ldpaa: Add debug information
Add following debug information in the driver
 - Get various DPNI counter values
 - Get link status of DPNI objects
 - Get information of both ends of connection (DPMAC - DPNI)

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
c919ab9ee5 driver: net: ldpaa: Use DPMAC as net device
As per current implementation of DPAA2 ethernet driver DPNI is used as
net device. DPNI is tangible objects can be multiple connected to same physical lane.

Use DPMAC as net device where it represents physical lane.
Below modification done in driver
 - Use global DPNI object
 - Connect DPMAC to DPNI
 - Create and destroy DPMAC

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
1730a17db9 driver: net: fsl-mc: Create DPAA2 object at run-time
Freescale's DPAA2 ethernet driver depends upon the static DPL for the
DPRC, DPNI, DPBP, DPIO objects.

Instead of static objects, Create DPNI, DPBP, DPIO objects at run-time.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
fb4a87a737 driver: net: fsl-mc: Add DPAA2 commands to manage MC
Management complex Firmware, DPL and DPC are depolyed during u-boot boot
sequence.

Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop
and apply DPL from u-boot command prompt.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:03 -08:00
Prabhakar Kushwaha
553d2751c1 driver: net: fsl-mc: Increase MC command timeout
dpni_create API take takes more time as comapred to existing supported
APIs of MC Flib.
So increase MC command timeout.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Prabhakar Kushwaha
f9127a046d driver: ldpaa: Add api to return linked PHY ID of DPMAC
DPMAC represents physical line on the board. This physical
line eventually asscociate with on-board PHY.

So Add an api to return linked PHY ID of DPMAC object.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Prabhakar Kushwaha
25af413740 armv8: ls2085aqds: Print function name during SerDes error
Print function name along with SerDes Protocol during SerDes Protocol
not supported error.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Prabhakar Kushwaha
872d48a777 driver: net: fsl-mc: Add APIs for DPMAC objects in FLIB
DPMAC object of Management complex controls Physical MAC and MDIO controller.
It provides APIs for MDIO and link state updates. It also provides APIs for
PHY/link configuration.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Prabhakar Kushwaha
1ebbe4fcf7 driver: net: fsl-mc: Add create, destroy APIs in flibs
Current Management Complex Flibs does not support APIs for adding and
destroying the objects.

Add APIs to create and destroy objects for DPBP, DPIO, DPNI and DPRC.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00
Prabhakar Kushwaha
99e904c1f0 armv8: lsch3: Fix lane protocol parsing logic
Current implementation only consider SGMIIs for dpmac initialization.
XFI serdes protocols also uses dpmac.

Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:02 -08:00