Current implementation to get board version through GPIO is
broken due to endianness issue hence it is not working for rev B
board.
Fix it to make it work for Rev A as well as Rev B boards
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
In commit <db4080d56dec>, SPL_FSL_PBL is removed from the configs of
some LayerScape platforms. Actually, SPL_FSL_PBL is needed for SD/NAND
boot on LS1021A/LS1043A/LS1046A to create boot binary having SPL binary
in PBI format concatenated with u-boot binary. SPL_FRAMEWORK is used on
these platforms too.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Hardware comes out of reset with implicit values, but these are outside
the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
Allocate different IDs and fix up Linux DT to use them.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
LX2160A PL011 UART driver fetch IP block values using
platform data from board file instead of device tree.
Modified UART nodes in device tree to disable state.
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar
to erratum A-009007, but this one is for LX2160A,
and the register value is different.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Mark board_fit_config_name_match() as weak so a board can overwrite the
empty function.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Maximum size of secure boot header to be read from MMC is
12KB which spans across 0x20 blocks.
Hence increase the mmc read size for secure boot
headers from MMC to 0x20 blocks.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add support for DPSPARSER object (create/destroy, open/close, apply spb)
which is required to configure Soft Parser by using MC.
Also add uboot command to apply Soft Parser Blob with command:
fsl_mc apply spb <spb_load_addr>
Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
- Enable DM driver on ppc/km boards
- Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x,
T104x, P4080, P2041, P2020, P1020, P3041
- Some updates in mpc85xx-ddr driver, km boards
This is the first step to use DM support for the KM powerpc boards.
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
CC: Mario Six <mario.six@gdsys.cc>
CC: Wolfgang Denk <wd@denx.de>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
Some of t1042 boards fails DDR init with an Automatic calibration error
every now and then. Investigations revealed that true Warm boots
never failed. Warm boots has some extra steps performed, one being
to start DDRC in Self Refresh and then clearing SR right after.
Applying this SR method unconditionally made all our boards
stable again, regardless of Cold/Warm boot.
Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
CONFIG_CONS_INDEX is nowhere used for this board, we can drop it.
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
We can use the existing CONFIG_SYS_CONFIG_NAME define for that and
remove the option. Also fix the boot string for all km83xx boards.
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
Remove this from the board header files and move it to Kconfig. Also use
the correct default address for kmtegr1.
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
On kmtegr1 we have to specify the second localbus clock signal also
instead of using the default for our ppc 8309 boards.
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral
i2c: for next
- misc: i2c_eeprom:
Add partition support and add ability to query size
of eeprom device and partitions
- i2c common:
add support for offset overflow in to address and add
sandbox tests for it.
Add ability to query size of eeprom device and partitions
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add support for setting the chip address offset mask to EEPROM sumulator
and add tests to test it.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Improve i2c EEPROM simulator testing by providing access functions to
check the previous chip addr and offset.
Given that we can now directly test the offsets, also simplified the
offset mapping and allow for wrapping acceses.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Some devices (2 wire eeproms for example) use some bits from the chip
address to represent the high bits of the offset instead of or as well
as using multiple bytes for the offset, effectively stealing chip
addresses on the bus.
Add a chip offset mask that can be set for any i2c chip which gets
filled with the offset overflow during offset setup.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Signed-off-by: Ian Ray <ian.ray@ge.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add support for coral which is a range of Apollo Lake-based Chromebook
released in 2017. This also includes reef released in 2016, since it is
based on the same SoC.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The memory and silicon init parts of the FSP need support code to work.
Add this for Apollo Lake.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These are mostly specific to a particular SoC. Add the definitions for
Apollo Lake.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports
various child devices. It supposed both device tree and of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add code to init the system both in TPL and SPL. Each phase has its own
procedure.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add loaders for SPL and TPL so that the next stage can be loaded from
memory-mapped SPI or, failing that, the Fast SPI driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
