This patch fixes a problem with DIMMs that have 8 banks. Now the
MCIF0_MBxCF register will be setup correctly for this setup too.
This was noticed with the 512MB DIMM on Canyonlands/Glacier.
Signed-off-by: Stefan Roese <sr@denx.de>
Since the current dflush() implementation is know to have some problems
(as seem on lwmon5 ECC init) this patch removes it completely and replaces
it by using clean_dcache_range().
Tested on Katmai with ECC DIMM.
Signed-off-by: Stefan Roese <sr@denx.de>
On ppc405EP and ppc405GP (at least) the ebc is directly attached to the plb
and not to the opb. This patch will try to fixup /plb/ebc if /plb/opb/ebc
doesn't exist.
Signed-off-by: Markus Brunner <super.firetwister@gmail.com>
The PCIe root-complex/endpoint setup as configured via the "pcie_mode"
environment variable will now get passed to the Linux kernel by setting
the device_type property of the PCIe device tree node. For normal root-
complex configuration it will keep its defaults value of "pci" and for
endpoint configuration it will get changed to "pci-endpoint".
Signed-off-by: Stefan Roese <sr@denx.de>
dcache_enable() was missing for 440 and the patch
017e9b7925 ["allow ports to override bootelf
"] behavior uses this function.
Note: Currently the cache handling functions like
d/icache_disable/enable() are NOP's on 440. This may be changed in the
future.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch assigns the correct EBC clock for 405GP(r) CPUs
to PPC4xx_SYS_INFO structure. Without this patch U-Boot
uses an uninitialized EBC clock in its startup message.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Currently U-Boot crashes in ppc_4xx_eth_init on sequoia
with cache enabled (TLB Parity exeption). This patch
fixes the problem.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Currently U-Boot crashes on sequoia board in CPU POST if
cache is enabled (CONFIG_4xx_DCACHE defined). The cache
won't be disabled by change_tlb before CPU POST because
there is an insufficient adress range check since
CFG_MEM_TOP_HIDE was introduced. This patch tries to fix
this problem.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This patch fixes a problem with the RGMII setup of the 460GT. The 460GT
has 2 RGMII instances and we need to configure the 2nd RGMII instance
for the EMAC2+3 channels.
Signed-off-by: Stefan Roese <sr@denx.de>
This bug was introduced with commit aee747f19b
which enabled CFG_4xx_GPIO_TABLE for PPC405 and unintentionally
disabled the setting of the emac noise filter bits for PPC405EP when CFG_4xx_GPIO_TABLE is set.
Signed-off-by: Markus Brunner <super.firetwister@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured
after startup to change the speed of the clocks. This patch adds the
option CFG_PLL_RECONFIG. If this option is set to 667, the CPU
initialization code will reconfigure the PLL to run the system with a CPU
frequency of 667MHz and PLB frequency of 166MHz, without the need for an
external EEPROM.
Signed-off-by: Mike Nuss <mike@terascala.com>
Acked-by: Stefan Roese <sr@denx.de>
This patch adds support for the AMCC Glacier 460GT eval board.
The main difference to the Canyonlands board are listed here:
- 4 ethernet ports instead of 2
- no SATA port
- no USB port
Currently EMAC2+3 are not working. This will be fixed in a later
release.
Signed-off-by: Stefan Roese <sr@denx.de>
460EX doesn't support a fixed bootstrap option to boot from 512 byte page
NAND devices. The only bootstrap option for NAND booting is option F for
2k page devices. So to boot from a 512 bype page device, the I2C bootstrap
EEPROM needs to be programmed accordingly.
This patch adds basic NAND booting support for the AMCC Canyonlands aval
board and also adds support to the "bootstrap" command, to enable NAND
booting I2C setting.
Tested with 512 byte page NAND device (32MByte) on Canyonlands.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch is a rework of the 4xx interrupt handling done while
adding the 460EX/GT support. Interrupts are needed on 4xx for the
EMAC driver.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch changes the physical addess parameter from 32bit to 64bit.
This is needed for 36bit 4xx platforms to access areas located
beyond the 4GB border, like SoC peripherals (EBC etc.).
Signed-off-by: Stefan Roese <sr@denx.de>
Every now and then a Sequoia board (or equivalent hardware) had
problems connecting to a Gigabit capable network interface.
There were differences in the PHY setup between Linux and U-Boot.
This patch fixes the problem. Apparently "remote fault" is being set,
which signals to some devices (on the other end of the cable) that a
fault has occurred, while other devices ignore it. I believe the RF bit
was causing the issue, but I removed T4 also, to match up with Linux.
Signed-off-by: Mike Nuss <mike@terascala.com>
The 405EZ only supports 512 bytes of rx-/tx-fifo EMAC sizes. But
currently 4k/2k is configured. This patch fixes this issue.
Thanks to Thomas Kindler <tkindler@lenord.de> for pointing this out.
Signed-off-by: Stefan Roese <sr@denx.de>
U-Boot crashes in the net loop if CONFIG_4xx_DCACHE is
enabled. To reproduce the problem ensure that 'ethrotate'
environment variable isn't set to "no" and then run
"tftp 200000 not_existent_file".
This patch tries to fix the issue.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc
will refuse to use load/store multiple insns; instead, it issues a
list of simple load/store instructions upon function entry and exit,
resulting in bigger code size, which in turn makes the build for a
few boards fail.
Use r2 instead.
Signed-off-by: Wolfgang Denk <wd@denx.de>
The current ndfc HW ECC implementation swaps the first two ECC bytes.
But the 4xx NDFC already uses the SMC (Smart Media Card) ECC ordering,
so this swapping in the HW ECC driver is bogus. This patch fixes this
problem and now really uses the SMC ECC byte order.
Thanks to Sean MacLennan for pointing this out.
Signed-off-by: Stefan Roese <sr@denx.de>
The privious 4xx POST implementation only supported storing the POST
WORD in OCM. Since we need to reserve the OCM on LWMON5 for the logbuffer
we need to store the POST WORD in some other non volatile location.
This patch adds CFG_POST_ALT_WORD_ADDR to specify an address for such
a location.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for locking the init-ram/stack in d-cache,
so that other regions may use d-cache as well
Note, that this current implementation locks exactly 4k of d-cache,
so please make sure that you don't define a bigger init-ram area. Take
a look at the lwmon5 440EPx implementation as a reference.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch allows the use of 4xx interrupt vector number defines
in board specific code outside cpu/ppc4xx.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Now that there are no board-specific versions of
"denali_core_search_data_eye()", the weak binding on the common version
can be removed.
Signed-off-by: Larry Johnson <lrj@acm.org>
On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.
This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
Signed-off-by: Stefan Roese <sr@denx.de>
This patch makes two additions to GPIO support:
First, it adds function gpio_read_in_bit() to read the a bit from the
GPIO Input Register (GPIOx_IR) in the same way that function
gpio_read_out_bit() reads a bit from the GPIO Output Register
(GPIOx_OR).
Second, it modifies function gpio_set_chip_configuration() to provide
an additional option for configuring the GPIO from the
"CFG_4xx_GPIO_TABLE".
According to the 440EPx User's Manual, when an alternate output is used,
the three-state control is configured in one of two ways, depending on
the particular output. The first option is to select the corresponding
alternate three-state control in the GPIOx_TRSH/L registers. The second
option is to select the GPIO Three-State Control Register (GPIOx_TCR) in
the GPIOx_TRSH/L registers, and set the corresponding bit in the
GPIOx_TCR register to enable the output. For example, the Manual
specifies configuring the GPIO00 Alternate 1 Signal (PreAddr07) to use
the alternate three-state control (first option), and specifies
configuring the GPIO32 Alternate 1 Signal (USB2OM0) with the output
enabled in the GPIOx_TCR register (second option).
Currently, gpio_set_chip_configuration() configures all alternate signal
outputs to use the first option. This patch allow the second option to
be selected by setting the "out_val" element in the table entry to
"GPIO_OUT_1". The first option is used when the "out_val" element is
set to "GPIO_OUT_0". Because "out_val" is not currently used when an
alternate signal is selected, and because all current GPIO tables set
"out_val" to "GPIO_OUT_0" for all alternate signals, this patch should
not change any existing configurations.
Signed-off-by: Larry Johnson <lrj@acm.org>
In an attmemt to clean up the 4xx start.S file, I removed the enabling
of the internal 405EP PCI arbiter. This is needed for multiple other
405EP platforms, like most of the esd 405EP. Now the internal PCI
arbiter is enabled again per default as it has been before.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
