TI QSPI driver directly typecasts fdt_addr_t to a pointer. This is
not strictly correct, as it gives a build warning when fdt_addr_t is u64.
So, use map_physmem for a proper typecasts.
This is inspired by commit 167efe01bc ("dm: ns16550: Use an address
instead of a pointer for the uart base")
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
In some case wordlen may not be set. Use SPI_DEFAULT_WORDLEN as default.
Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
When CONFIG_DMA is defined the default spi_flash_copy_mmap() can
handle dma memory copy, so compile out spi_flash_copy_mmap() from
ti_qspi driver when CONFIG_DMA config is defined.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Spell out 'sbase' to 'spi_base' so that it looks clearer.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
The ICH SPI controller supports two variants, one of which is ICH7
compatible and the other is ICH9 compatible. Change 'pch_version'
to 'ich_version' to better match its original name.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Simon Glass <sjg@chromium.org>
At present ich spi driver gets the controller version information via
pch, but this can be simply retrieved via spi node's compatible string.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tested-by: Simon Glass <sjg@chromium.org>
This cleans up the ich spi driver a little bit:
- Remove struct ich_spi_slave that is not referenced anywhere
- Remove ending period in some comments
- Move struct ich_spi_platdata and struct ich_spi_priv to ich.h
- Add #ifndef _ICH_H_ .. in ich.h
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jteki@openedev.com>
In current driver, we always copy 4 bytes to the dest memory.
Actually the dest memory may be shorter than 4 bytes.
Add an argument to indicate the dest memory length.
Avoid writing memory outside of the bounds.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In current driver everytime we memcpy 4 bytes to the dest memory
regardless of the remaining length.
This patch adds checking the remaining length before memcpy.
If the length is shorter than 4 bytes, memcpy the actual length of data
to the dest memory.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch fixes the following compile warning:
drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe':
drivers/spi/fsl_qspi.c:937:15:
warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
^
Just make the cast explicit.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.
In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.
While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.
Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.
This patch includes Bin's fix-up patch from here:
https://patchwork.ozlabs.org/patch/569478/
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The trace is seldom useful for basic debugging. Allow it to be enabled
separately so that it is easier to see the more important init and error
debug messages.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The correct pinctrl is handled automatically so we don't need to do it in
the driver. The exception is when we want to use a different chip select
(other than 0). But this isn't used at present.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present there is an incorrect call to rkspi_enable_chip(). It should
be disabling the chip, not enabling it. Correct this and ensure that the
chip is disabled when releasing the bus.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some devices need delays before and after activiation. Implement these
features in the SPI driver so that we will be able to enable the Chrome
OS EC.
Signed-off-by: Simon Glass <sjg@chromium.org>
Two of the init values are created locally so cannot be out of range.
The masking is unnecessary and in one case is incorrect. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than changing the clock to the same value on every transaction,
remember the last value and don't adjust the clock unless it is necessary.
Signed-off-by: Simon Glass <sjg@chromium.org>
If full pinctrl is enabled we don't need to manually set the pinctrl in the
driver. It will happen automatically. Adjust the code to suit - we will
still use manual mode in SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for
memory-mapped read. This restricts maximum addressable flash size to
16MB.
Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped
read to allow access to addresses above 16MB.
Signed-off-by: Ravi Babu <ravibabu@ti.com>
[vigneshr@ti.com: Re-word commit description]
Signed-off-by: Vignesh R <vigneshr@ti.com>
In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch adds driver model support to the kirkwood SPI driver. Which
is also used on the MVEBU SoC's, now being converted to DM. Non-DM
support is still available for the "older" platforms using this
driver, like kirkwood.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org>
This patch prepares the Kirkwood SPI driver, also used on the MVEBU board
(Armada XP / 38x), for the conversion to driver model.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org>
adopt ti_qspi driver to device driver model
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
spi bus can support dual and quad wire data transfers for tx and
rx. So defining dual and quad modes for both tx and rx. Also add
support to parse bus width used for spi tx and rx transfers.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Changing the ti_qspi_priv structure and its instance names from
to priv for driver mode conversion.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
To enable memory map in dra7xx, specific chip select must be
written to control module register. But this hard coded to chip
select 1, fixing it by writing the specific chip select value to
control module register.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Since spi rx mode macro's are renamed to simple and
meaninfull, this patch will rename the respective
structure members.
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Since SPI_TX_* are spi_slave{} members so use spi protocol
notation instead spi flash programming, like
SPI_TX_BP => SPI_TX_BYTE
SPI_TX_QPP => SPI_TX_QUAD
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Used mode member from spi_slave{} instead of op_mode_tx.
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
This commit fixes the change of below commit
"spi: fsl_qspi: Use GENMASK"
(sha1 :bad490a24212c068c5b718b9189f47ea4075d078)
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
When the Zynq Boot ROM code loads the payload from QSPI it uses the
LQSPI feature of the QSPI device, however it does not clean up its
configuration before handing over to the payload which leaves the device
confgured to by-pass the standard non-linear operating mode.
This ensures the Linear QSPI mode is disabled before re-enabling the
device.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog
timeout might occur meanwhile. So pet the watchdog while operating on
the flash.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add xlnx,xps-spi-2.00.a/b which is compatible string
listed in the Linux kernel.
Remove origin one which has no real background.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Extend compatible list table for cdns,spi-r1p6 compatible string.
Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
SPI_3WIRE is spi mode not spi flags, so this patch fixed
the spi-3wire checking throgh mode instead of flags.
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
spi-3wire is used when SI/SO signals shared so get
the same from dts node and assign to mode on slave
plat->mode.
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jteki@openedev.com>
The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is follow up patch based on
"dm: Add support for all targets which requires MANUAL_RELOC"
(sha1: 484fdf5ba0)
to update function pointers for DM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
Change ioremap() to map_physmem(), as it is more used in u-boot.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>
Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure
bus sync. Without this device's CS is not deactivated reliably leading
to failure to enumerate flash or failure to set quad enable bit on
Macronix flash present on am437x-sk and am437x-idk evms.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
This is the normal Tegra SPI driver modified to work with the
QSPI controller in Tegra210. It does not do 2x/4x transfers
or any other QSPI protocol.
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Ensure the intended SCLK frequency not exceeding the maximum
frequency. If that happen, SCLK will set to maximum frequency.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vikas Manocha <vikas.manocha@st.com>
Cc: Jagannadh Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Fix the fdt read for spi-max-frequency as it's contained
in the child node. Current state of code is always
returning default value.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vikas Manocha <vikas.manocha@st.com>
Cc: Jagannadh Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Ensuring spi_calibration is run when there is a change of sclk
frequency. This will ensure the qspi flash access works for high
sclk frequency
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vikas Manocha <vikas.manocha@st.com>
Cc: Jagannadh Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
- Moved macro definitions to top
- Give tab space to CONFIG_ALTERA_SPI_IDLE_VAL value
- Re-arrange header includes ascending order
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numerical bit shift with BIT macro
in altera_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Marek Vasut <marex@denx.de>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numeric mask hexcodes with GENMASK macro
in xilinx_spi
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numeric mask hexcodes with GENMASK macro
in tegra*.c
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numeric mask hexcodes with GENMASK macro
in fsl_qspi
Cc: York Sun <yorksun@freescale.com>
Cc: Haikun Wang <Haikun.Wang@freescale.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numeric mask hexcodes with GENMASK macro
in designware_spi
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numeric mask hexcodes with GENMASK macro
in atmel_spi
Cc: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numerical bit shift with BIT macro
in xilinx_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numerical bit shift with BIT macro
in ti_qspi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Reviewed-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numerical bit shift with BIT macro
in tegra*.c
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Warren <twarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numerical bit shift with BIT macro
in sh_qspi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numerical bit shift with BIT macro
in omap3_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numerical bit shift with BIT macro
in mpc8xxx_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numerical bit shift with BIT macro
in ich
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numerical bit shift with BIT macro
in fsl_*spi.c
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: York Sun <yorksun@freescale.com>
Cc: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numerical bit shift with BIT macro
in designware_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numerical bit shift with BIT macro
in cadence_qspi_apb
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numerical bit shift with BIT macro
in bfin_spi6xx
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Replace numerical bit shift with BIT macro
in atmel_spi
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
GENMASK macro used on zynq_spi.c and zynq_qspi.c
GENMASK is used to create a contiguous bitmask([hi:lo]).
Ex: (0x7 << 3) => GENMASK(5, 3)
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Used BIT macro on zynq_spi.c and zynq_qspi.c
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
- Use __func__ on debug
- Removed unnecessary comment
- Fix function name in debug as zynq_qspi_xfer instead of spi_xfer
Signed-off-by: Jagan Teki <jteki@openedev.com>
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.
This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Store cs value into private data and use it while activating
chipselect instead of passing through function.
Signed-off-by: Jagan Teki <jteki@openedev.com>
The current name is inconsistent with other driver model data access
functions. Rename it and fix up all users.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Add the Wildcat Point ID so Broadwell U based boards can use SPI.
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.
This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.
Signed-off-by: Jagan Teki <jteki@openedev.com>
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.
This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.
Signed-off-by: Jagan Teki <jteki@openedev.com>
introduce BIT() definition, used in at91_udc gadget
driver.
Signed-off-by: Heiko Schocher <hs@denx.de>
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
Now that we have a new header file for cache-aligned allocation, we should
move the stack-based allocation macro there also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a SPI driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is a convenient way for a driver to get the hardware address of a
device, when regmap or syscon are not being used. Change existing callers
to use it as an example to others.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
ti_qspi uses memory map mode for faster read. Enabling DMA will increase
read speed by 3x @48MHz on DRA74 EVM.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag,
instead of platform.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow
reuse of existing code for ARMv8 based Exynos platforms.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add support for AM43XX to the omap3_spi driver.
Cc: Jagan Teki <jteki@openedev.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagan Teki <jteki@openedev.com>
fdt_addr_t is changed to phys_addr_t. The format in debug should be updated
to %pa to match the type.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Since the timeout is reported through normal channels, and is sometimes
expected (e.g. if the bus is being probed for a non-existent device),
don't display the message in the driver.
In general, drivers should not write to the console as this limits their
usefulness in error conditions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Zynq is using Cadence IP where binding is documented in the Linux kernel
and there is no reason to use different binding.
Synchronize it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Fix below build warnings on armv8,
drivers/spi/fsl_dspi.c: In function ‘fsl_dspi_ofdata_to_platdata’:
drivers/spi/fsl_dspi.c:667:2:
warning: format ‘%x’ expects argument of type ‘unsigned int’,
but argument 2 has type ‘fdt_addr_t’ [-Wformat=]
debug("DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n",
^
lib/fdtdec.c: In function ‘fdtdec_get_addr_size’:
lib/fdtdec.c:105:4:
warning: format ‘%lx’ expects argument of type ‘long unsigned int’,
but argument 3 has type ‘fdt_size_t’ [-Wformat=]
debug("addr=%08lx, size=%08lx\n",
^
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tidy up three minor problems in this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read & half for write once at initialization.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Added TEGRA20_SLINK entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Added TEGRA20_SFLASH entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Added TEGRA114_SPI entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Added ICH_SPI entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Added FSL_QSPI entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Peng Fan <Peng.Fan@freescale.com>
Cc: Haikun Wang <haikun.wang@freescale.com>
DM supported spi drivers are enbled only when DM_SPI enabled,
so added DM_SPI if condition in Kconfig to show thoese only
when it enabled.
Also re-order the config items as incresing alphabetic order.
Signed-off-by: Jagan Teki <jteki@openedev.com>
This patch includes asm/io.h for readl and writel calls.
build errors:
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_probe':
drivers/spi/xilinx_spi.c:119:2: warning: implicit declaration of function 'writel' [-Wimplicit-function-declaration]
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer':
drivers/spi/xilinx_spi.c:193:2: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration]
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Michal Simek <michal.simek@xilinx.com>
This converts the xilinx spi driver to use the driver model.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying "okay" on respective board dts to use
the devicetree generated platdata.
Ex:
&spi1 {
status = "okay";
};
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
This converts the zynq spi driver to use the driver model.
Minimal functional changes like using meaningful name on
structure members wrt mainlined dm spi drivers.
- input_hz -> frequency
- req_hz -> freq
- base -> regs
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Arrange driver code in more readable format[1] for easy accessing
and readable.
[1] http://patchwork.ozlabs.org/patch/265683/
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Rex Chang <rchang@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Move the header code into driver for more readable and
easy to access it.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Rex Chang <rchang@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Move the header code into driver for more readable and
easy to access it.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Zap oc_tiny_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
Zap ftssp010_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Kuo-Jung Su <dantesu@faraday-tech.com>
Cc: Axel Lin <axel.lin@ingics.com>
Zap andes_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Macpaul Lin <macpaul@andestech.com>
Use the oscillator as the source clock when we cannot achieve a low-enough
speed with the peripheral clock. This happens when we request 3MHz on a SPI
clock, for example.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
At present the driver does not properly honour the requested SPI CS
deactivation delay since the SPI bus is changed in the claim_bus() method.
Everything the claim_bus() method does can be done when the device is probed
(setting the speed and mode) and at the start of a new transfer (where the
fifo_status is already cleared). So drop this method.
Also, until the delay is complete, we should not touch the bus, so make sure
that spi_cs_activate() is called before other things are done in the xfer()
method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Only set the speed if it has changed from last time. Since the speed will
be 0 when the device is probed it will always be changed on the first
transfer after the device is probed.
Signed-off-by: Simon Glass <sjg@chromium.org>
The timeout value is never reset during the transfer. This means that when
transferring more data we eventually trigger the timeout.
This was reported on the mailing list:
"Spansion SPI flash read timeout with AM335x"
Signed-off-by: David Dueck <davidcdueck@googlemail.com>
CC: Tom Rini <trini@konsulko.com>
CC: Stefan Roese <sr@denx.de>
CC: Andy Pont <andy.pont@sdcsystems.com>
Tested-by: David Dueck <davidcdueck@googlemail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
These methods should be passed a slave device, not a bus. This matches the
old SPI interface. It is important to know which device is claiming the bus
so passing a bus is not that useful.
Reported-by: Haikun Wang <haikun.wang@freescale.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Removed the unnecessary error check from spi_xfer
as the bitlen zero is possible now to deassert the
chip select for which no data is required to be transfered.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Move the Freescale QSPI driver over to driver model.
Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Tested-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
