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drivers: spi: ti_qspi: convert driver to adopt device driver model
adopt ti_qspi driver to device driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
This commit is contained in:
Mugunthan V N
Jagan Teki
parent
6145ef74f9
commit
106f813907
@ -11,11 +11,14 @@
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#include <asm/arch/omap.h>
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#include <malloc.h>
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#include <spi.h>
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#include <dm.h>
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#include <asm/gpio.h>
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#include <asm/omap_gpio.h>
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#include <asm/omap_common.h>
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#include <asm/ti-common/ti-edma3.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ti qpsi register bit masks */
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#define QSPI_TIMEOUT 2000000
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#define QSPI_FCLK 192000000
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@ -48,12 +51,14 @@
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#define CORE_CTRL_IO 0x4a002558
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#define QSPI_CMD_READ (0x3 << 0)
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#define QSPI_CMD_READ_DUAL (0x6b << 0)
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#define QSPI_CMD_READ_QUAD (0x6b << 0)
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#define QSPI_CMD_READ_FAST (0x0b << 0)
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#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8)
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#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
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#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
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#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
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#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
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#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
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#define QSPI_CMD_WRITE (0x2 << 16)
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#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
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@ -87,7 +92,13 @@ struct ti_qspi_regs {
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/* ti qspi priv */
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struct ti_qspi_priv {
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#ifndef CONFIG_DM_SPI
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struct spi_slave slave;
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#else
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void *memory_map;
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uint max_hz;
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u32 num_cs;
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#endif
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struct ti_qspi_regs *base;
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void *ctrl_mod_mmap;
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unsigned int mode;
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@ -288,6 +299,8 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len)
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}
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#endif
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#ifndef CONFIG_DM_SPI
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static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
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{
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return container_of(slave, struct ti_qspi_priv, slave);
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@ -401,3 +414,177 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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priv->slave.bus, priv->slave.cs, bitlen, flags);
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return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
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}
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#else /* CONFIG_DM_SPI */
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static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
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struct spi_slave *slave,
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bool enable)
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{
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u32 memval;
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u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL);
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if (!enable) {
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writel(0, &priv->base->setup0);
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return;
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}
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memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
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switch (mode) {
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case SPI_RX_QUAD:
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memval |= QSPI_CMD_READ_QUAD;
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memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
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memval |= QSPI_SETUP0_READ_QUAD;
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slave->mode_rx = SPI_RX_QUAD;
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break;
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case SPI_RX_DUAL:
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memval |= QSPI_CMD_READ_DUAL;
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memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
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memval |= QSPI_SETUP0_READ_DUAL;
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break;
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default:
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memval |= QSPI_CMD_READ;
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memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
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memval |= QSPI_SETUP0_READ_NORMAL;
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break;
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}
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writel(memval, &priv->base->setup0);
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}
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static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
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{
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struct ti_qspi_priv *priv = dev_get_priv(bus);
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ti_spi_set_speed(priv, max_hz);
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return 0;
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}
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static int ti_qspi_set_mode(struct udevice *bus, uint mode)
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{
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struct ti_qspi_priv *priv = dev_get_priv(bus);
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return __ti_qspi_set_mode(priv, mode);
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}
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static int ti_qspi_claim_bus(struct udevice *dev)
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{
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struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
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struct spi_slave *slave = dev_get_parent_priv(dev);
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struct ti_qspi_priv *priv;
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struct udevice *bus;
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bus = dev->parent;
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priv = dev_get_priv(bus);
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if (slave_plat->cs > priv->num_cs) {
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debug("invalid qspi chip select\n");
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return -EINVAL;
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}
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__ti_qspi_setup_memorymap(priv, slave, true);
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return __ti_qspi_claim_bus(priv, slave_plat->cs);
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}
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static int ti_qspi_release_bus(struct udevice *dev)
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{
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struct spi_slave *slave = dev_get_parent_priv(dev);
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struct ti_qspi_priv *priv;
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struct udevice *bus;
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bus = dev->parent;
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priv = dev_get_priv(bus);
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__ti_qspi_setup_memorymap(priv, slave, false);
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__ti_qspi_release_bus(priv);
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return 0;
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}
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static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
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struct ti_qspi_priv *priv;
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struct udevice *bus;
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bus = dev->parent;
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priv = dev_get_priv(bus);
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if (slave->cs > priv->num_cs) {
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debug("invalid qspi chip select\n");
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return -EINVAL;
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}
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return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
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}
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static int ti_qspi_probe(struct udevice *bus)
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{
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/* Nothing to do in probe */
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return 0;
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}
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static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
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{
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struct ti_qspi_priv *priv = dev_get_priv(bus);
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const void *blob = gd->fdt_blob;
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int node = bus->of_offset;
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fdt_addr_t addr;
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priv->base = (struct ti_qspi_regs *)dev_get_addr(bus);
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priv->memory_map = (void *)dev_get_addr_index(bus, 1);
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addr = dev_get_addr_index(bus, 2);
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priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;
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priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
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if (priv->max_hz < 0) {
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debug("Error: Max frequency missing\n");
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return -ENODEV;
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}
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priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
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debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
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(int)priv->base, priv->max_hz);
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return 0;
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}
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static int ti_qspi_child_pre_probe(struct udevice *dev)
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{
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struct spi_slave *slave = dev_get_parent_priv(dev);
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struct udevice *bus = dev_get_parent(dev);
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struct ti_qspi_priv *priv = dev_get_priv(bus);
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slave->memory_map = priv->memory_map;
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return 0;
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}
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static const struct dm_spi_ops ti_qspi_ops = {
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.claim_bus = ti_qspi_claim_bus,
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.release_bus = ti_qspi_release_bus,
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.xfer = ti_qspi_xfer,
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.set_speed = ti_qspi_set_speed,
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.set_mode = ti_qspi_set_mode,
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};
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static const struct udevice_id ti_qspi_ids[] = {
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{ .compatible = "ti,dra7xxx-qspi" },
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{ .compatible = "ti,am4372-qspi" },
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{ }
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};
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U_BOOT_DRIVER(ti_qspi) = {
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.name = "ti_qspi",
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.id = UCLASS_SPI,
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.of_match = ti_qspi_ids,
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.ops = &ti_qspi_ops,
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.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
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.probe = ti_qspi_probe,
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.child_pre_probe = ti_qspi_child_pre_probe,
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};
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#endif /* CONFIG_DM_SPI */
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