brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

Merge git://git.denx.de/u-boot-marvell

Browse Source 
- Fix BUILD_TARGET for ARCH_MVEBU from Baruch
- Fix MVEBU PCIe reset issues from Baruch
- Increase DDR stability on x530 from Chris
This commit is contained in:
Tom Rini 2019-02-11 10:35:52 -05:00
commit f49929772c
5 changed files with 14 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Kconfig
View File

@ -227,7 +227,7 @@ config BUILD_ROM
config BUILD_TARGET
string "Build target special images"
default "u-boot-with-spl.sfp" if ARCH_SOCFPGA
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL_BUILD
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI
default "u-boot.kwb" if KIRKWOOD

8
arch/arm/dts/armada-8040-clearfog-gt-8k.dts
View File

@ -99,6 +99,11 @@
0 0 0 0 0 0 0xe 0xe 0xe 0xe
0xe 0xe 0 >;
cpm_pcie_reset_pins: cpm-pcie-reset-pins {
marvell,pins = < 32 >;
marvell,function = <0>;
};
cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
marvell,pins = < 47 >;
marvell,function = <0>;
@ -120,6 +125,9 @@
&cpm_pcie0 {
num-lanes = <1>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_pcie_reset_pins>;
marvell,reset-gpio = <&cpm_gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm/dts/armada-8040-mcbin.dts
View File

@ -132,7 +132,7 @@
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cpm_pcie_reset_pins>;
marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */
marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
status = "okay";
};

2
board/alliedtelesis/x530/x530.c
View File

@ -57,7 +57,7 @@ static struct mv_ddr_topology_map board_topology_map = {
SPEED_BIN_DDR_1866M, /* speed_bin */
MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
MV_DDR_DIE_CAP_4GBIT, /* die capacity */
MV_DDR_FREQ_933, /* frequency */
MV_DDR_FREQ_SAR, /* frequency */
0, 0, /* cas_l cas_wl */
MV_DDR_TEMP_LOW, /* temperature */
MV_DDR_TIM_2T} }, /* timing */

4
drivers/pci/pcie_dw_mvebu.c
View File

@ -489,7 +489,9 @@ static int pcie_dw_mvebu_probe(struct udevice *dev)
* using this GPIO.
*/
if (dm_gpio_is_valid(&reset_gpio)) {
dm_gpio_set_value(&reset_gpio, 1);
dm_gpio_set_value(&reset_gpio, 1); /* assert */
mdelay(200);
dm_gpio_set_value(&reset_gpio, 0); /* de-assert */
mdelay(200);
}
#else