diff --git a/Kconfig b/Kconfig
index 2a48f53256..512c7beb89 100644
--- a/Kconfig
+++ b/Kconfig
@@ -227,7 +227,7 @@ config BUILD_ROM
 config BUILD_TARGET
 	string "Build target special images"
 	default "u-boot-with-spl.sfp" if ARCH_SOCFPGA
-	default "u-boot-spl.kwb" if ARCH_MVEBU && SPL_BUILD
+	default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
 	default "u-boot-elf.srec" if RCAR_GEN3
 	default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI
 	default "u-boot.kwb" if KIRKWOOD
diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
index 498105f25f..cdff44aca5 100644
--- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
@@ -99,6 +99,11 @@
 		     0    0    0    0    0    0    0xe  0xe  0xe  0xe
 		     0xe  0xe  0 >;
 
+	cpm_pcie_reset_pins: cpm-pcie-reset-pins {
+		marvell,pins = < 32 >;
+		marvell,function = <0>;
+	};
+
 	cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
 		marvell,pins = < 47 >;
 		marvell,function = <0>;
@@ -120,6 +125,9 @@
 
 &cpm_pcie0 {
 	num-lanes = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_pcie_reset_pins>;
+	marvell,reset-gpio = <&cpm_gpio1 0 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index 7e8e2f707c..5a046d9de4 100644
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -132,7 +132,7 @@
 	num-lanes = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&cpm_pcie_reset_pins>;
-	marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */
+	marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
 	status = "okay";
 };
 
diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c
index b34ae51345..d7d1942fe6 100644
--- a/board/alliedtelesis/x530/x530.c
+++ b/board/alliedtelesis/x530/x530.c
@@ -57,7 +57,7 @@ static struct mv_ddr_topology_map board_topology_map = {
 	    SPEED_BIN_DDR_1866M,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_16BIT,	/* sdram device width */
 	    MV_DDR_DIE_CAP_4GBIT,	/* die capacity */
-	    MV_DDR_FREQ_933,		/* frequency */
+	    MV_DDR_FREQ_SAR,		/* frequency */
 	    0, 0,			/* cas_l cas_wl */
 	    MV_DDR_TEMP_LOW,		/* temperature */
 	    MV_DDR_TIM_2T} },		/* timing */
diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index 8081005c27..95fb41966f 100644
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -489,7 +489,9 @@ static int pcie_dw_mvebu_probe(struct udevice *dev)
 	 * using this GPIO.
 	 */
 	if (dm_gpio_is_valid(&reset_gpio)) {
-		dm_gpio_set_value(&reset_gpio, 1);
+		dm_gpio_set_value(&reset_gpio, 1); /* assert */
+		mdelay(200);
+		dm_gpio_set_value(&reset_gpio, 0); /* de-assert */
 		mdelay(200);
 	}
 #else