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eth: mtk-eth: enable mt7629 sgmii mode support in mediatek eth driver
The sgmii mode init flow is almost the same for all mediatek SoC, the only difference is the register offset(SGMSYS_GEN2_SPEED) is 0x2028 in the old chip(mt7622) but changed to 0x128 for the newer chip(mt7629 and the following chips). Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
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@ -1094,7 +1094,8 @@ static int mtk_phy_probe(struct udevice *dev)
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static void mtk_sgmii_init(struct mtk_eth_priv *priv)
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static void mtk_sgmii_init(struct mtk_eth_priv *priv)
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{
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{
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/* Set SGMII GEN2 speed(2.5G) */
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/* Set SGMII GEN2 speed(2.5G) */
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clrsetbits_le32(priv->sgmii_base + SGMSYS_GEN2_SPEED,
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clrsetbits_le32(priv->sgmii_base + ((priv->soc == SOC_MT7622) ?
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SGMSYS_GEN2_SPEED : SGMSYS_GEN2_SPEED_V2),
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SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
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SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
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/* Disable SGMII AN */
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/* Disable SGMII AN */
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@ -46,6 +46,7 @@
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#define SGMII_PHYA_PWD BIT(4)
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#define SGMII_PHYA_PWD BIT(4)
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#define SGMSYS_GEN2_SPEED 0x2028
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#define SGMSYS_GEN2_SPEED 0x2028
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#define SGMSYS_GEN2_SPEED_V2 0x128
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#define SGMSYS_SPEED_2500 BIT(2)
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#define SGMSYS_SPEED_2500 BIT(2)
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/* Frame Engine Registers */
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/* Frame Engine Registers */
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