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Merge https://source.denx.de/u-boot/custodians/u-boot-sh 

- Various clk/pinctrl updates to re-sync with Linux and other fixes
This commit is contained in:
Tom Rini 2021-05-23 10:15:15 -04:00
parent a4262e5506 6fc323c1ae
commit eb53b943be
25 changed files with 448 additions and 373 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/clk/renesas/clk-rcar-gen2.c
View File

@ -23,8 +23,6 @@
#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"
#define CPG_RST_MODEMR 0x0060
#define CPG_PLL0CR 0x00d8
#define CPG_SDCKCR 0x0074
@ -63,14 +61,14 @@ static int gen2_clk_enable(struct clk *clk)
{
struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
return renesas_clk_endisable(clk, priv->base, true);
return renesas_clk_endisable(clk, priv->base, priv->info, true);
}
static int gen2_clk_disable(struct clk *clk)
{
struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
return renesas_clk_endisable(clk, priv->base, false);
return renesas_clk_endisable(clk, priv->base, priv->info, false);
}
static ulong gen2_clk_get_rate(struct clk *clk)

120
drivers/clk/renesas/clk-rcar-gen3.c
View File

@ -25,8 +25,6 @@
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
#define CPG_RST_MODEMR 0x0060
#define CPG_PLL0CR 0x00d8
#define CPG_PLL2CR 0x002c
#define CPG_PLL4CR 0x01f4
@ -145,14 +143,38 @@ static int gen3_clk_enable(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
return renesas_clk_endisable(clk, priv->base, true);
return renesas_clk_endisable(clk, priv->base, priv->info, true);
}
static int gen3_clk_disable(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
return renesas_clk_endisable(clk, priv->base, false);
return renesas_clk_endisable(clk, priv->base, priv->info, false);
}
static u64 gen3_clk_get_rate64(struct clk *clk);
static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv,
struct clk *parent,
const struct cpg_core_clk *core,
u32 mul_reg, u32 mult, u32 div,
char *name)
{
u32 value;
u64 rate;
if (mul_reg) {
value = readl(priv->base + mul_reg);
mult = (((value >> 24) & 0x7f) + 1) * 2;
div = 1;
}
rate = (gen3_clk_get_rate64(parent) * mult) / div;
debug("%s[%i] %s clk: parent=%i mult=%u div=%u => rate=%llu\n",
__func__, __LINE__, name, core->parent, mult, div, rate);
return rate;
}
static u64 gen3_clk_get_rate64(struct clk *clk)
@ -163,7 +185,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
const struct cpg_core_clk *core;
const struct rcar_gen3_cpg_pll_config *pll_config =
priv->cpg_pll_config;
u32 value, mult, div, prediv, postdiv;
u32 value, div, prediv, postdiv;
u64 rate = 0;
int i, ret;
@ -205,60 +227,36 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
return -EINVAL;
case CLK_TYPE_GEN3_MAIN:
rate = gen3_clk_get_rate64(&parent) / pll_config->extal_div;
debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%llu\n",
__func__, __LINE__,
core->parent, pll_config->extal_div, rate);
return rate;
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
0, 1, pll_config->extal_div,
"MAIN");
case CLK_TYPE_GEN3_PLL0:
value = readl(priv->base + CPG_PLL0CR);
mult = (((value >> 24) & 0x7f) + 1) * 2;
rate = gen3_clk_get_rate64(&parent) * mult;
debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%llu\n",
__func__, __LINE__, core->parent, mult, rate);
return rate;
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
CPG_PLL0CR, 0, 0, "PLL0");
case CLK_TYPE_GEN3_PLL1:
rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult;
rate /= pll_config->pll1_div;
debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n",
__func__, __LINE__,
core->parent, pll_config->pll1_mult,
pll_config->pll1_div, rate);
return rate;
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
0, pll_config->pll1_mult,
pll_config->pll1_div, "PLL1");
case CLK_TYPE_GEN3_PLL2:
value = readl(priv->base + CPG_PLL2CR);
mult = (((value >> 24) & 0x7f) + 1) * 2;
rate = gen3_clk_get_rate64(&parent) * mult;
debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%llu\n",
__func__, __LINE__, core->parent, mult, rate);
return rate;
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
CPG_PLL2CR, 0, 0, "PLL2");
case CLK_TYPE_GEN3_PLL3:
rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult;
rate /= pll_config->pll3_div;
debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n",
__func__, __LINE__,
core->parent, pll_config->pll3_mult,
pll_config->pll3_div, rate);
return rate;
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
0, pll_config->pll3_mult,
pll_config->pll3_div, "PLL3");
case CLK_TYPE_GEN3_PLL4:
value = readl(priv->base + CPG_PLL4CR);
mult = (((value >> 24) & 0x7f) + 1) * 2;
rate = gen3_clk_get_rate64(&parent) * mult;
debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%llu\n",
__func__, __LINE__, core->parent, mult, rate);
return rate;
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
CPG_PLL4CR, 0, 0, "PLL4");
case CLK_TYPE_FF:
rate = (gen3_clk_get_rate64(&parent) * core->mult) / core->div;
debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%llu\n",
__func__, __LINE__,
core->parent, core->mult, core->div, rate);
return rate;
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
0, core->mult, core->div,
"FIXED");
case CLK_TYPE_GEN3_MDSEL:
div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
@ -289,6 +287,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
return -EINVAL;
case CLK_TYPE_GEN3_RPC:
case CLK_TYPE_GEN3_RPCD2:
rate = gen3_clk_get_rate64(&parent);
value = readl(priv->base + core->offset);
@ -304,11 +303,19 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
CPG_RPC_POSTDIV_MASK;
rate /= postdiv + 1;
debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",
__func__, __LINE__,
core->parent, prediv, postdiv, rate);
if (postdiv % 2 != 0) {
rate /= postdiv + 1;
if (core->type == CLK_TYPE_GEN3_RPCD2)
rate /= 2;
debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",
__func__, __LINE__,
core->parent, prediv, postdiv, rate);
return rate;
}
return -EINVAL;
@ -373,7 +380,7 @@ int gen3_clk_probe(struct udevice *dev)
if (rst_base == FDT_ADDR_T_NONE)
return -EINVAL;
cpg_mode = readl(rst_base + CPG_RST_MODEMR);
cpg_mode = readl(rst_base + info->reset_modemr_offset);
priv->cpg_pll_config =
(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
@ -382,6 +389,15 @@ int gen3_clk_probe(struct udevice *dev)
priv->sscg = !(cpg_mode & BIT(12));
if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
priv->info->status_regs = mstpsr;
priv->info->control_regs = smstpcr;
priv->info->reset_regs = srcr;
priv->info->reset_clear_regs = srstclr;
} else {
return -EINVAL;
}
ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
if (ret < 0)
return ret;

15
drivers/clk/renesas/r8a774a1-cpg-mssr.c
View File

@ -68,13 +68,18 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A774A1_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */
DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@ -99,7 +104,6 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = {
DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
DEF_GEN3_RPC("rpc", R8A774A1_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1),
@ -203,7 +207,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] = {
DEF_MOD("can-fd", 914, R8A774A1_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4),
DEF_MOD("rpc", 917, R8A774A1_CLK_RPC),
DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
@ -317,6 +321,7 @@ static const struct cpg_mssr_info r8a774a1_cpg_mssr_info = {
.mstp_table = r8a774a1_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a774a1_mstp_table),
.reset_node = "renesas,r8a774a1-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,

9
drivers/clk/renesas/r8a774b1-cpg-mssr.c
View File

@ -39,6 +39,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
@ -64,6 +65,12 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A774B1_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
@ -195,6 +202,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] = {
DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4),
DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
@ -310,6 +318,7 @@ static const struct cpg_mssr_info r8a774b1_cpg_mssr_info = {
.mstp_table = r8a774b1_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a774b1_mstp_table),
.reset_node = "renesas,r8a774b1-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,

10
drivers/clk/renesas/r8a774c0-cpg-mssr.c
View File

@ -44,6 +44,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_RPCSRC,
CLK_RINT,
CLK_OCO,
@ -74,6 +75,13 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = {
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A774C0_CLK_RPC),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
@ -199,6 +207,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] = {
DEF_MOD("can-fd", 914, R8A774C0_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4),
DEF_MOD("rpc-if", 917, R8A774C0_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
@ -283,6 +292,7 @@ const struct cpg_mssr_info r8a774c0_cpg_mssr_info = {
.mstp_table = r8a774c0_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a774c0_mstp_table),
.reset_node = "renesas,r8a774c0-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = ~0,

1
drivers/clk/renesas/r8a774e1-cpg-mssr.c
View File

@ -332,6 +332,7 @@ static const struct cpg_mssr_info r8a774e1_cpg_mssr_info = {
.mstp_table = r8a774e1_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a774e1_mstp_table),
.reset_node = "renesas,r8a774e1-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,

5
drivers/clk/renesas/r8a7790-cpg-mssr.c
View File

@ -108,8 +108,8 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] = {
DEF_MOD("tmu0", 125, R8A7790_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7790_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7790_CLK_ZS),
DEF_MOD("vsp1-rt", 130, R8A7790_CLK_ZS),
DEF_MOD("vsp1-sy", 131, R8A7790_CLK_ZS),
DEF_MOD("vspr", 130, R8A7790_CLK_ZS),
DEF_MOD("vsps", 131, R8A7790_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7790_CLK_MP),
DEF_MOD("scifa1", 203, R8A7790_CLK_MP),
DEF_MOD("scifa0", 204, R8A7790_CLK_MP),
@ -263,6 +263,7 @@ static const struct cpg_mssr_info r8a7790_cpg_mssr_info = {
.mstp_table = r8a7790_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a7790_mstp_table),
.reset_node = "renesas,r8a7790-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.extal_usb_node = "usb_extal",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,

3
drivers/clk/renesas/r8a7791-cpg-mssr.c
View File

@ -106,7 +106,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] = {
DEF_MOD("tmu0", 125, R8A7791_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS),
DEF_MOD("vsp1-sy", 131, R8A7791_CLK_ZS),
DEF_MOD("vsps", 131, R8A7791_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7791_CLK_MP),
DEF_MOD("scifa1", 203, R8A7791_CLK_MP),
DEF_MOD("scifa0", 204, R8A7791_CLK_MP),
@ -265,6 +265,7 @@ static const struct cpg_mssr_info r8a7791_cpg_mssr_info = {
.mstp_table = r8a7791_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a7791_mstp_table),
.reset_node = "renesas,r8a7791-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.extal_usb_node = "usb_extal",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,

3
drivers/clk/renesas/r8a7792-cpg-mssr.c
View File

@ -88,7 +88,7 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] = {
DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS),
DEF_MOD("vsp1-sy", 131, R8A7792_CLK_ZS),
DEF_MOD("vsps", 131, R8A7792_CLK_ZS),
DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS),
DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS),
@ -213,6 +213,7 @@ static const struct cpg_mssr_info r8a7792_cpg_mssr_info = {
.mstp_table = r8a7792_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a7792_mstp_table),
.reset_node = "renesas,r8a7792-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.pll0_div = 2,

3
drivers/clk/renesas/r8a7794-cpg-mssr.c
View File

@ -97,7 +97,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] = {
DEF_MOD("cmt0", 124, R8A7794_CLK_R),
DEF_MOD("tmu0", 125, R8A7794_CLK_CP),
DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS),
DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS),
DEF_MOD("vsps", 131, R8A7794_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7794_CLK_MP),
DEF_MOD("scifa1", 203, R8A7794_CLK_MP),
DEF_MOD("scifa0", 204, R8A7794_CLK_MP),
@ -240,6 +240,7 @@ static const struct cpg_mssr_info r8a7794_cpg_mssr_info = {
.mstp_table = r8a7794_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a7794_mstp_table),
.reset_node = "renesas,r8a7794-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.extal_usb_node = "usb_extal",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,

59
drivers/clk/renesas/r8a7795-cpg-mssr.c
View File

@ -41,8 +41,8 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_RPCSRC,
CLK_SSPSRC,
CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
@ -69,13 +69,18 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A7795_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */
DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@ -102,8 +107,6 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
@ -132,14 +135,15 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
DEF_MOD("cmt3", 300, R8A7795_CLK_R),
DEF_MOD("cmt2", 301, R8A7795_CLK_R),
DEF_MOD("cmt1", 302, R8A7795_CLK_R),
DEF_MOD("cmt0", 303, R8A7795_CLK_R),
DEF_MOD("tpu0", 304, R8A7795_CLK_S3D4),
DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
@ -156,16 +160,16 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("rwdt", 402, R8A7795_CLK_R),
DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2),
DEF_MOD("drif31", 508, R8A7795_CLK_S3D2),
DEF_MOD("drif30", 509, R8A7795_CLK_S3D2),
DEF_MOD("drif21", 510, R8A7795_CLK_S3D2),
DEF_MOD("drif20", 511, R8A7795_CLK_S3D2),
DEF_MOD("drif11", 512, R8A7795_CLK_S3D2),
DEF_MOD("drif10", 513, R8A7795_CLK_S3D2),
DEF_MOD("drif01", 514, R8A7795_CLK_S3D2),
DEF_MOD("drif00", 515, R8A7795_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
@ -197,12 +201,16 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4),
DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2),
DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2),
DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2),
DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2),
DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2),
DEF_MOD("cmm3", 708, R8A7795_CLK_S2D1),
DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1),
DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1),
DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1),
DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
@ -239,7 +247,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
DEF_MOD("rpc", 917, R8A7795_CLK_RPC),
DEF_MOD("rpc-if", 917, R8A7795_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
@ -354,6 +362,7 @@ static const struct cpg_mssr_info r8a7795_cpg_mssr_info = {
.mstp_table = r8a7795_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a7795_mstp_table),
.reset_node = "renesas,r8a7795-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,

59
drivers/clk/renesas/r8a7796-cpg-mssr.c
View File

@ -47,8 +47,8 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_RPCSRC,
CLK_SSPSRC,
CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
@ -75,13 +75,18 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A7796_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */
DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@ -108,9 +113,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1),
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A7796_CLK_CPEX, CLK_EXTAL, 2, 1),
@ -126,6 +130,11 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A7796_CLK_S3D2),
DEF_MOD("tmu1", 124, R8A7796_CLK_S3D2),
DEF_MOD("tmu0", 125, R8A7796_CLK_CP),
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
@ -135,13 +144,15 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3),
DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3),
DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S3D1),
DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
DEF_MOD("sceg-pub", 229, R8A7796_CLK_CR),
DEF_MOD("cmt3", 300, R8A7796_CLK_R),
DEF_MOD("cmt2", 301, R8A7796_CLK_R),
DEF_MOD("cmt1", 302, R8A7796_CLK_R),
DEF_MOD("cmt0", 303, R8A7796_CLK_R),
DEF_MOD("tpu0", 304, R8A7796_CLK_S3D4),
DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
DEF_MOD("sdif3", 311, R8A7796_CLK_SD3),
DEF_MOD("sdif2", 312, R8A7796_CLK_SD2),
@ -155,16 +166,16 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("rwdt", 402, R8A7796_CLK_R),
DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
DEF_MOD("drif4", 511, R8A7796_CLK_S3D2),
DEF_MOD("drif3", 512, R8A7796_CLK_S3D2),
DEF_MOD("drif2", 513, R8A7796_CLK_S3D2),
DEF_MOD("drif1", 514, R8A7796_CLK_S3D2),
DEF_MOD("drif0", 515, R8A7796_CLK_S3D2),
DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2),
DEF_MOD("drif31", 508, R8A7796_CLK_S3D2),
DEF_MOD("drif30", 509, R8A7796_CLK_S3D2),
DEF_MOD("drif21", 510, R8A7796_CLK_S3D2),
DEF_MOD("drif20", 511, R8A7796_CLK_S3D2),
DEF_MOD("drif11", 512, R8A7796_CLK_S3D2),
DEF_MOD("drif10", 513, R8A7796_CLK_S3D2),
DEF_MOD("drif01", 514, R8A7796_CLK_S3D2),
DEF_MOD("drif00", 515, R8A7796_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
@ -185,9 +196,12 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2),
DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A7796_CLK_S3D2),
DEF_MOD("cmm2", 709, R8A7796_CLK_S2D1),
DEF_MOD("cmm1", 710, R8A7796_CLK_S2D1),
DEF_MOD("cmm0", 711, R8A7796_CLK_S2D1),
DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
@ -217,7 +231,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
DEF_MOD("rpc", 917, R8A7796_CLK_RPC),
DEF_MOD("rpc-if", 917, R8A7796_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
@ -332,6 +346,7 @@ static const struct cpg_mssr_info r8a7796_cpg_mssr_info = {
.mstp_table = r8a7796_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table),
.reset_node = "renesas,r8a7796-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,

59
drivers/clk/renesas/r8a77965-cpg-mssr.c
View File

@ -41,8 +41,8 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_RPCSRC,
CLK_SSPSRC,
CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
@ -68,12 +68,17 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A77965_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */
DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@ -100,9 +105,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
DEF_GEN3_RPC("rpc", R8A77965_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1),
DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77965_CLK_CPEX, CLK_EXTAL, 2, 1),
@ -118,6 +122,11 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
static const struct mssr_mod_clk r8a77965_mod_clks[] = {
DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A77965_CLK_S3D2),
DEF_MOD("tmu1", 124, R8A77965_CLK_S3D2),
DEF_MOD("tmu0", 125, R8A77965_CLK_CP),
DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
@ -127,14 +136,16 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
DEF_MOD("msiof2", 209, R8A77965_CLK_MSO),
DEF_MOD("msiof1", 210, R8A77965_CLK_MSO),
DEF_MOD("msiof0", 211, R8A77965_CLK_MSO),
DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3),
DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3),
DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
DEF_MOD("sceg-pub", 229, R8A77965_CLK_CR),
DEF_MOD("cmt3", 300, R8A77965_CLK_R),
DEF_MOD("cmt2", 301, R8A77965_CLK_R),
DEF_MOD("cmt1", 302, R8A77965_CLK_R),
DEF_MOD("cmt0", 303, R8A77965_CLK_R),
DEF_MOD("tpu0", 304, R8A77965_CLK_S3D4),
DEF_MOD("scif2", 310, R8A77965_CLK_S3D4),
DEF_MOD("sdif3", 311, R8A77965_CLK_SD3),
DEF_MOD("sdif2", 312, R8A77965_CLK_SD2),
@ -150,16 +161,16 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3),
DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3),
DEF_MOD("drif7", 508, R8A77965_CLK_S3D2),
DEF_MOD("drif6", 509, R8A77965_CLK_S3D2),
DEF_MOD("drif5", 510, R8A77965_CLK_S3D2),
DEF_MOD("drif4", 511, R8A77965_CLK_S3D2),
DEF_MOD("drif3", 512, R8A77965_CLK_S3D2),
DEF_MOD("drif2", 513, R8A77965_CLK_S3D2),
DEF_MOD("drif1", 514, R8A77965_CLK_S3D2),
DEF_MOD("drif0", 515, R8A77965_CLK_S3D2),
DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2),
DEF_MOD("drif31", 508, R8A77965_CLK_S3D2),
DEF_MOD("drif30", 509, R8A77965_CLK_S3D2),
DEF_MOD("drif21", 510, R8A77965_CLK_S3D2),
DEF_MOD("drif20", 511, R8A77965_CLK_S3D2),
DEF_MOD("drif11", 512, R8A77965_CLK_S3D2),
DEF_MOD("drif10", 513, R8A77965_CLK_S3D2),
DEF_MOD("drif01", 514, R8A77965_CLK_S3D2),
DEF_MOD("drif00", 515, R8A77965_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1),
@ -179,9 +190,12 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
DEF_MOD("vspb", 626, R8A77965_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1),
DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4),
DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4),
DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4),
DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2),
DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A77965_CLK_S3D2),
DEF_MOD("cmm3", 708, R8A77965_CLK_S2D1),
DEF_MOD("cmm1", 710, R8A77965_CLK_S2D1),
DEF_MOD("cmm0", 711, R8A77965_CLK_S2D1),
DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
DEF_MOD("du3", 721, R8A77965_CLK_S2D1),
@ -214,7 +228,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4),
DEF_MOD("rpc", 917, R8A77965_CLK_RPC),
DEF_MOD("rpc-if", 917, R8A77965_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP),
@ -330,6 +344,7 @@ static const struct cpg_mssr_info r8a77965_cpg_mssr_info = {
.mstp_table = r8a77965_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a77965_mstp_table),
.reset_node = "renesas,r8a77965-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,

123
drivers/clk/renesas/r8a77970-cpg-mssr.c
View File

@ -20,6 +20,13 @@
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
#define CPG_SD0CKCR 0x0074
enum r8a77970_clk_types {
CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
CLK_TYPE_R8A77970_SD0,
};
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
@ -32,24 +39,9 @@ enum clk_ids {
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
CLK_PLL2,
CLK_PLL3,
CLK_PLL4,
CLK_PLL1_DIV2,
CLK_PLL1_DIV4,
CLK_PLL0D2,
CLK_PLL0D3,
CLK_PLL0D5,
CLK_PLL1D2,
CLK_PE,
CLK_S0,
CLK_S1,
CLK_S2,
CLK_S3,
CLK_SDSRC,
CLK_RPCSRC,
CLK_SSPSRC,
CLK_RINT,
/* Module Clocks */
MOD_CLK_BASE
@ -57,67 +49,80 @@ enum clk_ids {
static const struct cpg_core_clk r8a77970_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
/* Core Clock Outputs */
DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1),
DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1),
DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1),
DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1),
DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1),
DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1),
DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_PLL1_DIV2, 8, 1),
DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_PLL1_DIV2, 16, 1),
DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074),
DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
CLK_PLL1_DIV2),
DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_FIXED("rpc", R8A77970_CLK_RPC, CLK_PLL1_DIV2, 5, 1),
DEF_FIXED("rpcd2", R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1),
DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77970_CLK_CPEX, CLK_EXTAL, 2, 1),
/* NOTE: HDMI, CSI, CAN etc. clock are missing */
DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014),
DEF_DIV6P1("csi0", R8A77970_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
DEF_FIXED("osc", R8A77970_CLK_OSC, CLK_PLL1_DIV2, 12*1024, 1),
DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1),
};
static const struct mssr_mod_clk r8a77970_mod_clks[] = {
DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
DEF_MOD("tmu1", 124, R8A77970_CLK_S2D2),
DEF_MOD("tmu0", 125, R8A77970_CLK_CP),
DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
DEF_MOD("scif4", 203, R8A77970_CLK_S2D4),
DEF_MOD("scif3", 204, R8A77970_CLK_S2D4),
DEF_MOD("scif1", 206, R8A77970_CLK_S2D4),
DEF_MOD("scif0", 207, R8A77970_CLK_S2D4),
DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */
DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
DEF_MOD("sdif", 314, R8A77970_CLK_SD0),
DEF_MOD("rwdt0", 402, R8A77970_CLK_R),
DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
DEF_MOD("cmt3", 300, R8A77970_CLK_R),
DEF_MOD("cmt2", 301, R8A77970_CLK_R),
DEF_MOD("cmt1", 302, R8A77970_CLK_R),
DEF_MOD("cmt0", 303, R8A77970_CLK_R),
DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4),
DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
DEF_MOD("rwdt", 402, R8A77970_CLK_R),
DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1),
DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1),
DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1),
DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1),
DEF_MOD("thermal", 522, R8A77970_CLK_CP),
DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
@ -130,7 +135,6 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] = {
DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
DEF_MOD("isp", 817, R8A77970_CLK_S2D1),
DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
@ -138,7 +142,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] = {
DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
DEF_MOD("rpc", 917, R8A77970_CLK_RPC),
DEF_MOD("rpc-if", 917, R8A77970_CLK_RPC),
DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
@ -207,6 +211,7 @@ static const struct cpg_mssr_info r8a77970_cpg_mssr_info = {
.mstp_table = r8a77970_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table),
.reset_node = "renesas,r8a77970-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,

1
drivers/clk/renesas/r8a77980-cpg-mssr.c
View File

@ -230,6 +230,7 @@ static const struct cpg_mssr_info r8a77980_cpg_mssr_info = {
.mstp_table = r8a77980_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a77980_mstp_table),
.reset_node = "renesas,r8a77980-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,

43
drivers/clk/renesas/r8a77990-cpg-mssr.c
View File

@ -74,7 +74,13 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A77990_CLK_RPC),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
@ -83,6 +89,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
/* Core Clock Outputs */
DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8),
DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1),
DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1),
@ -105,9 +112,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078),
DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
DEF_GEN3_RPC("rpc", R8A77990_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1),
DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
@ -126,6 +132,11 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
};
static const struct mssr_mod_clk r8a77990_mod_clks[] = {
DEF_MOD("tmu4", 121, R8A77990_CLK_S0D6C),
DEF_MOD("tmu3", 122, R8A77990_CLK_S3D2C),
DEF_MOD("tmu2", 123, R8A77990_CLK_S3D2C),
DEF_MOD("tmu1", 124, R8A77990_CLK_S3D2C),
DEF_MOD("tmu0", 125, R8A77990_CLK_CP),
DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C),
DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C),
DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C),
@ -138,6 +149,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
DEF_MOD("sceg-pub", 229, R8A77990_CLK_CR),
DEF_MOD("cmt3", 300, R8A77990_CLK_R),
DEF_MOD("cmt2", 301, R8A77990_CLK_R),
@ -156,15 +168,15 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
DEF_MOD("intc-ex", 407, R8A77990_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4),
DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
DEF_MOD("drif4", 511, R8A77990_CLK_S3D2),
DEF_MOD("drif3", 512, R8A77990_CLK_S3D2),
DEF_MOD("drif2", 513, R8A77990_CLK_S3D2),
DEF_MOD("drif1", 514, R8A77990_CLK_S3D2),
DEF_MOD("drif0", 515, R8A77990_CLK_S3D2),
DEF_MOD("audmac0", 502, R8A77990_CLK_S1D2),
DEF_MOD("drif31", 508, R8A77990_CLK_S3D2),
DEF_MOD("drif30", 509, R8A77990_CLK_S3D2),
DEF_MOD("drif21", 510, R8A77990_CLK_S3D2),
DEF_MOD("drif20", 511, R8A77990_CLK_S3D2),
DEF_MOD("drif11", 512, R8A77990_CLK_S3D2),
DEF_MOD("drif10", 513, R8A77990_CLK_S3D2),
DEF_MOD("drif01", 514, R8A77990_CLK_S3D2),
DEF_MOD("drif00", 515, R8A77990_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C),
DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C),
DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C),
@ -184,8 +196,10 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
DEF_MOD("vspb", 626, R8A77990_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
DEF_MOD("ehci0", 703, R8A77990_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A77990_CLK_S3D2),
DEF_MOD("cmm1", 710, R8A77990_CLK_S1D1),
DEF_MOD("cmm0", 711, R8A77990_CLK_S1D1),
DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
@ -290,6 +304,7 @@ static const struct cpg_mssr_info r8a77990_cpg_mssr_info = {
.mstp_table = r8a77990_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a77990_mstp_table),
.reset_node = "renesas,r8a77990-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = ~0,

22
drivers/clk/renesas/r8a77995-cpg-mssr.c
View File

@ -70,7 +70,13 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC,
CLK_RPCSRC),
DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
R8A77995_CLK_RPC),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
@ -93,13 +99,12 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("cr", R8A77995_CLK_CR, CLK_PLL1D2, 2, 1),
DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
DEF_GEN3_RPC("rpc", R8A77995_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
@ -114,6 +119,11 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
};
static const struct mssr_mod_clk r8a77995_mod_clks[] = {
DEF_MOD("tmu4", 121, R8A77995_CLK_S1D4C),
DEF_MOD("tmu3", 122, R8A77995_CLK_S3D2C),
DEF_MOD("tmu2", 123, R8A77995_CLK_S3D2C),
DEF_MOD("tmu1", 124, R8A77995_CLK_S3D2C),
DEF_MOD("tmu0", 125, R8A77995_CLK_CP),
DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
@ -126,6 +136,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
DEF_MOD("cmt3", 300, R8A77995_CLK_R),
DEF_MOD("cmt2", 301, R8A77995_CLK_R),
DEF_MOD("cmt1", 302, R8A77995_CLK_R),
@ -137,7 +148,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
DEF_MOD("rwdt", 402, R8A77995_CLK_R),
DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
DEF_MOD("audmac0", 502, R8A77995_CLK_S1D2),
DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
DEF_MOD("thermal", 522, R8A77995_CLK_CP),
@ -150,6 +161,8 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
DEF_MOD("cmm1", 710, R8A77995_CLK_S1D1),
DEF_MOD("cmm0", 711, R8A77995_CLK_S1D1),
DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
@ -229,6 +242,7 @@ static const struct cpg_mssr_info r8a77995_cpg_mssr_info = {
.mstp_table = r8a77995_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a77995_mstp_table),
.reset_node = "renesas,r8a77995-rst",
.reset_modemr_offset = CPG_RST_MODEMR,
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = ~0,

7
drivers/clk/renesas/rcar-gen2-cpg.h
View File

@ -1,11 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* R-Car Gen2 Clock Pulse Generator
*
* Copyright (C) 2016 Cogent Embedded Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation; version 2 of the License.
*/
#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
@ -33,6 +30,8 @@ struct rcar_gen2_cpg_pll_config {
unsigned int pll0_mult; /* leave as zero if PLL0CR exists */
};
#define CPG_RST_MODEMR 0x060
struct gen2_clk_priv {
void __iomem *base;
struct cpg_mssr_info *info;

19
drivers/clk/renesas/rcar-gen3-cpg.h
View File

@ -1,11 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* R-Car Gen3 Clock Pulse Generator
*
* Copyright (C) 2015-2016 Glider bvba
* Copyright (C) 2015-2018 Glider bvba
* Copyright (C) 2018 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
@ -22,10 +21,10 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_R,
CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
CLK_TYPE_GEN3_Z,
CLK_TYPE_GEN3_Z2,
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
CLK_TYPE_GEN3_RPCSRC,
CLK_TYPE_GEN3_E3_RPCSRC,
CLK_TYPE_GEN3_RPC,
CLK_TYPE_GEN3_RPCD2,
@ -36,8 +35,8 @@ enum rcar_gen3_clk_types {
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
#define DEF_GEN3_RPCD2(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPCD2, _parent, .offset = _offset)
#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
@ -59,6 +58,10 @@ enum rcar_gen3_clk_types {
#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
#define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
(_parent0) << 16 | (_parent1), .div = 8)
struct rcar_gen3_cpg_pll_config {
u8 extal_div;
u8 pll1_mult;
@ -68,6 +71,8 @@ struct rcar_gen3_cpg_pll_config {
u8 osc_prediv;
};
#define CPG_RST_MODEMR 0x060
#define CPG_RPCCKCR 0x238
#define CPG_RCKCR 0x240

52
drivers/clk/renesas/renesas-cpg-mssr.c
View File

@ -22,47 +22,6 @@
#include "renesas-cpg-mssr.h"
/*
* Module Standby and Software Reset register offets.
*
* If the registers exist, these are valid for SH-Mobile, R-Mobile,
* R-Car Gen2, R-Car Gen3, and RZ/G1.
* These are NOT valid for R-Car Gen1 and RZ/A1!
*/
/*
* Module Stop Status Register offsets
*/
static const u16 mstpsr[] = {
0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
0x9A0, 0x9A4, 0x9A8, 0x9AC,
};
#define MSTPSR(i) mstpsr[i]
/*
* System Module Stop Control Register offsets
*/
static const u16 smstpcr[] = {
0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
0x990, 0x994, 0x998, 0x99C,
};
#define SMSTPCR(i) smstpcr[i]
/* Realtime Module Stop Control Register offsets */
#define RMSTPCR(i) (smstpcr[i] - 0x20)
/* Modem Module Stop Control Register offsets (r8a73a4) */
#define MMSTPCR(i) (smstpcr[i] + 0x20)
/* Software Reset Clearing Register offsets */
#define SRSTCLR(i) (0x940 + (i) * 4)
bool renesas_clk_is_mod(struct clk *clk)
{
return (clk->id >> 16) == CPG_MOD;
@ -132,7 +91,8 @@ int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
return 0;
}
int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable)
int renesas_clk_endisable(struct clk *clk, void __iomem *base,
struct cpg_mssr_info *info, bool enable)
{
const unsigned long clkid = clk->id & 0xffff;
const unsigned int reg = clkid / 100;
@ -146,11 +106,11 @@ int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable)
clkid, reg, bit, enable ? "ON" : "OFF");
if (enable) {
clrbits_le32(base + SMSTPCR(reg), bitmask);
return wait_for_bit_le32(base + MSTPSR(reg),
clrbits_le32(base + info->control_regs[reg], bitmask);
return wait_for_bit_le32(base + info->status_regs[reg],
bitmask, 0, 100, 0);
} else {
setbits_le32(base + SMSTPCR(reg), bitmask);
setbits_le32(base + info->control_regs[reg], bitmask);
return 0;
}
}
@ -164,7 +124,7 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
/* Stop module clock */
for (i = 0; i < info->mstp_table_size; i++) {
clrsetbits_le32(base + SMSTPCR(i),
clrsetbits_le32(base + info->control_regs[i],
info->mstp_table[i].sdis,
info->mstp_table[i].sen);
clrsetbits_le32(base + RMSTPCR(i),

62
drivers/clk/renesas/renesas-cpg-mssr.h
View File

@ -14,14 +14,21 @@
#define __DRIVERS_CLK_RENESAS_CPG_MSSR__
#include <linux/bitops.h>
enum clk_reg_layout {
CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
};
struct cpg_mssr_info {
const struct cpg_core_clk *core_clk;
unsigned int core_clk_size;
enum clk_reg_layout reg_layout;
const struct mssr_mod_clk *mod_clk;
unsigned int mod_clk_size;
const struct mstp_stop_table *mstp_table;
unsigned int mstp_table_size;
const char *reset_node;
unsigned int reset_modemr_offset;
const char *extalr_node;
const char *extal_usb_node;
unsigned int mod_clk_base;
@ -30,6 +37,10 @@ struct cpg_mssr_info {
unsigned int clk_extal_usb_id;
unsigned int pll0_div;
const void *(*get_pll_config)(const u32 cpg_mode);
const u16 *status_regs;
const u16 *control_regs;
const u16 *reset_regs;
const u16 *reset_clear_regs;
};
/*
@ -114,7 +125,56 @@ int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
const struct cpg_core_clk **core);
int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
struct clk *parent);
int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
int renesas_clk_endisable(struct clk *clk, void __iomem *base,
struct cpg_mssr_info *info, bool enable);
int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
/*
* Module Standby and Software Reset register offets.
*
* If the registers exist, these are valid for SH-Mobile, R-Mobile,
* R-Car Gen2, R-Car Gen3, and RZ/G1.
* These are NOT valid for R-Car Gen1 and RZ/A1!
*/
/*
* Module Stop Status Register offsets
*/
static const u16 mstpsr[] = {
0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
0x9A0, 0x9A4, 0x9A8, 0x9AC,
};
/*
* System Module Stop Control Register offsets
*/
static const u16 smstpcr[] = {
0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
0x990, 0x994, 0x998, 0x99C,
};
/*
* Software Reset Register offsets
*/
static const u16 srcr[] = {
0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
0x920, 0x924, 0x928, 0x92C,
};
/* Realtime Module Stop Control Register offsets */
#define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10)
/* Modem Module Stop Control Register offsets (r8a73a4) */
#define MMSTPCR(i) (smstpcr[i] + 0x20)
/* Software Reset Clearing Register offsets */
static const u16 srstclr[] = {
0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
0x960, 0x964, 0x968, 0x96C,
};
#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */

13
drivers/gpio/gpio-rcar.c
View File

@ -66,9 +66,12 @@ static int rcar_gpio_set_value(struct udevice *dev, unsigned offset,
return 0;
}
static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset,
static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset,
bool output)
{
struct rcar_gpio_priv *priv = dev_get_priv(dev);
void __iomem *regs = priv->regs;
/*
* follow steps in the GPIO documentation for
* "Setting General Output Mode" and
@ -90,9 +93,7 @@ static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset,
static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset)
{
struct rcar_gpio_priv *priv = dev_get_priv(dev);
rcar_gpio_set_direction(priv->regs, offset, false);
rcar_gpio_set_direction(dev, offset, false);
return 0;
}
@ -100,11 +101,9 @@ static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset)
static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset,
int value)
{
struct rcar_gpio_priv *priv = dev_get_priv(dev);
/* write GPIO value to output before selecting output mode of pin */
rcar_gpio_set_value(dev, offset, value);
rcar_gpio_set_direction(priv->regs, offset, true);
rcar_gpio_set_direction(dev, offset, true);
return 0;
}

84
drivers/pinctrl/renesas/Kconfig
View File

@ -5,57 +5,41 @@ config PINCTRL_PFC
depends on DM && ARCH_RMOBILE
default n if CPU_RZA1
help
Enable support for clock present on Renesas RCar SoCs.
Support pin multiplexing control on Renesas SoCs.
These drivers are controlled by a device tree node which contains
both the GPIO definitions and pin control functions for each
available multiplex function.
config PINCTRL_PFC_R8A7790
bool "Renesas RCar Gen2 R8A7790 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A7790 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
Support pin multiplexing control on Renesas RCar Gen2 R8A7790 SoCs.
config PINCTRL_PFC_R8A7791
bool "Renesas RCar Gen2 R8A7791 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A7791 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
Support pin multiplexing control on Renesas RCar Gen2 R8A7791 SoCs.
config PINCTRL_PFC_R8A7792
bool "Renesas RCar Gen2 R8A7792 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A7792 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
Support pin multiplexing control on Renesas RCar Gen2 R8A7792 SoCs.
config PINCTRL_PFC_R8A7793
bool "Renesas RCar Gen2 R8A7793 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A7793 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
Support pin multiplexing control on Renesas RCar Gen2 R8A7793 SoCs.
config PINCTRL_PFC_R8A7794
bool "Renesas RCar Gen2 R8A7794 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A7794 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
Support pin multiplexing control on Renesas RCar Gen2 R8A7794 SoCs.
config PINCTRL_PFC_R8A774A1
bool "Renesas RZ/G2 R8A774A1 pin control driver"
@ -63,110 +47,66 @@ config PINCTRL_PFC_R8A774A1
help
Support pin multiplexing control on Renesas RZ/G2M R8A774A1 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A774B1
bool "Renesas RZ/G2 R8A774B1 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RZ/G2N R8A774B1 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A774C0
bool "Renesas RZ/G2 R8A774C0 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RZ/G2E R8A774C0 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A774E1
bool "Renesas RZ/G2 R8A774E1 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A7795
bool "Renesas RCar Gen3 R8A7795 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A7796
bool "Renesas RCar Gen3 R8A7796 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A7796 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A77965
bool "Renesas RCar Gen3 R8A77965 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A77965 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A77970
bool "Renesas RCar Gen3 R8A77970 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A77970 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A77980
bool "Renesas RCar Gen3 R8A77980 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A77980 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A77990
bool "Renesas RCar Gen3 R8A77990 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A77990 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A77995
bool "Renesas RCar Gen3 R8A77995 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A77995 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R7S72100
bool "Renesas RZ/A1 R7S72100 pin control driver"
depends on CPU_RZA1
@ -174,8 +114,4 @@ config PINCTRL_PFC_R7S72100
help
Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
endif

41
drivers/pinctrl/renesas/pfc.c
View File

@ -131,14 +131,25 @@ u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
}
static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
{
u32 unlock;
if (!pfc->info->unlock_reg)
return;
if (pfc->info->unlock_reg >= 0x80000000UL)
unlock = pfc->info->unlock_reg;
else
/* unlock_reg is a mask */
unlock = reg & ~pfc->info->unlock_reg;
sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)unlock, 32, ~data);
}
void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
{
void __iomem *unlock_reg =
(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
if (pfc->info->unlock_reg)
sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
sh_pfc_unlock_reg(pfc, reg, data);
sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
}
@ -168,8 +179,6 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
unsigned int field, u32 value)
{
void __iomem *mapped_reg;
void __iomem *unlock_reg =
(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
unsigned int pos;
u32 mask, data;
@ -186,9 +195,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
data &= mask;
data |= value;
if (pfc->info->unlock_reg)
sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
sh_pfc_unlock_reg(pfc, crp->reg, data);
sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}
@ -679,8 +686,6 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
unsigned int size;
unsigned int step;
void __iomem *reg;
void __iomem *unlock_reg =
(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
u32 val;
reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
@ -701,9 +706,7 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
val &= ~GENMASK(offset + 4 - 1, offset);
val |= strength << offset;
if (unlock_reg)
sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
sh_pfc_unlock_reg(pfc, (uintptr_t)reg, val);
sh_pfc_write_raw_reg(reg, 32, val);
return 0;
@ -743,8 +746,6 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
{
struct sh_pfc *pfc = pmx->pfc;
void __iomem *pocctrl;
void __iomem *unlock_reg =
(void __iomem *)(uintptr_t)pfc->info->unlock_reg;
u32 addr, val;
int bit, ret;
@ -790,9 +791,7 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
else
val &= ~BIT(bit);
if (unlock_reg)
sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
sh_pfc_unlock_reg(pfc, addr, val);
sh_pfc_write_raw_reg(pocctrl, 32, val);
break;

2
drivers/pinctrl/renesas/sh_pfc.h
View File

@ -284,7 +284,7 @@ struct sh_pfc_soc_info {
const struct pinmux_irq *gpio_irq;
unsigned int gpio_irq_size;
u32 unlock_reg;
u32 unlock_reg; /* can be literal address or mask */
};
u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);