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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
e935409199
The MODEMR register offset changed on R8A779A0, make the MODEMR offset configurable. Fill the offset in on all clock drivers. No functional change. Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from struct cpg_mssr_info" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
269 lines
9.4 KiB
C
269 lines
9.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* r8a77995 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2017 Glider bvba
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*
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* Based on r8a7795-cpg-mssr.c
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*
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* Copyright (C) 2015 Glider bvba
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* Copyright (C) 2015 Renesas Electronics Corp.
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/bitops.h>
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#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen3-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,
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/* External Input Clocks */
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CLK_EXTAL,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL0,
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CLK_PLL1,
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CLK_PLL3,
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CLK_PLL0D2,
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CLK_PLL0D3,
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CLK_PLL0D5,
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CLK_PLL1D2,
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CLK_PE,
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CLK_S0,
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CLK_S1,
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CLK_S2,
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CLK_S3,
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CLK_SDSRC,
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CLK_RPCSRC,
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CLK_RINT,
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CLK_OCO,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static const struct cpg_core_clk r8a77995_core_clks[] = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
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DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
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DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
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DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
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DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
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DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
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DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
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DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
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DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
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DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
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DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
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DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC,
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CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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R8A77995_CLK_RPC),
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DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
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DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
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/* Core Clock Outputs */
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DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
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DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
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DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
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DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
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DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
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DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
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DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
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DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
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DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
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DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
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DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
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DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
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DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
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DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
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DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
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DEF_FIXED("cr", R8A77995_CLK_CR, CLK_PLL1D2, 2, 1),
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DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
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DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
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DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
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DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
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DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
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DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
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DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
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DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
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DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
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DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
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};
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static const struct mssr_mod_clk r8a77995_mod_clks[] = {
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DEF_MOD("tmu4", 121, R8A77995_CLK_S1D4C),
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DEF_MOD("tmu3", 122, R8A77995_CLK_S3D2C),
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DEF_MOD("tmu2", 123, R8A77995_CLK_S3D2C),
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DEF_MOD("tmu1", 124, R8A77995_CLK_S3D2C),
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DEF_MOD("tmu0", 125, R8A77995_CLK_CP),
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DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
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DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
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DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
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DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
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DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
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DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
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DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
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DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
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DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
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DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
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DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
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DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
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DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
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DEF_MOD("cmt3", 300, R8A77995_CLK_R),
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DEF_MOD("cmt2", 301, R8A77995_CLK_R),
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DEF_MOD("cmt1", 302, R8A77995_CLK_R),
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DEF_MOD("cmt0", 303, R8A77995_CLK_R),
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DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
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DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
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DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
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DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
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DEF_MOD("rwdt", 402, R8A77995_CLK_R),
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DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
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DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
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DEF_MOD("audmac0", 502, R8A77995_CLK_S1D2),
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DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
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DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
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DEF_MOD("thermal", 522, R8A77995_CLK_CP),
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DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
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DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
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DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
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DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
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DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
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DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
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DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
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DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
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DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
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DEF_MOD("cmm1", 710, R8A77995_CLK_S1D1),
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DEF_MOD("cmm0", 711, R8A77995_CLK_S1D1),
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DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
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DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
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DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
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DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
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DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
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DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
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DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
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DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
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DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
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DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
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DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
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DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
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DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
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DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
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DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
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DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
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DEF_MOD("rpc", 917, R8A77995_CLK_RPC),
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DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
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DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
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DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
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DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
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DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
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DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
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DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
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DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
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DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
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DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
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DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
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DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
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DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
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};
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/*
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* CPG Clock Data
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*/
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/*
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* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
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*--------------------------------------------------------------------
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* 0 48 x 1 x250/4 x100/3 x100/3
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* 1 48 x 1 x250/4 x100/3 x58/3
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*/
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#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
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static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
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/* EXTAL div PLL1 mult/div PLL3 mult/div */
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{ 1, 100, 3, 100, 3, },
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{ 1, 100, 3, 58, 3, },
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};
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static const struct mstp_stop_table r8a77995_mstp_table[] = {
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{ 0x00210000, 0x0, 0x00210000, 0 },
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{ 0x03e01000, 0x0, 0x03e01000, 0 },
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{ 0x000e2fdc, 0x2000, 0x000e2fd8, 0 },
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{ 0xc00014df, 0x400, 0xc00014df, 0 },
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{ 0x80000004, 0x180, 0x80000004, 0 },
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{ 0x40d20004, 0x0, 0x40d20004, 0 },
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{ 0x08c0008c, 0x0, 0x08c0008c, 0 },
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{ 0x09941c18, 0x0, 0x09941c18, 0 },
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{ 0x00801087, 0x0, 0x00801087, 0 },
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{ 0xf143dfc0, 0x0, 0xf143dfc0, 0 },
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{ 0x063e1820, 0x0, 0x063e1820, 0 },
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{ 0x00000000, 0x0, 0x00000000, 0 },
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};
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static const void *r8a77995_get_pll_config(const u32 cpg_mode)
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{
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return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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}
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static const struct cpg_mssr_info r8a77995_cpg_mssr_info = {
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.core_clk = r8a77995_core_clks,
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.core_clk_size = ARRAY_SIZE(r8a77995_core_clks),
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.mod_clk = r8a77995_mod_clks,
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.mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks),
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.mstp_table = r8a77995_mstp_table,
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.mstp_table_size = ARRAY_SIZE(r8a77995_mstp_table),
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.reset_node = "renesas,r8a77995-rst",
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.reset_modemr_offset = CPG_RST_MODEMR,
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.mod_clk_base = MOD_CLK_BASE,
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.clk_extal_id = CLK_EXTAL,
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.clk_extalr_id = ~0,
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.get_pll_config = r8a77995_get_pll_config,
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};
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static const struct udevice_id r8a77995_clk_ids[] = {
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{
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.compatible = "renesas,r8a77995-cpg-mssr",
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.data = (ulong)&r8a77995_cpg_mssr_info
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},
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{ }
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};
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U_BOOT_DRIVER(clk_r8a77995) = {
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.name = "clk_r8a77995",
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.id = UCLASS_CLK,
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.of_match = r8a77995_clk_ids,
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.priv_auto = sizeof(struct gen3_clk_priv),
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.ops = &gen3_clk_ops,
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.probe = gen3_clk_probe,
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.remove = gen3_clk_remove,
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};
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