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imx: mx6slevk: add SPL support
Add SPL boot support for mx6slevk board. 1. Introduce a configuration file mx6slevk_spl_defconfig. 2. i.MX6SL has same DRAM space with i.MX6SX, need to change SPL DRAM SPACE. 3. Include imx6_spl.h and related SPL macro in mx6slevk.h. 4. select SUPPORT_SPL for TARGET_MX6SLEVK. 5. Add SPL board code to do related initialization. Boot Log: U-Boot SPL 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59) reading u-boot.img reading u-boot.img U-Boot 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59 +0000) CPU: Freescale i.MX6SL rev1.2 996 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 50C Reset cause: POR Board: MX6SLEVK I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
eb796cbb69
commit
e7d3b21bb7
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@ -91,6 +91,7 @@ config TARGET_MX6SABRESD
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config TARGET_MX6SLEVK
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bool "mx6slevk"
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_MX6SXSABRESD
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bool "mx6sxsabresd"
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@ -8,7 +8,9 @@
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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@ -190,6 +192,7 @@ int board_mmc_getcd(struct mmc *mmc)
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int board_mmc_init(bd_t *bis)
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{
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#ifndef CONFIG_SPL_BUILD
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int i, ret;
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/*
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@ -234,6 +237,44 @@ int board_mmc_init(bd_t *bis)
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}
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return 0;
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#else
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struct src *src_regs = (struct src *)SRC_BASE_ADDR;
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u32 val;
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u32 port;
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val = readl(&src_regs->sbmr1);
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/* Boot from USDHC */
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port = (val >> 11) & 0x3;
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switch (port) {
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case 0:
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imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
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ARRAY_SIZE(usdhc1_pads));
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gpio_direction_input(USDHC1_CD_GPIO);
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usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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break;
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case 1:
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imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
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ARRAY_SIZE(usdhc2_pads));
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gpio_direction_input(USDHC2_CD_GPIO);
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usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
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usdhc_cfg[0].max_bus_width = 4;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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break;
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case 2:
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
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ARRAY_SIZE(usdhc3_pads));
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gpio_direction_input(USDHC3_CD_GPIO);
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usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg[0].max_bus_width = 4;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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break;
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}
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gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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#endif
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}
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#ifdef CONFIG_SYS_I2C_MXC
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@ -361,3 +402,126 @@ int checkboard(void)
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#include <spl.h>
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#include <libfdt.h>
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const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_sdqs0 = 0x00003030,
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.dram_sdqs1 = 0x00003030,
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.dram_sdqs2 = 0x00003030,
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.dram_sdqs3 = 0x00003030,
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.dram_dqm0 = 0x00000030,
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.dram_dqm1 = 0x00000030,
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.dram_dqm2 = 0x00000030,
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.dram_dqm3 = 0x00000030,
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.dram_cas = 0x00000030,
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.dram_ras = 0x00000030,
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.dram_sdclk_0 = 0x00000028,
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.dram_reset = 0x00000030,
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.dram_sdba2 = 0x00000000,
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.dram_odt0 = 0x00000008,
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.dram_odt1 = 0x00000008,
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};
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const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
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.grp_b0ds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_b2ds = 0x00000030,
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.grp_b3ds = 0x00000030,
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.grp_addds = 0x00000030,
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.grp_ctlds = 0x00000030,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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.grp_ddr_type = 0x00080000,
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};
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const struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p0_mpdgctrl0 = 0x20000000,
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.p0_mpdgctrl1 = 0x00000000,
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.p0_mprddlctl = 0x4241444a,
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.p0_mpwrdlctl = 0x3030312b,
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.mpzqlp2ctl = 0x1b4700c7,
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};
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static struct mx6_lpddr2_cfg mem_ddr = {
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.mem_speed = 800,
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.density = 4,
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.width = 32,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.trcd_lp = 2000,
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.trppb_lp = 2000,
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.trpab_lp = 2250,
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.trasmin = 4200,
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};
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0xFFFFFFFF, &ccm->CCGR0);
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writel(0xFFFFFFFF, &ccm->CCGR1);
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writel(0xFFFFFFFF, &ccm->CCGR2);
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writel(0xFFFFFFFF, &ccm->CCGR3);
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writel(0xFFFFFFFF, &ccm->CCGR4);
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writel(0xFFFFFFFF, &ccm->CCGR5);
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writel(0xFFFFFFFF, &ccm->CCGR6);
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writel(0x00260324, &ccm->cbcmr);
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}
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static void spl_dram_init(void)
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{
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struct mx6_ddr_sysinfo sysinfo = {
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.dsize = mem_ddr.width / 32,
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.cs_density = 20,
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.ncs = 2,
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.cs1_mirror = 0,
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.walat = 0,
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.ralat = 2,
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.mif3_mode = 3,
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.bi_on = 1,
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.rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
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.rtt_nom = 0,
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.sde_to_rst = 0, /* LPDDR2 does not need this field */
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.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
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.ddr_type = DDR_TYPE_LPDDR2,
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};
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mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
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}
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void board_init_f(ulong dummy)
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{
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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ccgr_init();
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/* iomux and setup of i2c */
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board_early_init_f();
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/* setup GP timer */
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timer_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* DDR initialization */
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spl_dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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/* load/boot image from boot device */
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board_init_r(NULL, 0);
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}
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void reset_cpu(ulong addr)
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{
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}
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#endif
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8
configs/mx6slevk_spl_defconfig
Normal file
8
configs/mx6slevk_spl_defconfig
Normal file
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@ -0,0 +1,8 @@
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CONFIG_ARM=y
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CONFIG_ARCH_MX6=y
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CONFIG_TARGET_MX6SLEVK=y
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CONFIG_SPL=y
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL"
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CONFIG_DM=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_THERMAL=y
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@ -61,7 +61,7 @@
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#endif
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#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
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#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SL)
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#define CONFIG_SPL_BSS_START_ADDR 0x88200000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x88300000
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@ -11,6 +11,13 @@
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#include "mx6_common.h"
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#ifdef CONFIG_SPL
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_FAT_SUPPORT
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#include "imx6_spl.h"
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#endif
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#define MACH_TYPE_MX6SLEVK 4307
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#define CONFIG_MACH_TYPE MACH_TYPE_MX6SLEVK
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