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https://github.com/brain-hackers/u-boot-brain
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imx: mx6: ddr: add LPDDR2 support
Add LPDDR2 support: 1. Implement a function mx6_lpddr2_cfg to initialize MMDC for LPDDR2. 2. Introduce a structure mx6_lpddr2_cfg, most entrys are same to mx6_ddr3_cfg, but still keep it a single one for easy to choose parameters for LPDDR2. 3. If ddr_type is LPDDR2, use mx6_lpddr2_cfg to init MMDC. 4. Update comments. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
f2ff834365
commit
eb796cbb69
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@ -7,6 +7,7 @@
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#include <common.h>
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#include <linux/types.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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@ -330,15 +331,20 @@ void mx6sdl_dram_iocfg(unsigned width,
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* Configure mx6 mmdc registers based on:
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* - board-specific memory configuration
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* - board-specific calibration data
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* - ddr3 chip details
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* - ddr3/lpddr2 chip details
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*
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* The various calculations here are derived from the Freescale
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* i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC
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* configuration registers based on memory system and memory chip parameters.
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* 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
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* MMDC configuration registers based on memory system and memory chip
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* parameters.
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*
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* 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
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* configuration registers based on memory system and memory chip
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* parameters.
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*
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* The defaults here are those which were specified in the spreadsheet.
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* For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
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* section titled MMDC initialization
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* and/or IMX6SLRM section titled MMDC initialization.
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*/
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#define MR(val, ba, cmd, cs1) \
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((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
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@ -348,6 +354,290 @@ void mx6sdl_dram_iocfg(unsigned width,
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mmdc1->entry = value; \
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} while (0)
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/*
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* According JESD209-2B-LPDDR2: Table 103
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* WL: write latency
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*/
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static int lpddr2_wl(uint32_t mem_speed)
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{
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switch (mem_speed) {
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case 1066:
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case 933:
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return 4;
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case 800:
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return 3;
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case 677:
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case 533:
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return 2;
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case 400:
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case 333:
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return 1;
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default:
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puts("invalid memory speed\n");
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hang();
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}
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return 0;
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}
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/*
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* According JESD209-2B-LPDDR2: Table 103
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* RL: read latency
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*/
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static int lpddr2_rl(uint32_t mem_speed)
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{
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switch (mem_speed) {
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case 1066:
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return 8;
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case 933:
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return 7;
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case 800:
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return 6;
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case 677:
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return 5;
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case 533:
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return 4;
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case 400:
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case 333:
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return 3;
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default:
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puts("invalid memory speed\n");
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hang();
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}
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return 0;
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}
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void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
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const struct mx6_mmdc_calibration *calib,
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const struct mx6_lpddr2_cfg *lpddr2_cfg)
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{
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volatile struct mmdc_p_regs *mmdc0;
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u32 val;
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u8 tcke, tcksrx, tcksre, trrd;
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u8 twl, txp, tfaw, tcl;
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u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
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u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
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u16 cs0_end;
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u8 coladdr;
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int clkper; /* clock period in picoseconds */
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int clock; /* clock freq in mHz */
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int cs;
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/* only support 16/32 bits */
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if (sysinfo->dsize > 1)
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hang();
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mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
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clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
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clkper = (1000 * 1000) / clock; /* pico seconds */
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twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
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/* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
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switch (lpddr2_cfg->density) {
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case 1:
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case 2:
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case 4:
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trfc = DIV_ROUND_UP(130000, clkper) - 1;
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txsr = DIV_ROUND_UP(140000, clkper) - 1;
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break;
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case 8:
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trfc = DIV_ROUND_UP(210000, clkper) - 1;
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txsr = DIV_ROUND_UP(220000, clkper) - 1;
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break;
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default:
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/*
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* 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
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*/
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hang();
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break;
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}
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/*
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* txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
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* set them to 0. */
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txp = DIV_ROUND_UP(7500, clkper) - 1;
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tcke = 3;
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if (lpddr2_cfg->mem_speed == 333)
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tfaw = DIV_ROUND_UP(60000, clkper) - 1;
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else
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tfaw = DIV_ROUND_UP(50000, clkper) - 1;
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trrd = DIV_ROUND_UP(10000, clkper) - 1;
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/* tckesr for LPDDR2 */
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tcksre = DIV_ROUND_UP(15000, clkper);
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tcksrx = tcksre;
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twr = DIV_ROUND_UP(15000, clkper) - 1;
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/*
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* tMRR: 2, tMRW: 5
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* tMRD should be set to max(tMRR, tMRW)
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*/
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tmrd = 5;
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tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
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/* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
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trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
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trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
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clkper / 10) - 1;
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trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
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trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
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/* To LPDDR2, CL in MDCFG0 refers to RL */
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tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
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twtr = DIV_ROUND_UP(7500, clkper) - 1;
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trtp = DIV_ROUND_UP(7500, clkper) - 1;
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cs0_end = 4 * sysinfo->cs_density - 1;
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debug("density:%d Gb (%d Gb per chip)\n",
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sysinfo->cs_density, lpddr2_cfg->density);
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debug("clock: %dMHz (%d ps)\n", clock, clkper);
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debug("memspd:%d\n", lpddr2_cfg->mem_speed);
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debug("trcd_lp=%d\n", trcd_lp);
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debug("trppb_lp=%d\n", trppb_lp);
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debug("trpab_lp=%d\n", trpab_lp);
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debug("trc_lp=%d\n", trc_lp);
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debug("tcke=%d\n", tcke);
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debug("tcksrx=%d\n", tcksrx);
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debug("tcksre=%d\n", tcksre);
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debug("trfc=%d\n", trfc);
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debug("txsr=%d\n", txsr);
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debug("txp=%d\n", txp);
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debug("tfaw=%d\n", tfaw);
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debug("tcl=%d\n", tcl);
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debug("tras=%d\n", tras);
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debug("twr=%d\n", twr);
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debug("tmrd=%d\n", tmrd);
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debug("twl=%d\n", twl);
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debug("trtp=%d\n", trtp);
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debug("twtr=%d\n", twtr);
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debug("trrd=%d\n", trrd);
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debug("cs0_end=%d\n", cs0_end);
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debug("ncs=%d\n", sysinfo->ncs);
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/*
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* board-specific configuration:
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* These values are determined empirically and vary per board layout
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*/
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mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
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mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
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mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
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mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
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mmdc0->mprddlctl = calib->p0_mprddlctl;
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mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
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mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
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/* Read data DQ Byte0-3 delay */
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mmdc0->mprddqby0dl = 0x33333333;
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mmdc0->mprddqby1dl = 0x33333333;
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if (sysinfo->dsize > 0) {
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mmdc0->mprddqby2dl = 0x33333333;
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mmdc0->mprddqby3dl = 0x33333333;
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}
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/* Write data DQ Byte0-3 delay */
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mmdc0->mpwrdqby0dl = 0xf3333333;
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mmdc0->mpwrdqby1dl = 0xf3333333;
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if (sysinfo->dsize > 0) {
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mmdc0->mpwrdqby2dl = 0xf3333333;
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mmdc0->mpwrdqby3dl = 0xf3333333;
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}
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/*
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* In LPDDR2 mode this register should be cleared,
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* so no termination will be activated.
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*/
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mmdc0->mpodtctrl = 0;
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/* complete calibration */
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val = (1 << 11); /* Force measurement on delay-lines */
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mmdc0->mpmur0 = val;
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/* Step 1: configuration request */
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mmdc0->mdscr = (u32)(1 << 15); /* config request */
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/* Step 2: Timing configuration */
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mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
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(tfaw << 4) | tcl;
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mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
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mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
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mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
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(trppb_lp << 4) | trpab_lp;
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mmdc0->mdotc = 0;
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mmdc0->mdasp = cs0_end; /* CS addressing */
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/* Step 3: Configure DDR type */
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mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
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(sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
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(sysinfo->ralat << 6) | (1 << 3);
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/* Step 4: Configure delay while leaving reset */
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mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
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(sysinfo->rst_to_cke << 0);
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/* Step 5: Configure DDR physical parameters (density and burst len) */
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coladdr = lpddr2_cfg->coladdr;
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if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
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coladdr += 4;
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else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
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coladdr += 1;
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mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
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(coladdr - 9) << 20 | /* COL */
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(0 << 19) | /* Burst Length = 4 for LPDDR2 */
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(sysinfo->dsize << 16); /* DDR data bus size */
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/* Step 6: Perform ZQ calibration */
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val = 0xa1390003; /* one-time HW ZQ calib */
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mmdc0->mpzqhwctrl = val;
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/* Step 7: Enable MMDC with desired chip select */
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mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
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((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
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/* Step 8: Write Mode Registers to Init LPDDR2 devices */
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for (cs = 0; cs < sysinfo->ncs; cs++) {
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/* MR63: reset */
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mmdc0->mdscr = MR(63, 0, 3, cs);
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/* MR10: calibration,
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* 0xff is calibration command after intilization.
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*/
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val = 0xA | (0xff << 8);
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mmdc0->mdscr = MR(val, 0, 3, cs);
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/* MR1 */
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val = 0x1 | (0x82 << 8);
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mmdc0->mdscr = MR(val, 0, 3, cs);
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/* MR2 */
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val = 0x2 | (0x04 << 8);
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mmdc0->mdscr = MR(val, 0, 3, cs);
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/* MR3 */
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val = 0x3 | (0x02 << 8);
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mmdc0->mdscr = MR(val, 0, 3, cs);
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}
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/* Step 10: Power down control and self-refresh */
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mmdc0->mdpdc = (tcke & 0x7) << 16 |
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5 << 12 | /* PWDT_1: 256 cycles */
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5 << 8 | /* PWDT_0: 256 cycles */
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1 << 6 | /* BOTH_CS_PD */
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(tcksrx & 0x7) << 3 |
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(tcksre & 0x7);
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mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
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/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
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val = 0xa1310003;
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mmdc0->mpzqhwctrl = val;
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/* Step 12: Configure and activate periodic refresh */
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mmdc0->mdref = (0 << 14) | /* REF_SEL: Periodic refresh cycle: 64kHz */
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(3 << 11); /* REFR: Refresh Rate - 4 refreshes */
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/* Step 13: Deassert config request - init complete */
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mmdc0->mdscr = 0x00000000;
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/* wait for auto-ZQ calibration to complete */
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mdelay(1);
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}
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void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
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const struct mx6_mmdc_calibration *calib,
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const struct mx6_ddr3_cfg *ddr3_cfg)
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@ -662,6 +952,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
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{
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if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
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mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
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} else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
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mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
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} else {
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puts("Unsupported ddr type\n");
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hang();
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@ -377,6 +377,21 @@ struct mx6_ddr3_cfg {
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u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
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};
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/* Device Information: Varies per LPDDR2 part number and speed grade */
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struct mx6_lpddr2_cfg {
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u16 mem_speed; /* ie 800 for LPDDR2-800 */
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u8 density; /* chip density (Gb) (1,2,4,8) */
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u8 width; /* bus width (bits) (4,8,16) */
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u8 banks; /* number of banks */
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u8 rowaddr; /* row address bits (11-16)*/
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u8 coladdr; /* col address bits (9-12) */
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u16 trcd_lp;
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u16 trppb_lp;
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u16 trpab_lp;
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u16 trcmin; /* tRC min (ns*100) */
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u16 trasmin; /* tRAS min (ns*100) */
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};
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/* System Information: Varies per board design, layout, and term choices */
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struct mx6_ddr_sysinfo {
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u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
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