mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 07:16:04 +09:00
ppc: Remove MPC8308RDB board
This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
2322b9568f
commit
ddfb9aef65
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@ -28,11 +28,6 @@ config TARGET_CADDY2
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bool "Support caddy2"
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select ARCH_MPC8349
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config TARGET_MPC8308RDB
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bool "Support MPC8308RDB"
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select ARCH_MPC8308
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select SYS_FSL_ERRATUM_ESDHC111
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config TARGET_MPC8313ERDB_NOR
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bool "Support MPC8313ERDB_NOR"
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select ARCH_MPC8313
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@ -325,7 +320,6 @@ config FSL_ELBC
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bool
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source "board/esd/vme8349/Kconfig"
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source "board/freescale/mpc8308rdb/Kconfig"
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source "board/freescale/mpc8313erdb/Kconfig"
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source "board/freescale/mpc8315erdb/Kconfig"
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source "board/freescale/mpc8323erdb/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_MPC8308RDB
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config SYS_BOARD
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default "mpc8308rdb"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "MPC8308RDB"
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endif
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@ -1,6 +0,0 @@
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MPC8308RDB BOARD
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M: Ilya Yanok <yanok@emcraft.com>
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S: Maintained
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F: board/freescale/mpc8308rdb/
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F: include/configs/MPC8308RDB.h
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F: configs/MPC8308RDB_defconfig
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@ -1,8 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# (C) Copyright 2010
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# Ilya Yanok, Emcraft Systems, yanok@emcraft.com
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obj-y := mpc8308rdb.o sdram.o
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@ -1,192 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2010 Freescale Semiconductor, Inc.
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* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
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*/
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#include <common.h>
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#include <hwconfig.h>
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#include <i2c.h>
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#include <init.h>
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#include <net.h>
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#include <spi.h>
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#include <linux/delay.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#include <pci.h>
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#include <mpc83xx.h>
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#include <vsc7385.h>
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#include <netdev.h>
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#include <fsl_esdhc.h>
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#include <asm/io.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_mpc83xx_serdes.h>
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/*
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* The following are used to control the SPI chip selects for the SPI command.
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*/
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#ifdef CONFIG_MPC8XXX_SPI
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#define SPI_CS_MASK 0x00400000
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs == 0;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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/* active low */
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clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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/* inactive high */
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setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
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}
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#endif /* CONFIG_MPC8XXX_SPI */
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#ifdef CONFIG_FSL_ESDHC
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int board_mmc_init(struct bd_info *bd)
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{
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return fsl_esdhc_mmc_init(bd);
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}
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#endif
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static u8 read_board_info(void)
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{
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u8 val8;
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i2c_set_bus_num(0);
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if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
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return val8;
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else
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return 0;
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}
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int checkboard(void)
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{
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static const char * const rev_str[] = {
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"1.0",
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"<reserved>",
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"<reserved>",
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"<reserved>",
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"<unknown>",
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};
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u8 info;
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int i;
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info = read_board_info();
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i = (!info) ? 4 : info & 0x03;
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printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
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return 0;
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}
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static struct pci_region pcie_regions_0[] = {
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{
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.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
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.size = CONFIG_SYS_PCIE1_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
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.size = CONFIG_SYS_PCIE1_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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void pci_init_board(void)
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{
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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sysconf83xx_t *sysconf = &immr->sysconf;
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law83xx_t *pcie_law = sysconf->pcielaw;
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struct pci_region *pcie_reg[] = { pcie_regions_0 };
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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/* Deassert the resets in the control register */
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out_be32(&sysconf->pecr1, 0xE0008000);
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udelay(2000);
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/* Configure PCI Express Local Access Windows */
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out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
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mpc83xx_pcie_init(1, pcie_reg);
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}
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/*
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* Miscellaneous late-boot configurations
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*
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* If a VSC7385 microcode image is present, then upload it.
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*/
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int misc_init_r(void)
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{
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#ifdef CONFIG_MPC8XXX_SPI
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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sysconf83xx_t *sysconf = &immr->sysconf;
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/*
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* Set proper bits in SICRH to allow SPI on header J8
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*
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* NOTE: this breaks the TSEC2 interface, attached to the Vitesse
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* switch. The pinmux configuration does not have a fine enough
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* granularity to support both simultaneously.
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*/
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clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
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puts("WARNING: SPI enabled, TSEC2 support is broken\n");
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/* Set header J8 SPI chip select output, disabled */
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setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
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setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
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#endif
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#ifdef CONFIG_VSC7385_IMAGE
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if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
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CONFIG_VSC7385_IMAGE_SIZE)) {
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puts("Failure uploading VSC7385 microcode.\n");
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return 1;
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}
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#endif
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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ft_cpu_setup(blob, bd);
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fsl_fdt_fixup_dr_usb(blob, bd);
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fdt_fixup_esdhc(blob, bd);
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return 0;
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}
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#endif
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int board_eth_init(struct bd_info *bis)
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{
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int rv, num_if = 0;
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/* Initialize TSECs first */
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rv = cpu_eth_init(bis);
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if (rv >= 0)
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num_if += rv;
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else
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printf("ERROR: failed to initialize TSECs.\n");
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rv = pci_eth_init(bis);
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if (rv >= 0)
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num_if += rv;
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else
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printf("ERROR: failed to initialize PCI Ethernet.\n");
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return num_if;
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}
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@ -1,84 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
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*
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* Authors: Nick.Spence@freescale.com
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* Wilson.Lo@freescale.com
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* scottwood@freescale.com
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*
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* This files is mostly identical to the original from
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* board\freescale\mpc8315erdb\sdram.c
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*/
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#include <common.h>
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#include <init.h>
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#include <mpc83xx.h>
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#include <asm/global_data.h>
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#include <asm/bitops.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Fixed sdram init -- doesn't use serial presence detect.
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*
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* This is useful for faster booting in configs where the RAM is unlikely
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* to be changed, or for things like NAND booting where space is tight.
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*/
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static long fixed_sdram(void)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2(msize);
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out_be32(&im->sysconf.ddrlaw[0].bar,
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CONFIG_SYS_SDRAM_BASE & 0xfffff000);
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out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
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out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
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out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
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out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
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/* Currently we use only one CS, so disable the other bank. */
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out_be32(&im->ddr.cs_config[1], 0);
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out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
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out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
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out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
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out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
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out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
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out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
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out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
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out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
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sync();
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/* enable DDR controller */
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setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
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sync();
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return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
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}
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int dram_init(void)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize;
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if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
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return -ENXIO;
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/* DDR SDRAM */
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msize = fixed_sdram();
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/* return total bus SDRAM size(bytes) -- DDR */
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gd->ram_size = msize;
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return 0;
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}
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@ -1,152 +0,0 @@
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CONFIG_PPC=y
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CONFIG_SYS_TEXT_BASE=0xFE000000
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_SECT_SIZE=0x10000
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CONFIG_SYS_CLK_FREQ=33333333
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CONFIG_MPC83xx=y
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CONFIG_TARGET_MPC8308RDB=y
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CONFIG_SYSTEM_PLL_VCO_DIV_2=y
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CONFIG_SYSTEM_PLL_FACTOR_4_1=y
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CONFIG_CORE_PLL_RATIO_3_1=y
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CONFIG_BOOT_MEMORY_SPACE_LOW=y
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CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
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CONFIG_TSEC1_MODE_RGMII=y
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CONFIG_TSEC2_MODE_RGMII=y
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CONFIG_BAT0=y
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CONFIG_BAT0_NAME="DDR"
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CONFIG_BAT0_BASE=0x00000000
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CONFIG_BAT0_LENGTH_128_MBYTES=y
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CONFIG_BAT0_ACCESS_RW=y
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CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
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CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
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CONFIG_BAT0_USER_MODE_VALID=y
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CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT1=y
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CONFIG_BAT1_NAME="IMMRBAR"
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CONFIG_BAT1_BASE=0xE0000000
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CONFIG_BAT1_LENGTH_8_MBYTES=y
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CONFIG_BAT1_ACCESS_RW=y
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CONFIG_BAT1_ICACHE_INHIBITED=y
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CONFIG_BAT1_ICACHE_GUARDED=y
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CONFIG_BAT1_DCACHE_INHIBITED=y
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CONFIG_BAT1_DCACHE_GUARDED=y
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CONFIG_BAT1_USER_MODE_VALID=y
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CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT2=y
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CONFIG_BAT2_NAME="FLASH"
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CONFIG_BAT2_BASE=0xFE000000
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CONFIG_BAT2_LENGTH_8_MBYTES=y
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CONFIG_BAT2_ACCESS_RW=y
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CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
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CONFIG_BAT2_DCACHE_INHIBITED=y
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CONFIG_BAT2_DCACHE_GUARDED=y
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CONFIG_BAT2_USER_MODE_VALID=y
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CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT3=y
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CONFIG_BAT3_NAME="STACK_IN_DCACHE"
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CONFIG_BAT3_BASE=0xE6000000
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CONFIG_BAT3_ACCESS_RW=y
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CONFIG_BAT3_USER_MODE_VALID=y
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CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
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CONFIG_LBLAW0=y
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CONFIG_LBLAW0_BASE=0xFE000000
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CONFIG_LBLAW0_NAME="FLASH"
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CONFIG_LBLAW0_LENGTH_8_MBYTES=y
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CONFIG_LBLAW1=y
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CONFIG_LBLAW1_BASE=0xE0600000
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CONFIG_LBLAW1_NAME="NAND"
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CONFIG_LBLAW1_LENGTH_32_KBYTES=y
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CONFIG_LBLAW2=y
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CONFIG_LBLAW2_BASE=0xF0000000
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CONFIG_LBLAW2_NAME="VSC7385"
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CONFIG_LBLAW2_LENGTH_128_KBYTES=y
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CONFIG_ELBC_BR0_OR0=y
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CONFIG_BR0_OR0_NAME="FLASH"
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CONFIG_BR0_OR0_BASE=0xFE000000
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CONFIG_BR0_PORTSIZE_16BIT=y
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CONFIG_OR0_AM_8_MBYTES=y
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CONFIG_OR0_XAM_SET=y
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CONFIG_OR0_SCY_15=y
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CONFIG_OR0_CSNT_EARLIER=y
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CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
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CONFIG_OR0_XACS_EXTENDED=y
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CONFIG_OR0_TRLX_RELAXED=y
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CONFIG_OR0_EHTR_8_CYCLE=y
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CONFIG_ELBC_BR1_OR1=y
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CONFIG_BR1_OR1_NAME="NAND"
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CONFIG_BR1_OR1_BASE=0xE0600000
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CONFIG_BR1_ERRORCHECKING_BOTH=y
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CONFIG_BR1_MACHINE_FCM=y
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CONFIG_OR1_SCY_1=y
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CONFIG_OR1_CSCT_8_CYCLE=y
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CONFIG_OR1_CST_ONE_CLOCK=y
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CONFIG_OR1_CHT_TWO_CLOCK=y
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CONFIG_OR1_TRLX_RELAXED=y
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CONFIG_OR1_EHTR_8_CYCLE=y
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CONFIG_ELBC_BR2_OR2=y
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CONFIG_BR2_OR2_NAME="VSC7385_BASE"
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CONFIG_BR2_OR2_BASE=0xF0000000
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CONFIG_OR2_AM_128_KBYTES=y
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CONFIG_OR2_SCY_15=y
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CONFIG_OR2_CSNT_EARLIER=y
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CONFIG_OR2_XACS_EXTENDED=y
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CONFIG_OR2_SETA_EXTERNAL=y
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CONFIG_OR2_TRLX_RELAXED=y
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CONFIG_OR2_EHTR_8_CYCLE=y
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CONFIG_HID0_FINAL_EMCP=y
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CONFIG_HID0_FINAL_DPM=y
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CONFIG_HID0_FINAL_ICE=y
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||||
CONFIG_HID2_HBE=y
|
||||
CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
|
||||
CONFIG_SICR_GPIO_A_TSEC2=y
|
||||
CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y
|
||||
CONFIG_SICR_IEEE1588_A_GPIO=y
|
||||
CONFIG_SICR_GTM_GPIO=y
|
||||
CONFIG_SICR_GPIOSEL_IEEE1588=y
|
||||
CONFIG_SICR_TMSOBI1_2_5_V=y
|
||||
CONFIG_SICR_TMSOBI2_2_5_V=y
|
||||
CONFIG_ACR_PIPE_DEP_4=y
|
||||
CONFIG_ACR_RPTCNT_4=y
|
||||
CONFIG_SPCR_TSECEP_3=y
|
||||
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
|
||||
CONFIG_LCRR_CLKDIV_2=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=5
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_AUTO_COMPLETE is not set
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_ADDR=0xFE080000
|
||||
CONFIG_ENV_ADDR_REDUND=0xFE090000
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,329 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_E300 1 /* E300 family */
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
|
||||
#define CONFIG_SYS_FSL_ESDHC_USE_PIO
|
||||
#endif
|
||||
|
||||
/*
|
||||
* On-board devices
|
||||
*
|
||||
* TSEC1 is SoC TSEC
|
||||
* TSEC2 is VSC switch
|
||||
*/
|
||||
#define CONFIG_TSEC1
|
||||
#define CONFIG_VSC7385_ENET
|
||||
|
||||
/*
|
||||
* SERDES
|
||||
*/
|
||||
#define CONFIG_FSL_SERDES
|
||||
#define CONFIG_FSL_SERDES1 0xe3000
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
|
||||
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
|
||||
| DDRCDR_PZ_LOZ \
|
||||
| DDRCDR_NZ_LOZ \
|
||||
| DDRCDR_ODT \
|
||||
| DDRCDR_Q_DRN)
|
||||
/* 0x7b880001 */
|
||||
/*
|
||||
* Manually set up DDR parameters
|
||||
* consist of two chips HY5PS12621BFP-C4 from HYNIX
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
|
||||
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
|
||||
| CSCONFIG_ODT_RD_NEVER \
|
||||
| CSCONFIG_ODT_WR_ONLY_CURRENT \
|
||||
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
|
||||
/* 0x80010102 */
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
||||
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_WRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_RRT_SHIFT) \
|
||||
| (0 << TIMING_CFG0_WWT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
|
||||
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
|
||||
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
|
||||
/* 0x00220802 */
|
||||
#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
|
||||
| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
|
||||
| (5 << TIMING_CFG1_CASLAT_SHIFT) \
|
||||
| (6 << TIMING_CFG1_REFREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRREC_SHIFT) \
|
||||
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
|
||||
| (2 << TIMING_CFG1_WRTORD_SHIFT))
|
||||
/* 0x27256222 */
|
||||
#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
|
||||
| (4 << TIMING_CFG2_CPO_SHIFT) \
|
||||
| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
|
||||
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
|
||||
| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
|
||||
| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
|
||||
| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
|
||||
/* 0x121048c5 */
|
||||
#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
|
||||
| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
|
||||
/* 0x03600100 */
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
|
||||
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
|
||||
| SDRAM_CFG_DBW_32)
|
||||
/* 0x43080000 */
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
|
||||
#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
|
||||
| (0x0232 << SDRAM_MODE_SD_SHIFT))
|
||||
/* ODT 150ohm CL=3, AL=1 on SDRAM */
|
||||
#define CONFIG_SYS_DDR_MODE2 0x00000000
|
||||
|
||||
/*
|
||||
* Memory test
|
||||
*/
|
||||
|
||||
/*
|
||||
* The reserved memory
|
||||
*/
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
|
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
|
||||
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
|
||||
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
/* 127 64KB sectors and 8 8KB top sectors per device */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 135
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
/*
|
||||
* NAND Flash on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
|
||||
#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
|
||||
/* 0xFFFF8396 */
|
||||
|
||||
#ifdef CONFIG_VSC7385_ENET
|
||||
#define CONFIG_TSEC2
|
||||
/* VSC7385 Base address on CS2 */
|
||||
#define CONFIG_SYS_VSC7385_BASE 0xF0000000
|
||||
#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
|
||||
/* 0xFFFE09FF */
|
||||
/* The flash address and size of the VSC7385 firmware image */
|
||||
#define CONFIG_VSC7385_IMAGE 0xFE7FE000
|
||||
#define CONFIG_VSC7385_IMAGE_SIZE 8192
|
||||
#endif
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
|
||||
|
||||
/*
|
||||
* SPI on header J8
|
||||
*
|
||||
* WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
|
||||
* due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
|
||||
*/
|
||||
#ifdef CONFIG_MPC8XXX_SPI
|
||||
#define CONFIG_USE_SPIFLASH
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Board info - revision and where boot from
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
|
||||
|
||||
/*
|
||||
* Config on-board RTC
|
||||
*/
|
||||
#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CONFIG_SYS_PCIE1_BASE 0xA0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
|
||||
#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
|
||||
#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
|
||||
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
|
||||
|
||||
/* enable PCIE clock */
|
||||
#define CONFIG_SYS_SCCR_PCIEXP1CM 1
|
||||
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||
#define CONFIG_PCIE
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
|
||||
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
|
||||
|
||||
/*
|
||||
* TSEC
|
||||
*/
|
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
|
||||
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
|
||||
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
|
||||
#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
|
||||
|
||||
/*
|
||||
* TSEC ethernet configuration
|
||||
*/
|
||||
#define CONFIG_TSEC1_NAME "eTSEC0"
|
||||
#define CONFIG_TSEC2_NAME "eTSEC1"
|
||||
#define TSEC1_PHY_ADDR 2
|
||||
#define TSEC2_PHY_ADDR 1
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define TSEC1_FLAGS TSEC_GIGABIT
|
||||
#define TSEC2_FLAGS TSEC_GIGABIT
|
||||
|
||||
/* Options are: eTSEC[0-1] */
|
||||
#define CONFIG_ETHPRIME "eTSEC0"
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 256 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
|
||||
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs}" \
|
||||
" console=${consoledev},${baudrate}\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"addmisc=setenv bootargs ${bootargs}\0" \
|
||||
"kernel_addr=FE080000\0" \
|
||||
"fdt_addr=FE280000\0" \
|
||||
"ramdisk_addr=FE290000\0" \
|
||||
"u-boot=mpc8308rdb/u-boot.bin\0" \
|
||||
"kernel_addr_r=1000000\0" \
|
||||
"fdt_addr_r=C00000\0" \
|
||||
"hostname=mpc8308rdb\0" \
|
||||
"bootfile=mpc8308rdb/uImage\0" \
|
||||
"fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
|
||||
"rootpath=/opt/eldk-4.2/ppc_6xx\0" \
|
||||
"flash_self=run ramargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr} - ${fdt_addr}\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
|
||||
"tftp ${fdt_addr_r} ${fdtfile};" \
|
||||
"run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
||||
"bootcmd=run flash_self\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
|
||||
" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
|
||||
" +${filesize};cp.b ${fileaddr} " \
|
||||
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
|
||||
"upd=run load update\0" \
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user