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ppc: Remove T2081QDS board and ARCH_T2081 support 

This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.  It is also the only ARCH_T2081 board so remove that support
as well.

Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-02-20 20:06:21 -05:00
parent bf85995a25
commit 2322b9568f
18 changed files with 7 additions and 582 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -210,14 +210,6 @@ config TARGET_T2080RDB
imply CMD_SATA
imply PANIC_HANG
config TARGET_T2081QDS
bool "Support T2081QDS"
select ARCH_T2081
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
config TARGET_T4160RDB
bool "Support T4160RDB"
select ARCH_T4160
@ -928,29 +920,6 @@ config ARCH_T2080
imply CMD_REGINFO
imply FSL_SATA
config ARCH_T2081
bool
select E500MC
select E6500
select FSL_LAW
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
select SYS_FSL_ERRATUM_A007186
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
select FSL_IFC
imply CMD_NAND
imply CMD_REGINFO
config ARCH_T4160
bool
select E500MC
@ -1052,8 +1021,7 @@ config MAX_CPUS
ARCH_P5040 || \
ARCH_T1040 || \
ARCH_T1042 || \
ARCH_T2080 || \
ARCH_T2081
ARCH_T2080
default 2 if ARCH_B4420 || \
ARCH_BSC9132 || \
ARCH_MPC8572 || \
@ -1110,7 +1078,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_T1040 || \
ARCH_T1042 || \
ARCH_T2080 || \
ARCH_T2081 || \
ARCH_T4160 || \
ARCH_T4240
default 0xe0000000 if ARCH_QEMU_E500
@ -1297,7 +1264,6 @@ config SYS_FSL_NUM_LAWS
ARCH_P5020 || \
ARCH_P5040 || \
ARCH_T2080 || \
ARCH_T2081 || \
ARCH_T4160 || \
ARCH_T4240
default 16 if ARCH_T1023 || \

2
arch/powerpc/cpu/mpc85xx/Makefile
View File

@ -51,7 +51,6 @@ obj-$(CONFIG_ARCH_T1042) += t1040_ids.o
obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
obj-$(CONFIG_ARCH_T2081) += t2080_ids.o
obj-$(CONFIG_QE) += qe_io.o
@ -90,7 +89,6 @@ obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o
obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
obj-$(CONFIG_ARCH_T2081) += t2080_serdes.o
obj-y += cpu.o
obj-y += cpu_init.o

4
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -127,7 +127,7 @@ void get_sys_info(sys_info_t *sys_info)
* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
*/
#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
defined(CONFIG_ARCH_T2080)
svr = get_svr();
switch (SVR_SOC_VER(svr)) {
case SVR_T4240:
@ -198,7 +198,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
defined(CONFIG_ARCH_T2080)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)

4
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
View File

@ -160,7 +160,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
{}
};
#ifndef CONFIG_ARCH_T2081
static const struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
@ -176,13 +175,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
{}
};
#endif
static const struct serdes_config *serdes_cfg_tbl[] = {
serdes1_cfg_tbl,
#ifndef CONFIG_ARCH_T2081
serdes2_cfg_tbl,
#endif
};
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)

5
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -364,7 +364,7 @@
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#elif defined(CONFIG_ARCH_T2080)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
@ -381,9 +381,6 @@
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_ARCH_T2081)
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
#endif
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_PME_PLAT_CLK_DIV 1

4
arch/powerpc/include/asm/immap_85xx.h
View File

@ -1808,7 +1808,7 @@ typedef struct ccsr_gur {
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#elif defined(CONFIG_ARCH_T2080)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
@ -1880,7 +1880,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
#endif
#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#if defined(CONFIG_ARCH_T2080)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000

2
board/freescale/t208xqds/Kconfig
View File

@ -1,4 +1,4 @@
if TARGET_T2080QDS || TARGET_T2081QDS
if TARGET_T2080QDS
config SYS_BOARD
default "t208xqds"

1
board/freescale/t208xqds/Makefile
View File

@ -8,7 +8,6 @@ ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
obj-$(CONFIG_TARGET_T2081QDS) += t208xqds.o eth_t208xqds.o
obj-$(CONFIG_PCI) += pci.o
endif

106
board/freescale/t208xqds/eth_t208xqds.c
View File

@ -42,13 +42,6 @@
#define EMI1_SLOT4 4
#define EMI1_SLOT5 5
#define EMI2 7
#elif defined(CONFIG_TARGET_T2081QDS)
#define EMI1_SLOT2 3
#define EMI1_SLOT3 4
#define EMI1_SLOT5 5
#define EMI1_SLOT6 6
#define EMI1_SLOT7 7
#define EMI2 8
#endif
#define PCCR1_SGMIIA_KX_MASK 0x00008000
@ -72,24 +65,12 @@ static const char * const mdio_names[] = {
"T2080QDS_MDIO_SLOT5",
"T2080QDS_MDIO_SLOT2",
"T2080QDS_MDIO_10GC",
#elif defined(CONFIG_TARGET_T2081QDS)
"T2081QDS_MDIO_RGMII1",
"T2081QDS_MDIO_RGMII2",
"T2081QDS_MDIO_SLOT1",
"T2081QDS_MDIO_SLOT2",
"T2081QDS_MDIO_SLOT3",
"T2081QDS_MDIO_SLOT5",
"T2081QDS_MDIO_SLOT6",
"T2081QDS_MDIO_SLOT7",
"T2081QDS_MDIO_10GC",
#endif
};
/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
#if defined(CONFIG_TARGET_T2080QDS)
static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
#elif defined(CONFIG_TARGET_T2081QDS)
static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
#endif
static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
@ -316,35 +297,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
fdt_status_okay_by_alias(fdt, "emi1_slot2");
}
break;
#elif defined(CONFIG_TARGET_T2081QDS)
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC5:
case FM1_DTSEC6:
case FM1_DTSEC9:
case FM1_DTSEC10:
if (mdio_mux[port] == EMI1_SLOT2) {
sprintf(alias, "phy_sgmii_s2_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
fdt_status_okay_by_alias(fdt, "emi1_slot2");
} else if (mdio_mux[port] == EMI1_SLOT3) {
sprintf(alias, "phy_sgmii_s3_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
fdt_status_okay_by_alias(fdt, "emi1_slot3");
} else if (mdio_mux[port] == EMI1_SLOT5) {
sprintf(alias, "phy_sgmii_s5_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
fdt_status_okay_by_alias(fdt, "emi1_slot5");
} else if (mdio_mux[port] == EMI1_SLOT6) {
sprintf(alias, "phy_sgmii_s6_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
fdt_status_okay_by_alias(fdt, "emi1_slot6");
} else if (mdio_mux[port] == EMI1_SLOT7) {
sprintf(alias, "phy_sgmii_s7_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
fdt_status_okay_by_alias(fdt, "emi1_slot7");
}
break;
#endif
default:
break;
@ -495,30 +447,6 @@ static void initialize_lane_to_slot(void)
lane_to_slot[6] = 3;
lane_to_slot[7] = 3;
break;
#elif defined(CONFIG_TARGET_T2081QDS)
case 0x6b:
lane_to_slot[4] = 1;
lane_to_slot[5] = 3;
lane_to_slot[6] = 3;
lane_to_slot[7] = 3;
break;
case 0xca:
case 0xcb:
lane_to_slot[1] = 7;
lane_to_slot[2] = 6;
lane_to_slot[3] = 5;
lane_to_slot[5] = 3;
lane_to_slot[6] = 3;
lane_to_slot[7] = 3;
break;
case 0xf2:
lane_to_slot[1] = 7;
lane_to_slot[2] = 7;
lane_to_slot[3] = 7;
lane_to_slot[5] = 4;
lane_to_slot[6] = 3;
lane_to_slot[7] = 7;
break;
#endif
default:
break;
@ -570,10 +498,6 @@ int board_eth_init(struct bd_info *bis)
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
#endif
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
#if defined(CONFIG_TARGET_T2081QDS)
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
#endif
t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
/* Set the two on-board RGMII PHY address */
@ -689,19 +613,6 @@ int board_eth_init(struct bd_info *bis)
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
#elif defined(CONFIG_TARGET_T2081QDS)
case 0xca:
case 0xcb:
/* SGMII in Slot3 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
/* SGMII in Slot5 */
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
/* SGMII in Slot6 */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
/* SGMII in Slot7 */
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
break;
#endif
case 0xf2:
/* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
@ -745,23 +656,6 @@ int board_eth_init(struct bd_info *bis)
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
#if defined(CONFIG_TARGET_T2081QDS)
case 5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 6:
mdio_mux[i] = EMI1_SLOT6;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 7:
mdio_mux[i] = EMI1_SLOT7;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
#endif
}
break;
case PHY_INTERFACE_MODE_RGMII:

70
board/freescale/t208xqds/t208xqds.c
View File

@ -209,76 +209,6 @@ int brd_mux_lane_to_slot(void)
*/
QIXIS_WRITE(brdcfg[12], 0x1a);
break;
#elif defined(CONFIG_TARGET_T2081QDS)
case 0x50:
case 0x51:
/* SD1(A:D) => SLOT2 XAUI
* SD1(E) => SLOT1 PCIe4 x1
* SD1(F:H) => SLOT3 SGMII
*/
QIXIS_WRITE(brdcfg[12], 0x98);
QIXIS_WRITE(brdcfg[13], 0x70);
break;
case 0x6a:
case 0x6b:
/* SD1(A:D) => XFI SFP Module
* SD1(E) => SLOT1 PCIe4 x1
* SD1(F:H) => SLOT3 SGMII
*/
QIXIS_WRITE(brdcfg[12], 0x80);
QIXIS_WRITE(brdcfg[13], 0x70);
break;
case 0x6c:
case 0x6d:
/* SD1(A:B) => XFI SFP Module
* SD1(C:D) => SLOT2 SGMII
* SD1(E:H) => SLOT1 PCIe4 x4
*/
QIXIS_WRITE(brdcfg[12], 0xe8);
QIXIS_WRITE(brdcfg[13], 0x0);
break;
case 0xaa:
case 0xab:
/* SD1(A:D) => SLOT2 PCIe3 x4
* SD1(F:H) => SLOT1 SGMI4 x4
*/
QIXIS_WRITE(brdcfg[12], 0xf8);
QIXIS_WRITE(brdcfg[13], 0x0);
break;
case 0xca:
case 0xcb:
/* SD1(A) => SLOT2 PCIe3 x1
* SD1(B) => SLOT7 SGMII
* SD1(C) => SLOT6 SGMII
* SD1(D) => SLOT5 SGMII
* SD1(E) => SLOT1 PCIe4 x1
* SD1(F:H) => SLOT3 SGMII
*/
QIXIS_WRITE(brdcfg[12], 0x80);
QIXIS_WRITE(brdcfg[13], 0x70);
break;
case 0xde:
case 0xdf:
/* SD1(A:D) => SLOT2 PCIe3 x4
* SD1(E) => SLOT1 PCIe4 x1
* SD1(F) => SLOT4 PCIe1 x1
* SD1(G) => SLOT3 PCIe2 x1
* SD1(H) => SLOT7 SGMII
*/
QIXIS_WRITE(brdcfg[12], 0x98);
QIXIS_WRITE(brdcfg[13], 0x25);
break;
case 0xf2:
/* SD1(A) => SLOT2 PCIe3 x1
* SD1(B:D) => SLOT7 SGMII
* SD1(E) => SLOT1 PCIe4 x1
* SD1(F) => SLOT4 PCIe1 x1
* SD1(G) => SLOT3 PCIe2 x1
* SD1(H) => SLOT7 SGMII
*/
QIXIS_WRITE(brdcfg[12], 0x81);
QIXIS_WRITE(brdcfg[13], 0xa5);
break;
#endif
default:
printf("WARNING: unsupported for SerDes1 Protocol %d\n",

78
configs/T2081QDS_NAND_defconfig
View File

@ -1,78 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x00201000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x140000
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2081QDS=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_BOOT=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y

75
configs/T2081QDS_SDCARD_defconfig
View File

@ -1,75 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x00201000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2081QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y

77
configs/T2081QDS_SPIFLASH_defconfig
View File

@ -1,77 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x00201000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2081QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y

54
configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
View File

@ -1,54 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2081QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_ENV_ADDR=0xFFE20000
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y

62
configs/T2081QDS_defconfig
View File

@ -1,62 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2081QDS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_OF_LIBFDT=y

1
drivers/net/Kconfig
View File

@ -721,7 +721,6 @@ config SYS_DPAA_QBMAN
ARCH_T1040 || \
ARCH_T1042 || \
ARCH_T2080 || \
ARCH_T2081 || \
ARCH_T4240 || \
ARCH_T4160 || \
ARCH_P4080 || \

1
drivers/net/fm/Makefile
View File

@ -27,7 +27,6 @@ obj-$(CONFIG_ARCH_T1042) += t1040.o
obj-$(CONFIG_ARCH_T1023) += t1024.o
obj-$(CONFIG_ARCH_T1024) += t1024.o
obj-$(CONFIG_ARCH_T2080) += t2080.o
obj-$(CONFIG_ARCH_T2081) += t2080.o
obj-$(CONFIG_ARCH_T4240) += t4240.o
obj-$(CONFIG_ARCH_T4160) += t4240.o
obj-$(CONFIG_ARCH_B4420) += b4860.o

7
include/configs/T208xQDS.h
View File

@ -19,7 +19,6 @@
#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
#elif defined(CONFIG_ARCH_T2081)
#endif
/* High Level Configuration Options */
@ -50,8 +49,6 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
#elif defined(CONFIG_ARCH_T2081)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
#endif
#endif
@ -67,8 +64,6 @@
#endif
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
#elif defined(CONFIG_ARCH_T2081)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
#endif
#endif
@ -83,8 +78,6 @@
#endif
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
#elif defined(CONFIG_ARCH_T2081)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
#endif
#endif