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https://github.com/brain-hackers/u-boot-brain
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mx6cuboxi: Convert to DM_ETH
Migration to DM_ETH is mandatory, so convert mx6cuboxi to Ethernet Driver Model. This also brings the benefit of restoring Ethernet functionality. Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Fabio Estevam
Stefano Babic
parent
db86e6c66a
commit
d8da22c5db
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@ -17,7 +17,6 @@
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <net.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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@ -33,8 +32,6 @@
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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@ -52,16 +49,6 @@ DECLARE_GLOBAL_DATA_PTR;
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define ETH_PHY_RESET IMX_GPIO_NR(4, 15)
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#define USB_H1_VBUS IMX_GPIO_NR(1, 0)
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enum board_type {
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@ -237,110 +224,6 @@ int board_mmc_init(bd_t *bis)
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return 0;
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}
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static iomux_v3_cfg_t const enet_pads[] = {
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IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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/* AR8035 reset */
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IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
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/* AR8035 interrupt */
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IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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/* GPIO16 -> AR8035 25MHz */
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IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
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IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
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IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
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IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
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IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
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IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
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IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
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};
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static void setup_iomux_enet(void)
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{
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struct gpio_desc desc;
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int ret;
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SETUP_IOMUX_PADS(enet_pads);
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ret = dm_gpio_lookup_name("GPIO4_15", &desc);
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if (ret) {
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printf("%s: phy reset lookup failed\n", __func__);
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return;
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}
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ret = dm_gpio_request(&desc, "phy-reset");
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if (ret) {
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printf("%s: phy reset request failed\n", __func__);
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return;
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}
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gpio_direction_output(ETH_PHY_RESET, 0);
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mdelay(10);
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gpio_set_value(ETH_PHY_RESET, 1);
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udelay(100);
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gpio_free_list_nodev(&desc, 1);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
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#define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4))
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int board_eth_init(bd_t *bis)
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{
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struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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struct mii_dev *bus;
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struct phy_device *phydev;
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int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
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if (ret)
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return ret;
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/* set gpr1[ENET_CLK_SEL] */
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setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
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setup_iomux_enet();
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bus = fec_get_miibus(IMX_FEC_BASE, -1);
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if (!bus)
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return -EINVAL;
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phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
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if (!phydev) {
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ret = -EINVAL;
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goto free_bus;
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}
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debug("using phy at address %d\n", phydev->addr);
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ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
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if (ret)
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goto free_phydev;
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return 0;
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free_phydev:
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free(phydev);
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free_bus:
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free(bus);
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return ret;
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}
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#ifdef CONFIG_VIDEO_IPUV3
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static void do_enable_hdmi(struct display_info_t const *dev)
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{
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@ -433,6 +316,21 @@ static int setup_display(void)
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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static int setup_fec(void)
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{
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struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int ret;
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ret = enable_fec_anatop_clock(0, ENET_25MHZ);
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if (ret)
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return ret;
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/* set gpr1[ENET_CLK_SEL] */
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setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
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return 0;
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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@ -440,6 +338,8 @@ int board_early_init_f(void)
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#ifdef CONFIG_CMD_SATA
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setup_sata();
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#endif
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setup_fec();
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return 0;
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}
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@ -50,6 +50,9 @@ CONFIG_DM_MMC=y
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CONFIG_FSL_USDHC=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_DM_ETH=y
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CONFIG_FEC_MXC=y
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CONFIG_RGMII=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -29,12 +29,6 @@
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#define CONFIG_LBA48
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#endif
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/* Ethernet Configuration */
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_FEC_MXC_PHYADDR 0
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/* Framebuffer */
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SPLASH_SCREEN
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