Revert "Revert "mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output""
This reverts commit f132aab403
.
Since this revert commit a imx7ulp board (Sharp Brain PW-B1 model) did not initialize SD card
in both SPL as well as U-Boot proper.
Fix this regression by reverting the offending commit for now.
This commit is contained in:
parent
467a6e6d35
commit
d8c99c87a4
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@ -653,7 +653,10 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
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clk = (pre_div << 8) | (div << 4);
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clk = (pre_div << 8) | (div << 4);
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#ifdef CONFIG_FSL_USDHC
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#ifdef CONFIG_FSL_USDHC
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esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
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esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
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ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
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if (ret)
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pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n");
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#else
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#else
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esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
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esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
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#endif
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#endif
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@ -665,7 +668,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
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pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
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pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
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#ifdef CONFIG_FSL_USDHC
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#ifdef CONFIG_FSL_USDHC
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esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
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esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
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#else
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#else
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esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
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esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
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#endif
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#endif
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@ -720,8 +723,14 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
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struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
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struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
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struct fsl_esdhc *regs = priv->esdhc_regs;
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struct fsl_esdhc *regs = priv->esdhc_regs;
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u32 val;
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u32 val;
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u32 tmp;
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int ret;
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if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
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if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
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esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
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ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
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if (ret)
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pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n");
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esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
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esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
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/*
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/*
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@ -739,6 +748,7 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
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pr_warn("HS400 strobe DLL status REF not lock!\n");
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pr_warn("HS400 strobe DLL status REF not lock!\n");
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if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
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if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
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pr_warn("HS400 strobe DLL status SLV not lock!\n");
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pr_warn("HS400 strobe DLL status SLV not lock!\n");
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esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
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}
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}
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}
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}
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@ -970,14 +980,18 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
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#ifdef MMC_SUPPORTS_TUNING
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#ifdef MMC_SUPPORTS_TUNING
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if (mmc->clk_disable) {
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if (mmc->clk_disable) {
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#ifdef CONFIG_FSL_USDHC
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#ifdef CONFIG_FSL_USDHC
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esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
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u32 tmp;
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esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
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ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
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if (ret)
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pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n");
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#else
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#else
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esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
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esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
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#endif
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#endif
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} else {
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} else {
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#ifdef CONFIG_FSL_USDHC
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#ifdef CONFIG_FSL_USDHC
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esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
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esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
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VENDORSPEC_CKEN);
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#else
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#else
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esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
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esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
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#endif
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#endif
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@ -1053,7 +1067,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
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#ifndef CONFIG_FSL_USDHC
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#ifndef CONFIG_FSL_USDHC
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esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
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esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
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#else
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#else
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esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
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esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
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#endif
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#endif
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/* Set the initial clock speed */
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/* Set the initial clock speed */
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@ -1191,8 +1205,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
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esdhc_write32(®s->autoc12err, 0);
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esdhc_write32(®s->autoc12err, 0);
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esdhc_write32(®s->clktunectrlstatus, 0);
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esdhc_write32(®s->clktunectrlstatus, 0);
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#else
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#else
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esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
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esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
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VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
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#endif
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#endif
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if (priv->vs18_enable)
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if (priv->vs18_enable)
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@ -39,6 +39,7 @@
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#define VENDORSPEC_HCKEN 0x00001000
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#define VENDORSPEC_HCKEN 0x00001000
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#define VENDORSPEC_IPGEN 0x00000800
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#define VENDORSPEC_IPGEN 0x00000800
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#define VENDORSPEC_INIT 0x20007809
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#define VENDORSPEC_INIT 0x20007809
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#define VENDORSPEC_FRC_SDCLK_ON 0x00000100
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#define IRQSTAT 0x0002e030
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#define IRQSTAT 0x0002e030
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#define IRQSTAT_DMAE (0x10000000)
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#define IRQSTAT_DMAE (0x10000000)
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@ -96,6 +97,7 @@
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#define PRSSTAT_CINS (0x00010000)
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#define PRSSTAT_CINS (0x00010000)
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#define PRSSTAT_BREN (0x00000800)
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#define PRSSTAT_BREN (0x00000800)
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#define PRSSTAT_BWEN (0x00000400)
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#define PRSSTAT_BWEN (0x00000400)
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#define PRSSTAT_SDOFF (0x00000080)
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#define PRSSTAT_SDSTB (0X00000008)
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#define PRSSTAT_SDSTB (0X00000008)
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#define PRSSTAT_DLA (0x00000004)
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#define PRSSTAT_DLA (0x00000004)
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#define PRSSTAT_CICHB (0x00000002)
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#define PRSSTAT_CICHB (0x00000002)
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