imx: ventana: enable dm support for PCI and FEC ethernet
Enable driver model support for FEC ethernet which allows us to remove the iomux and board_eth_init function. Replace the toggling of the ethernet phy reset with dt configuration. Enable driver model support for PCI which allows us to remove the eth1000_initialize() call. Additionally enable PCI_INIT_R to scan for PCI devices on init such as the e1000 that is present on the GW552x. Convert board_pci_fixup to use dm callback and remove pcidisable env variable which is not supported for DM_PCI and thus leave PCI always enabled during init. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This commit is contained in:
parent
d9a7f1a913
commit
cd18f1e6e6
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@ -129,6 +129,8 @@
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pinctrl-0 = <&pinctrl_enet>;
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii-id";
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phy-mode = "rgmii-id";
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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phy-reset-post-delay = <100>;
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status = "okay";
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status = "okay";
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};
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};
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@ -195,6 +195,8 @@
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pinctrl-0 = <&pinctrl_enet>;
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii-id";
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phy-mode = "rgmii-id";
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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phy-reset-post-delay = <100>;
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status = "okay";
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status = "okay";
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};
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};
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@ -188,6 +188,8 @@
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pinctrl-0 = <&pinctrl_enet>;
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii-id";
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phy-mode = "rgmii-id";
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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phy-reset-post-delay = <100>;
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status = "okay";
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status = "okay";
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};
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};
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@ -597,6 +599,7 @@
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
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MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
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MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
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>;
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>;
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};
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};
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@ -225,6 +225,8 @@
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pinctrl-0 = <&pinctrl_enet>;
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii-id";
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phy-mode = "rgmii-id";
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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phy-reset-post-delay = <100>;
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status = "okay";
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status = "okay";
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};
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};
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@ -675,6 +677,7 @@
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
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MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
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MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
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>;
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>;
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};
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};
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@ -279,6 +279,8 @@
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pinctrl-0 = <&pinctrl_enet>;
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii-id";
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phy-mode = "rgmii-id";
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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phy-reset-post-delay = <100>;
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status = "okay";
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status = "okay";
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};
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};
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@ -223,6 +223,9 @@
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pinctrl-names = "default";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii-id";
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phy-mode = "rgmii-id";
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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phy-reset-post-delay = <100>;
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status = "okay";
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status = "okay";
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};
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};
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@ -200,6 +200,9 @@
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pinctrl-names = "default";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii-id";
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phy-mode = "rgmii-id";
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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phy-reset-post-delay = <100>;
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status = "okay";
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status = "okay";
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fixed-link {
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fixed-link {
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@ -131,6 +131,8 @@
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pinctrl-0 = <&pinctrl_enet>;
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii-id";
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phy-mode = "rgmii-id";
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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phy-reset-post-delay = <100>;
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status = "okay";
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status = "okay";
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};
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};
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@ -146,6 +146,9 @@
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pinctrl-names = "default";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii-id";
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phy-mode = "rgmii-id";
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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phy-reset-post-delay = <100>;
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status = "okay";
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status = "okay";
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};
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};
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@ -141,6 +141,9 @@
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pinctrl-names = "default";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii-id";
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phy-mode = "rgmii-id";
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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phy-reset-post-delay = <100>;
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status = "okay";
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status = "okay";
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};
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};
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@ -426,6 +429,7 @@
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
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>;
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>;
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};
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};
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@ -121,6 +121,9 @@
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pinctrl-names = "default";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii-id";
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phy-mode = "rgmii-id";
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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phy-reset-post-delay = <100>;
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status = "okay";
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status = "okay";
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};
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};
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@ -11,7 +11,6 @@
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#include "ventana_eeprom.h"
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#include "ventana_eeprom.h"
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/* GPIO's common to all baseboards */
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/* GPIO's common to all baseboards */
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#define GP_PHY_RST IMX_GPIO_NR(1, 30)
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#define GP_RS232_EN IMX_GPIO_NR(2, 11)
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#define GP_RS232_EN IMX_GPIO_NR(2, 11)
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#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
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#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
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@ -31,7 +31,6 @@
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#include <linux/ctype.h>
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#include <linux/ctype.h>
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#include <miiphy.h>
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#include <miiphy.h>
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#include <mtd_node.h>
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#include <mtd_node.h>
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#include <netdev.h>
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#include <pci.h>
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#include <pci.h>
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#include <linux/delay.h>
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#include <linux/delay.h>
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#include <linux/libfdt.h>
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#include <linux/libfdt.h>
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struct ventana_board_info ventana_info;
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struct ventana_board_info ventana_info;
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static int board_type;
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static int board_type;
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/* ENET */
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static iomux_v3_cfg_t const enet_pads[] = {
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IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
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MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
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MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
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MUX_PAD_CTRL(ENET_PAD_CTRL)),
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/* PHY nRST */
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IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
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};
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static void setup_iomux_enet(int gpio)
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{
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SETUP_IOMUX_PADS(enet_pads);
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/* toggle PHY_RST# */
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gpio_request(gpio, "phy_rst#");
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gpio_direction_output(gpio, 0);
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mdelay(10);
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gpio_set_value(gpio, 1);
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mdelay(100);
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}
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#ifdef CONFIG_USB_EHCI_MX6
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#ifdef CONFIG_USB_EHCI_MX6
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/* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */
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/* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */
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int board_ehci_hcd_init(int port)
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int board_ehci_hcd_init(int port)
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}
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}
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#endif // CONFIG_MV88E61XX_SWITCH
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#endif // CONFIG_MV88E61XX_SWITCH
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int board_eth_init(struct bd_info *bis)
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{
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#ifdef CONFIG_FEC_MXC
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struct ventana_board_info *info = &ventana_info;
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if (test_bit(EECONFIG_ETH0, info->config)) {
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setup_iomux_enet(GP_PHY_RST);
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cpu_eth_init(bis);
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}
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#endif
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#ifdef CONFIG_E1000
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e1000_initialize(bis);
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#endif
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#ifdef CONFIG_CI_UDC
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/* For otg ethernet*/
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usb_eth_initialize(bis);
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#endif
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/* default to the first detected enet dev */
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if (!env_get("ethprime")) {
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struct eth_device *dev = eth_get_dev_by_index(0);
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if (dev) {
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env_set("ethprime", dev->name);
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printf("set ethprime to %s\n", env_get("ethprime"));
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}
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}
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return 0;
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}
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#if defined(CONFIG_VIDEO_IPUV3)
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#if defined(CONFIG_VIDEO_IPUV3)
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static void enable_hdmi(struct display_info_t const *dev)
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static void enable_hdmi(struct display_info_t const *dev)
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{
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{
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imx_enable_hdmi_phy();
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imx_enable_hdmi_phy();
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return 0;
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return 0;
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}
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}
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#if defined(CONFIG_CMD_PCI)
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int imx6_pcie_toggle_reset(void)
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int imx6_pcie_toggle_reset(void)
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{
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{
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if (board_type < GW_UNKNOWN) {
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if (board_type < GW_UNKNOWN) {
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@ -448,6 +377,7 @@ int imx6_pcie_toggle_reset(void)
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#define MAX_PCI_DEVS 32
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#define MAX_PCI_DEVS 32
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struct pci_dev {
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struct pci_dev {
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pci_dev_t devfn;
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pci_dev_t devfn;
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struct udevice *dev;
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unsigned short vendor;
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unsigned short vendor;
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unsigned short device;
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unsigned short device;
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unsigned short class;
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unsigned short class;
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@ -458,18 +388,21 @@ struct pci_dev pci_devs[MAX_PCI_DEVS];
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int pci_devno;
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int pci_devno;
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int pci_bridgeno;
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int pci_bridgeno;
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void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
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void board_pci_fixup_dev(struct udevice *bus, struct udevice *udev)
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unsigned short vendor, unsigned short device,
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unsigned short class)
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{
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{
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int i;
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struct pci_child_plat *pdata = dev_get_parent_plat(udev);
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u32 dw;
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struct pci_dev *pdev = &pci_devs[pci_devno++];
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struct pci_dev *pdev = &pci_devs[pci_devno++];
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unsigned short vendor = pdata->vendor;
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unsigned short device = pdata->device;
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unsigned int class = pdata->class;
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pci_dev_t dev = dm_pci_get_bdf(udev);
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int i;
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debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
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debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
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PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
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PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
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/* store array of devs for later use in device-tree fixup */
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/* store array of devs for later use in device-tree fixup */
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pdev->dev = udev;
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pdev->devfn = dev;
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pdev->devfn = dev;
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pdev->vendor = vendor;
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pdev->vendor = vendor;
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pdev->device = device;
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pdev->device = device;
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@ -496,19 +429,19 @@ void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
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if (vendor == PCI_VENDOR_ID_PLX &&
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if (vendor == PCI_VENDOR_ID_PLX &&
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||||||
(device & 0xfff0) == 0x8600 &&
|
(device & 0xfff0) == 0x8600 &&
|
||||||
PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
|
PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
|
||||||
|
ulong val;
|
||||||
debug("configuring PLX 860X downstream PERST#\n");
|
debug("configuring PLX 860X downstream PERST#\n");
|
||||||
pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
|
pci_bus_read_config(bus, dev, 0x62c, &val, PCI_SIZE_32);
|
||||||
dw |= 0xaaa8; /* GPIO1-7 outputs */
|
val |= 0xaaa8; /* GPIO1-7 outputs */
|
||||||
pci_hose_write_config_dword(hose, dev, 0x62c, dw);
|
pci_bus_write_config(bus, dev, 0x62c, val, PCI_SIZE_32);
|
||||||
|
|
||||||
pci_hose_read_config_dword(hose, dev, 0x644, &dw);
|
pci_bus_read_config(bus, dev, 0x644, &val, PCI_SIZE_32);
|
||||||
dw |= 0xfe; /* GPIO1-7 output high */
|
val |= 0xfe; /* GPIO1-7 output high */
|
||||||
pci_hose_write_config_dword(hose, dev, 0x644, dw);
|
pci_bus_write_config(bus, dev, 0x644, val, PCI_SIZE_32);
|
||||||
|
|
||||||
mdelay(100);
|
mdelay(100);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_CMD_PCI */
|
|
||||||
|
|
||||||
#ifdef CONFIG_SERIAL_TAG
|
#ifdef CONFIG_SERIAL_TAG
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -34,6 +34,7 @@ CONFIG_USE_PREBOOT=y
|
||||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||||
CONFIG_BOARD_EARLY_INIT_F=y
|
CONFIG_BOARD_EARLY_INIT_F=y
|
||||||
CONFIG_MISC_INIT_R=y
|
CONFIG_MISC_INIT_R=y
|
||||||
|
CONFIG_PCI_INIT_R=y
|
||||||
CONFIG_SPL_BOARD_INIT=y
|
CONFIG_SPL_BOARD_INIT=y
|
||||||
CONFIG_SPL_STACK_R=y
|
CONFIG_SPL_STACK_R=y
|
||||||
CONFIG_SPL_FIT_IMAGE_TINY=y
|
CONFIG_SPL_FIT_IMAGE_TINY=y
|
||||||
|
@ -85,9 +86,13 @@ CONFIG_SUPPORT_EMMC_BOOT=y
|
||||||
CONFIG_FSL_USDHC=y
|
CONFIG_FSL_USDHC=y
|
||||||
CONFIG_MTD=y
|
CONFIG_MTD=y
|
||||||
CONFIG_PHYLIB=y
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_DM_MDIO=y
|
||||||
CONFIG_E1000=y
|
CONFIG_E1000=y
|
||||||
|
CONFIG_FEC_MXC=y
|
||||||
CONFIG_MII=y
|
CONFIG_MII=y
|
||||||
CONFIG_PCI=y
|
CONFIG_PCI=y
|
||||||
|
CONFIG_DM_PCI=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
CONFIG_PINCTRL_IMX6=y
|
CONFIG_PINCTRL_IMX6=y
|
||||||
CONFIG_DM_REGULATOR=y
|
CONFIG_DM_REGULATOR=y
|
||||||
|
|
|
@ -34,6 +34,7 @@ CONFIG_USE_PREBOOT=y
|
||||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||||
CONFIG_BOARD_EARLY_INIT_F=y
|
CONFIG_BOARD_EARLY_INIT_F=y
|
||||||
CONFIG_MISC_INIT_R=y
|
CONFIG_MISC_INIT_R=y
|
||||||
|
CONFIG_PCI_INIT_R=y
|
||||||
CONFIG_SPL_BOARD_INIT=y
|
CONFIG_SPL_BOARD_INIT=y
|
||||||
CONFIG_SPL_STACK_R=y
|
CONFIG_SPL_STACK_R=y
|
||||||
CONFIG_SPL_FIT_IMAGE_TINY=y
|
CONFIG_SPL_FIT_IMAGE_TINY=y
|
||||||
|
@ -89,9 +90,13 @@ CONFIG_MV88E61XX_SWITCH=y
|
||||||
CONFIG_MV88E61XX_CPU_PORT=5
|
CONFIG_MV88E61XX_CPU_PORT=5
|
||||||
CONFIG_MV88E61XX_PHY_PORTS=0xf
|
CONFIG_MV88E61XX_PHY_PORTS=0xf
|
||||||
CONFIG_MV88E61XX_FIXED_PORTS=0x0
|
CONFIG_MV88E61XX_FIXED_PORTS=0x0
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_DM_MDIO=y
|
||||||
CONFIG_E1000=y
|
CONFIG_E1000=y
|
||||||
|
CONFIG_FEC_MXC=y
|
||||||
CONFIG_MII=y
|
CONFIG_MII=y
|
||||||
CONFIG_PCI=y
|
CONFIG_PCI=y
|
||||||
|
CONFIG_DM_PCI=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
CONFIG_PINCTRL_IMX6=y
|
CONFIG_PINCTRL_IMX6=y
|
||||||
CONFIG_DM_REGULATOR=y
|
CONFIG_DM_REGULATOR=y
|
||||||
|
|
|
@ -34,6 +34,7 @@ CONFIG_USE_PREBOOT=y
|
||||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||||
CONFIG_BOARD_EARLY_INIT_F=y
|
CONFIG_BOARD_EARLY_INIT_F=y
|
||||||
CONFIG_MISC_INIT_R=y
|
CONFIG_MISC_INIT_R=y
|
||||||
|
CONFIG_PCI_INIT_R=y
|
||||||
CONFIG_SPL_BOARD_INIT=y
|
CONFIG_SPL_BOARD_INIT=y
|
||||||
CONFIG_SPL_STACK_R=y
|
CONFIG_SPL_STACK_R=y
|
||||||
CONFIG_SPL_FIT_IMAGE_TINY=y
|
CONFIG_SPL_FIT_IMAGE_TINY=y
|
||||||
|
@ -91,9 +92,13 @@ CONFIG_MTD_RAW_NAND=y
|
||||||
CONFIG_NAND_MXS=y
|
CONFIG_NAND_MXS=y
|
||||||
CONFIG_NAND_MXS_DT=y
|
CONFIG_NAND_MXS_DT=y
|
||||||
CONFIG_PHYLIB=y
|
CONFIG_PHYLIB=y
|
||||||
|
CONFIG_DM_ETH=y
|
||||||
|
CONFIG_DM_MDIO=y
|
||||||
CONFIG_E1000=y
|
CONFIG_E1000=y
|
||||||
|
CONFIG_FEC_MXC=y
|
||||||
CONFIG_MII=y
|
CONFIG_MII=y
|
||||||
CONFIG_PCI=y
|
CONFIG_PCI=y
|
||||||
|
CONFIG_DM_PCI=y
|
||||||
CONFIG_PINCTRL=y
|
CONFIG_PINCTRL=y
|
||||||
CONFIG_PINCTRL_IMX6=y
|
CONFIG_PINCTRL_IMX6=y
|
||||||
CONFIG_DM_REGULATOR=y
|
CONFIG_DM_REGULATOR=y
|
||||||
|
|
|
@ -65,8 +65,6 @@
|
||||||
* PCI express
|
* PCI express
|
||||||
*/
|
*/
|
||||||
#ifdef CONFIG_CMD_PCI
|
#ifdef CONFIG_CMD_PCI
|
||||||
#define CONFIG_PCI_SCAN_SHOW
|
|
||||||
#define CONFIG_PCI_FIXUP_DEV
|
|
||||||
#define CONFIG_PCIE_IMX
|
#define CONFIG_PCIE_IMX
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -82,13 +80,6 @@
|
||||||
|
|
||||||
/* Various command support */
|
/* Various command support */
|
||||||
|
|
||||||
/* Ethernet support */
|
|
||||||
#define CONFIG_FEC_MXC
|
|
||||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
|
||||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
|
||||||
#define CONFIG_FEC_MXC_PHYADDR 0
|
|
||||||
#define CONFIG_ARP_TIMEOUT 200UL
|
|
||||||
|
|
||||||
/* USB Configs */
|
/* USB Configs */
|
||||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
|
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
|
||||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||||
|
@ -129,7 +120,6 @@
|
||||||
#define CONFIG_SERVERIP 192.168.1.146
|
#define CONFIG_SERVERIP 192.168.1.146
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
|
#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
|
||||||
"pcidisable=1\0" \
|
|
||||||
"splashpos=m,m\0" \
|
"splashpos=m,m\0" \
|
||||||
"usb_pgood_delay=2000\0" \
|
"usb_pgood_delay=2000\0" \
|
||||||
"console=ttymxc1\0" \
|
"console=ttymxc1\0" \
|
||||||
|
|
Loading…
Reference in New Issue