dm: test: clk: add the test for the ccf gated clock

Unlike the other clock types, in the case of the gated clock, a new
driver has been developed which does not use the registering routine
provided by the common clock framework.
The addition of the ecspi0 clock to sandbox therefore allows testing
the ccf gate clock.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Dario Binacchi 2020-04-13 14:36:26 +02:00 committed by Lukasz Majewski
parent 32f462ba3b
commit cd16c57bd0
3 changed files with 20 additions and 0 deletions

View File

@ -250,6 +250,10 @@ static int sandbox_clk_ccf_probe(struct udevice *dev)
clk_dm(SANDBOX_CLK_ECSPI_ROOT, clk_dm(SANDBOX_CLK_ECSPI_ROOT,
sandbox_clk_divider("ecspi_root", "pll3_60m", &reg, 19, 6)); sandbox_clk_divider("ecspi_root", "pll3_60m", &reg, 19, 6));
reg = 0;
clk_dm(SANDBOX_CLK_ECSPI0,
sandbox_clk_gate("ecspi0", "ecspi_root", &reg, 0, 0));
clk_dm(SANDBOX_CLK_ECSPI1, clk_dm(SANDBOX_CLK_ECSPI1,
sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0)); sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));

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@ -50,6 +50,14 @@ static inline struct clk *sandbox_clk_divider(const char *name,
reg, shift, width, 0); reg, shift, width, 0);
} }
static inline struct clk *sandbox_clk_gate(const char *name, const char *parent,
void __iomem *reg, u8 bit_idx,
u8 clk_gate_flags)
{
return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT,
reg, bit_idx, clk_gate_flags, NULL);
}
struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name, struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
const char *parent_name, const char *parent_name,
unsigned long flags, unsigned long flags,

View File

@ -39,6 +39,14 @@ static int dm_test_clk_ccf(struct unit_test_state *uts)
rate = clk_get_parent_rate(clk); rate = clk_get_parent_rate(clk);
ut_asserteq(rate, 20000000); ut_asserteq(rate, 20000000);
/* test the gate of CCF */
ret = clk_get_by_id(SANDBOX_CLK_ECSPI0, &clk);
ut_assertok(ret);
ut_asserteq_str("ecspi0", clk->dev->name);
rate = clk_get_parent_rate(clk);
ut_asserteq(rate, 20000000);
/* Test the mux of CCF */ /* Test the mux of CCF */
ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk); ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
ut_assertok(ret); ut_assertok(ret);