pwh1: support PW-H1 for 2021.07+fslc
This commit is contained in:
parent
d8c99c87a4
commit
c6fab5a020
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@ -11,11 +11,11 @@
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#include "imx7ulp.dtsi"
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/ {
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model = "NXP i.MX7ULP EVK";
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compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
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model = "NXP i.MX7ULP Sharp Brain PW-H1";
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compatible = "fsl,imx7ulp-pwh1", "fsl,imx7ulp", "Generic DT based system";
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chosen {
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bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
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bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200";
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stdout-path = &lpuart4;
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};
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@ -47,6 +47,13 @@
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#reset-cells = <0>;
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};
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emmc_sdhc1_pwrseq: emmc-sdhc1-reset {
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compatible = "mmc-pwrseq-emmc";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1_rst>;
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reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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@ -66,7 +73,7 @@
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compatible = "regulator-fixed";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1>;
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pinctrl-0 = <&pinctrl_usbotg1_vbus>;
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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@ -77,6 +84,8 @@
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reg_vsd_3v3: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc0_vsd>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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@ -84,33 +93,23 @@
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enable-active-high;
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};
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reg_vsd_3v3b: regulator@2 {
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reg_vmmc_3v3: regulator@2 {
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compatible = "regulator-fixed";
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reg = <2>;
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regulator-name = "VSD_3V3B";
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regulator-name = "VMMC_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_vsd_1v8: regulator@3 {
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reg_vqmmc_1v8: regulator@3 {
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compatible = "regulator-fixed";
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reg = <3>;
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regulator-name = "VSD_1V8";
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regulator-name = "VQMMC_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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enable-active-high;
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};
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};
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extcon_usb1: extcon_usb1 {
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compatible = "linux,extcon-usb-gpio";
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id-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_extcon_usb1>;
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};
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pf1550-rpmsg {
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compatible = "fsl,pf1550-rpmsg";
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sw1_reg: SW1 {
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@ -172,152 +171,144 @@
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog_1>;
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imx7ulp-evk {
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imx7ulp-pwh1 {
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pinctrl_hog_1: hoggrp-1 {
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fsl,pins = <
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ULP1_PAD_PTC10__PTC10 0x30100 /* USDHC0 CD */
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ULP1_PAD_PTC1__PTC1 0x20100
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ULP1_PAD_PTD0__PTD0 0x30100 /* USDHC0 RST */
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ULP1_PAD_PTE13__PTE13 0x30103 /* USDHC1 CD */
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ULP1_PAD_PTE12__PTE12 0x30103 /* USDHC1 WP */
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ULP1_PAD_PTE14__SDHC1_VS 0x843 /* USDHC1 VSEL */
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IMX7ULP_PAD_PTC1__PTC1 0x20000
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>;
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};
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pinctrl_backlight: backlight_grp {
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fsl,pins = <
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ULP1_PAD_PTF2__PTF2 0x20100
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IMX7ULP_PAD_PTF2__PTF2 0x20000
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>;
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};
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pinctrl_lpi2c5: lpi2c5grp {
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fsl,pins = <
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ULP1_PAD_PTC4__LPI2C5_SCL 0x527
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ULP1_PAD_PTC5__LPI2C5_SDA 0x527
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IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x27
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IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x27
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>;
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};
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pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp {
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fsl,pins = <
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ULP1_PAD_PTC19__PTC19 0x20103
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IMX7ULP_PAD_PTC19__PTC19 0x20003
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>;
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};
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pinctrl_lpuart4: lpuart4grp {
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fsl,pins = <
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ULP1_PAD_PTC3__LPUART4_RX 0x400
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ULP1_PAD_PTC2__LPUART4_TX 0x400
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IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
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IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
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>;
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};
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pinctrl_lpuart6: lpuart6grp {
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fsl,pins = <
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ULP1_PAD_PTE10__LPUART6_TX 0x400
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ULP1_PAD_PTE11__LPUART6_RX 0x400
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ULP1_PAD_PTE9__LPUART6_RTS_B 0x400
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ULP1_PAD_PTE8__LPUART6_CTS_B 0x400
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ULP1_PAD_PTE7__PTE7 0x00 /* BT_REG_ON */
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IMX7ULP_PAD_PTE10__LPUART6_TX 0x3
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IMX7ULP_PAD_PTE11__LPUART6_RX 0x3
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IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3
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IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3
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IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */
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>;
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};
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pinctrl_lpuart7: lpuart7grp {
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fsl,pins = <
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ULP1_PAD_PTF14__LPUART7_TX 0x400
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ULP1_PAD_PTF15__LPUART7_RX 0x400
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ULP1_PAD_PTF13__LPUART7_RTS_B 0x400
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ULP1_PAD_PTF12__LPUART7_CTS_B 0x400
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IMX7ULP_PAD_PTF14__LPUART7_TX 0x3
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IMX7ULP_PAD_PTF15__LPUART7_RX 0x3
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IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3
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IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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ULP1_PAD_PTD1__SDHC0_CMD 0x843
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ULP1_PAD_PTD2__SDHC0_CLK 0x10843
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ULP1_PAD_PTD7__SDHC0_D3 0x843
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ULP1_PAD_PTD8__SDHC0_D2 0x843
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ULP1_PAD_PTD9__SDHC0_D1 0x843
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ULP1_PAD_PTD10__SDHC0_D0 0x843
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IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
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IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10043
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IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
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IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
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IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
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IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
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>;
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};
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pinctrl_usdhc0_vsd: usdhc0grp_vsd {
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fsl,pins = <
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IMX7ULP_PAD_PTD0__PTD0 0x20000 /* SD_POWER_FET_ON */
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>;
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};
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pinctrl_usdhc0_8bit: usdhc0grp_8bit {
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fsl,pins = <
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ULP1_PAD_PTD1__SDHC0_CMD 0x843
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ULP1_PAD_PTD2__SDHC0_CLK 0x843
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ULP1_PAD_PTD3__SDHC0_D7 0x843
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ULP1_PAD_PTD4__SDHC0_D6 0x843
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ULP1_PAD_PTD5__SDHC0_D5 0x843
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ULP1_PAD_PTD6__SDHC0_D4 0x843
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ULP1_PAD_PTD7__SDHC0_D3 0x843
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ULP1_PAD_PTD8__SDHC0_D2 0x843
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ULP1_PAD_PTD9__SDHC0_D1 0x843
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ULP1_PAD_PTD10__SDHC0_D0 0x843
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IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
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IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
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IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
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IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
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IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
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IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
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IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
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IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
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IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
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IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
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IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
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>;
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};
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pinctrl_lpi2c7: lpi2c7grp {
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fsl,pins = <
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ULP1_PAD_PTF12__LPI2C7_SCL 0x527
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ULP1_PAD_PTF13__LPI2C7_SDA 0x527
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IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x27
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IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x27
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>;
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};
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pinctrl_lpspi3: lpspi3grp {
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fsl,pins = <
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ULP1_PAD_PTF16__LPSPI3_SIN 0x300
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ULP1_PAD_PTF17__LPSPI3_SOUT 0x300
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ULP1_PAD_PTF18__LPSPI3_SCK 0x300
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ULP1_PAD_PTF19__LPSPI3_PCS0 0x300
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IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0
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IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0
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IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0
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IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0
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>;
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};
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pinctrl_usb_otg1: usbotg1grp {
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pinctrl_usbotg1_vbus: otg1vbusgrp {
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fsl,pins = <
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ULP1_PAD_PTC0__PTC0 0x30100
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IMX7ULP_PAD_PTC0__PTC0 0x20000
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>;
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};
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pinctrl_extcon_usb1: extcon1grp {
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pinctrl_usbotg1_id: otg1idgrp {
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fsl,pins = <
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ULP1_PAD_PTC8__PTC8 0x30103
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IMX7ULP_PAD_PTC13__USB0_ID 0x10003
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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pinctrl_usdhc1_8bit: usdhc1grp {
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fsl,pins = <
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ULP1_PAD_PTE3__SDHC1_CMD 0x843
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ULP1_PAD_PTE2__SDHC1_CLK 0x843
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ULP1_PAD_PTE1__SDHC1_D0 0x843
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ULP1_PAD_PTE0__SDHC1_D1 0x843
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ULP1_PAD_PTE5__SDHC1_D2 0x843
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ULP1_PAD_PTE4__SDHC1_D3 0x843
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>;
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};
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pinctrl_usdhc1_8bit: usdhc1grp_8bit {
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fsl,pins = <
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ULP1_PAD_PTE3__SDHC1_CMD 0x803
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ULP1_PAD_PTE2__SDHC1_CLK 0x802
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ULP1_PAD_PTE9__SDHC1_D7 0x803
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ULP1_PAD_PTE8__SDHC1_D6 0x803
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ULP1_PAD_PTE7__SDHC1_D5 0x803
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ULP1_PAD_PTE6__SDHC1_D4 0x803
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ULP1_PAD_PTE4__SDHC1_D3 0x803
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ULP1_PAD_PTE5__SDHC1_D2 0x803
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ULP1_PAD_PTE0__SDHC1_D1 0x803
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ULP1_PAD_PTE1__SDHC1_D0 0x803
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IMX7ULP_PAD_PTE3__SDHC1_CMD 0x03
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IMX7ULP_PAD_PTE2__SDHC1_CLK 0x02
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IMX7ULP_PAD_PTE1__SDHC1_D0 0x03
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IMX7ULP_PAD_PTE0__SDHC1_D1 0x03
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IMX7ULP_PAD_PTE5__SDHC1_D2 0x03
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IMX7ULP_PAD_PTE4__SDHC1_D3 0x03
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IMX7ULP_PAD_PTE6__SDHC1_D4 0x03
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IMX7ULP_PAD_PTE7__SDHC1_D5 0x03
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IMX7ULP_PAD_PTE8__SDHC1_D6 0x03
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IMX7ULP_PAD_PTE9__SDHC1_D7 0x03
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IMX7ULP_PAD_PTE10__SDHC1_DQS 0x03
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>;
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};
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pinctrl_usdhc1_rst: usdhc1grp_rst {
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fsl,pins = <
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ULP1_PAD_PTE11__PTE11 0x30100 /* USDHC1 RST */
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IMX7ULP_PAD_PTE11__PTE11 0x10003
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>;
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};
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pinctrl_wifi: wifigrp {
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pinctrl_dsi_hdmi: dsi_hdmi_grp {
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fsl,pins = <
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ULP1_PAD_PTE6__PTE6 0x43 /* WL_REG_ON */
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IMX7ULP_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */
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>;
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};
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};
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@ -328,7 +319,7 @@
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disp-dev = "mipi_dsi_northwest";
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display = <&display0>;
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display0: display {
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display0: display@0 {
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bits-per-pixel = <16>;
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bus-width = <24>;
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@ -367,21 +358,6 @@
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c5>;
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status = "okay";
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fxas2100x@20 {
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compatible = "fsl,fxas2100x";
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reg = <0x20>;
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};
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fxos8700@1e {
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compatible = "fsl,fxos8700";
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reg = <0x1e>;
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};
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mpl3115@60 {
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compatible = "fsl,mpl3115";
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reg = <0x60>;
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};
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};
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&lpspi3 {
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@ -430,22 +406,26 @@
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&usbotg1 {
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vbus-supply = <®_usb_otg1_vbus>;
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extcon = <0>, <&extcon_usb1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_id>;
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srp-disable;
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hnp-disable;
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adp-disable;
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status = "okay";
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};
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&usbphy1 {
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fsl,tx-d-cal = <88>;
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};
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&usdhc0 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
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pinctrl-0 = <&pinctrl_usdhc0>;
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pinctrl-1 = <&pinctrl_usdhc0>;
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pinctrl-2 = <&pinctrl_usdhc0>;
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pinctrl-3 = <&pinctrl_usdhc0>;
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cd-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
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broken-cd;
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vmmc-supply = <®_vsd_3v3>;
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vqmmc-supply = <&vldo2_reg>;
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status = "okay";
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};
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@ -455,8 +435,10 @@
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pinctrl-1 = <&pinctrl_usdhc1_8bit>;
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pinctrl-2 = <&pinctrl_usdhc1_8bit>;
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pinctrl-3 = <&pinctrl_usdhc1_8bit>;
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vmmc-supply = <®_vsd_1v8>;
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vqmmc-supply = <&vldo1_reg>;
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data-bus = <8>;
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non-removable;
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vmmc-supply = <®_vmmc_3v3>;
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vqmmc-supply = <®_vqmmc_1v8>;
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mmc-pwrseq = <&emmc_sdhc1_pwrseq>;
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status = "okay";
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};
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@ -27,7 +27,8 @@ config TARGET_MX7ULP_EVK
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select SYS_ARCH_TIMER
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config TARGET_PWH1
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bool "Support PW-H1 board"
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bool "Support PW-H1 board"
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select MX7ULP
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select SYS_ARCH_TIMER
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endchoice
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@ -24,7 +24,7 @@ BOOT_FROM sd
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#ifdef CONFIG_USE_IMXIMG_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
|
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PLUGIN board/sharp/pwh1/plugin.bin 0x2F020000
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
|
|
|
@ -4,6 +4,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/mx7ulp-pins.h>
|
||||
|
|
|
@ -1,33 +1,38 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_THUMB_BUILD=y
|
||||
CONFIG_ARCH_MX7ULP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x60000000
|
||||
CONFIG_TARGET_PWH1=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SYS_MEMTEST_START=0x60000000
|
||||
CONFIG_SYS_MEMTEST_END=0x66000000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0xC0000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-pwh1"
|
||||
CONFIG_TARGET_PWH1=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/sharp/pwh1/imximage.cfg"
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-pwh1"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
# CONFIG_NET is not set
|
||||
CONFIG_DM=y
|
||||
# CONFIG_DM_GPIO is not set
|
||||
# CONFIG_IMX_RGPIO2P is not set
|
||||
CONFIG_BOUNCE_BUFFER=y
|
||||
CONFIG_IMX_RGPIO2P=y
|
||||
# CONFIG_MXC_GPIO is not set
|
||||
CONFIG_DM_MMC=y
|
||||
# CONFIG_MMC_VERBOSE is not set
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX7ULP=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
|
|
@ -5,43 +5,18 @@
|
|||
* Configuration settings for the Freescale i.MX7ULP EVK board.
|
||||
*/
|
||||
|
||||
#ifndef __MX7ULP_EVK_CONFIG_H
|
||||
#define __MX7ULP_EVK_CONFIG_H
|
||||
#ifndef __MX7ULP_PWH1_CONFIG_H
|
||||
#define __MX7ULP_PWH1_CONFIG_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
/*Uncomment it to use secure boot*/
|
||||
/*#define CONFIG_SECURE_BOOT*/
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
#ifndef CONFIG_CSF_SIZE
|
||||
#define CONFIG_CSF_SIZE 0x4000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOARD_POSTCLK_INIT
|
||||
#define CONFIG_SYS_BOOTM_LEN 0x1000000
|
||||
|
||||
#define SRC_BASE_ADDR CMC1_RBASE
|
||||
#define IRAM_BASE_ADDR OCRAM_0_BASE
|
||||
#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
|
||||
|
||||
#define CONFIG_BOUNCE_BUFFER
|
||||
#define CONFIG_FSL_USDHC
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1
|
||||
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
#define CONFIG_ENV_OFFSET (12 * SZ_64K)
|
||||
#define CONFIG_ENV_SIZE SZ_8K
|
||||
|
||||
/* Using ULP WDOG for reset */
|
||||
#define WDOG_BASE_ADDR WDG1_RBASE
|
||||
|
||||
|
@ -55,15 +30,9 @@
|
|||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* UART */
|
||||
#define LPUART_BASE LPUART4_RBASE
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
|
@ -75,14 +44,11 @@
|
|||
/* Physical Memory Map */
|
||||
|
||||
#define PHYS_SDRAM 0x60000000
|
||||
#define PHYS_SDRAM_SIZE 0x8000000
|
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
|
||||
#define PHYS_SDRAM_SIZE SZ_128M
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
|
||||
#define CONFIG_LOADADDR 0x60800000
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_END 0x66000000
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
|
@ -169,8 +135,4 @@
|
|||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_CMD_CACHE
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
Loading…
Reference in New Issue