mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-28 23:50:26 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-arm
This commit is contained in:
commit
c23154aab5
4
.gitignore
vendored
4
.gitignore
vendored
@ -44,11 +44,7 @@
|
||||
#
|
||||
# Generated files
|
||||
#
|
||||
|
||||
/LOG
|
||||
/errlog
|
||||
/reloc_off
|
||||
|
||||
/spl/
|
||||
/tpl/
|
||||
|
||||
|
27
.mailmap
Normal file
27
.mailmap
Normal file
@ -0,0 +1,27 @@
|
||||
#
|
||||
# This list is used by git-shortlog to fix a few botched name translations
|
||||
# in the git archive, either because the author's full name was messed up
|
||||
# and/or not always written the same way, making contributions from the
|
||||
# same person appearing not to be so or badly displayed.
|
||||
#
|
||||
# This file can be modified by hand or updated by the following command:
|
||||
# scripts/mailmapper > tmp; mv tmp .mailmap
|
||||
#
|
||||
|
||||
Allen Martin <amartin@nvidia.com>
|
||||
Andreas Bießmann <andreas.devel@googlemail.com>
|
||||
Aneesh V <aneesh@ti.com>
|
||||
Dirk Behme <dirk.behme@googlemail.com>
|
||||
Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Jagannadha Sutradharudu Teki <402jagan@gmail.com>
|
||||
Markus Klotzbuecher <mk@denx.de>
|
||||
Prabhakar Kushwaha <prabhakar@freescale.com>
|
||||
Rajeshwari Shinde <rajeshwari.s@samsung.com>
|
||||
Sandeep Paulraj <s-paulraj@ti.com>
|
||||
Shaohui Xie <Shaohui.Xie@freescale.com>
|
||||
Stefan Roese <stroese>
|
||||
Stefano Babic <sbabic@denx.de>
|
||||
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
|
||||
Wolfgang Denk <wdenk>
|
||||
York Sun <yorksun@freescale.com>
|
||||
Łukasz Majewski <l.majewski@samsung.com>
|
15
Makefile
15
Makefile
@ -915,6 +915,12 @@ OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
|
||||
u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
|
||||
$(call if_changed,pad_cat)
|
||||
|
||||
MKIMAGEFLAGS_u-boot-nand.gph = -A $(ARCH) -T gpimage -C none \
|
||||
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot
|
||||
u-boot-nand.gph: u-boot.bin FORCE
|
||||
$(call if_changed,mkimage)
|
||||
@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
|
||||
|
||||
ifneq ($(CONFIG_SUNXI),)
|
||||
OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
|
||||
--pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
|
||||
@ -1137,7 +1143,7 @@ spl/sunxi-spl.bin: spl/u-boot-spl
|
||||
tpl/u-boot-tpl.bin: tools prepare
|
||||
$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all CONFIG_TPL_BUILD=y
|
||||
|
||||
TAG_SUBDIRS := $(u-boot-dirs) include
|
||||
TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include)
|
||||
|
||||
FIND := find
|
||||
FINDFLAGS := -L
|
||||
@ -1147,7 +1153,7 @@ tags ctags:
|
||||
-name '*.[chS]' -print`
|
||||
|
||||
etags:
|
||||
etags -a -o $(obj)etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
|
||||
etags -a -o etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
|
||||
-name '*.[chS]' -print`
|
||||
cscope:
|
||||
$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) -name '*.[chS]' -print > \
|
||||
@ -1222,7 +1228,7 @@ CLOBBER_FILES += u-boot* MLO* SPL System.map
|
||||
MRPROPER_DIRS += include/config include/generated \
|
||||
.tmp_objdiff
|
||||
MRPROPER_FILES += .config .config.old \
|
||||
tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
|
||||
ctags etags cscope* GPATH GTAGS GRTAGS GSYMS \
|
||||
include/config.h include/config.mk
|
||||
|
||||
# clean - Delete most, but leave enough to build external modules
|
||||
@ -1311,7 +1317,8 @@ help:
|
||||
@echo ' dir/file.[oisS] - Build specified target only'
|
||||
@echo ' dir/file.lst - Build specified mixed source/assembly target only'
|
||||
@echo ' (requires a recent binutils and recent build (System.map))'
|
||||
@echo ' tags/TAGS - Generate tags file for editors'
|
||||
@echo ' tags/ctags - Generate ctags file for editors'
|
||||
@echo ' etags - Generate etags file for editors'
|
||||
@echo ' cscope - Generate cscope index'
|
||||
@echo ' ubootrelease - Output the release version string'
|
||||
@echo ' ubootversion - Output the version stored in Makefile'
|
||||
|
16
README
16
README
@ -3751,6 +3751,22 @@ Configuration Settings:
|
||||
- CONFIG_SYS_MALLOC_LEN:
|
||||
Size of DRAM reserved for malloc() use.
|
||||
|
||||
- CONFIG_SYS_MALLOC_F_LEN
|
||||
Size of the malloc() pool for use before relocation. If
|
||||
this is defined, then a very simple malloc() implementation
|
||||
will become available before relocation. The address is just
|
||||
below the global data, and the stack is moved down to make
|
||||
space.
|
||||
|
||||
This feature allocates regions with increasing addresses
|
||||
within the region. calloc() is supported, but realloc()
|
||||
is not available. free() is supported but does nothing.
|
||||
The memory will be freed (or in fact just forgotton) when
|
||||
U-Boot relocates itself.
|
||||
|
||||
Pre-relocation malloc() is only supported on sandbox
|
||||
at present but is fairly easy to enable for other archs.
|
||||
|
||||
- CONFIG_SYS_BOOTM_LEN:
|
||||
Normally compressed uImages are limited to an
|
||||
uncompressed size of 8 MBytes. If this is not enough,
|
||||
|
@ -113,7 +113,7 @@ endif
|
||||
ifdef CONFIG_ARM64
|
||||
OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
|
||||
else
|
||||
OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
|
||||
OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
|
||||
endif
|
||||
|
||||
ifdef CONFIG_OF_EMBED
|
||||
|
@ -21,6 +21,11 @@ endif
|
||||
ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
|
||||
obj-y += nonsec_virt.o
|
||||
obj-y += virt-v7.o
|
||||
obj-y += virt-dt.o
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_ARMV7_PSCI),)
|
||||
obj-y += psci.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_KONA) += kona-common/
|
||||
|
@ -8,9 +8,12 @@
|
||||
obj-y += init.o
|
||||
obj-y += psc.o
|
||||
obj-y += clock.o
|
||||
obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
|
||||
obj-$(CONFIG_SOC_K2E) += clock-k2e.o
|
||||
obj-y += cmd_clock.o
|
||||
obj-y += cmd_mon.o
|
||||
obj-y += keystone_nav.o
|
||||
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
|
||||
obj-y += msmc.o
|
||||
obj-$(CONFIG_SPL_BUILD) += spl.o
|
||||
obj-y += ddr3.o
|
||||
obj-y += keystone.o
|
||||
|
101
arch/arm/cpu/armv7/keystone/clock-k2e.c
Normal file
101
arch/arm/cpu/armv7/keystone/clock-k2e.c
Normal file
@ -0,0 +1,101 @@
|
||||
/*
|
||||
* Keystone2: get clk rate for K2E
|
||||
*
|
||||
* (C) Copyright 2012-2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/clock_defs.h>
|
||||
|
||||
const struct keystone_pll_regs keystone_pll_regs[] = {
|
||||
[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
|
||||
[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
|
||||
[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
|
||||
};
|
||||
|
||||
/**
|
||||
* pll_freq_get - get pll frequency
|
||||
* Fout = Fref * NF(mult) / NR(prediv) / OD
|
||||
* @pll: pll identifier
|
||||
*/
|
||||
static unsigned long pll_freq_get(int pll)
|
||||
{
|
||||
unsigned long mult = 1, prediv = 1, output_div = 2;
|
||||
unsigned long ret;
|
||||
u32 tmp, reg;
|
||||
|
||||
if (pll == CORE_PLL) {
|
||||
ret = external_clk[sys_clk];
|
||||
if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
|
||||
/* PLL mode */
|
||||
tmp = __raw_readl(KS2_MAINPLLCTL0);
|
||||
prediv = (tmp & PLL_DIV_MASK) + 1;
|
||||
mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
|
||||
(pllctl_reg_read(pll, mult) &
|
||||
PLLM_MULT_LO_MASK)) + 1;
|
||||
output_div = ((pllctl_reg_read(pll, secctl) >>
|
||||
PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
|
||||
|
||||
ret = ret / prediv / output_div * mult;
|
||||
}
|
||||
} else {
|
||||
switch (pll) {
|
||||
case PASS_PLL:
|
||||
ret = external_clk[pa_clk];
|
||||
reg = KS2_PASSPLLCTL0;
|
||||
break;
|
||||
case DDR3_PLL:
|
||||
ret = external_clk[ddr3_clk];
|
||||
reg = KS2_DDR3APLLCTL0;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
tmp = __raw_readl(reg);
|
||||
|
||||
if (!(tmp & PLLCTL_BYPASS)) {
|
||||
/* Bypass disabled */
|
||||
prediv = (tmp & PLL_DIV_MASK) + 1;
|
||||
mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
|
||||
output_div = ((tmp >> PLL_CLKOD_SHIFT) &
|
||||
PLL_CLKOD_MASK) + 1;
|
||||
ret = ((ret / prediv) * mult) / output_div;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
unsigned long clk_get_rate(unsigned int clk)
|
||||
{
|
||||
switch (clk) {
|
||||
case core_pll_clk: return pll_freq_get(CORE_PLL);
|
||||
case pass_pll_clk: return pll_freq_get(PASS_PLL);
|
||||
case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
|
||||
case sys_clk0_1_clk:
|
||||
case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
|
||||
case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
|
||||
case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
|
||||
case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
|
||||
case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
|
||||
case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
|
||||
case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
|
||||
case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
|
||||
case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
|
||||
case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
|
||||
case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
|
||||
case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
|
||||
case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
|
||||
case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
|
||||
case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
113
arch/arm/cpu/armv7/keystone/clock-k2hk.c
Normal file
113
arch/arm/cpu/armv7/keystone/clock-k2hk.c
Normal file
@ -0,0 +1,113 @@
|
||||
/*
|
||||
* Keystone2: get clk rate for K2HK
|
||||
*
|
||||
* (C) Copyright 2012-2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/clock_defs.h>
|
||||
|
||||
const struct keystone_pll_regs keystone_pll_regs[] = {
|
||||
[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
|
||||
[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
|
||||
[TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
|
||||
[DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
|
||||
[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
|
||||
};
|
||||
|
||||
/**
|
||||
* pll_freq_get - get pll frequency
|
||||
* Fout = Fref * NF(mult) / NR(prediv) / OD
|
||||
* @pll: pll identifier
|
||||
*/
|
||||
static unsigned long pll_freq_get(int pll)
|
||||
{
|
||||
unsigned long mult = 1, prediv = 1, output_div = 2;
|
||||
unsigned long ret;
|
||||
u32 tmp, reg;
|
||||
|
||||
if (pll == CORE_PLL) {
|
||||
ret = external_clk[sys_clk];
|
||||
if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
|
||||
/* PLL mode */
|
||||
tmp = __raw_readl(KS2_MAINPLLCTL0);
|
||||
prediv = (tmp & PLL_DIV_MASK) + 1;
|
||||
mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
|
||||
(pllctl_reg_read(pll, mult) &
|
||||
PLLM_MULT_LO_MASK)) + 1;
|
||||
output_div = ((pllctl_reg_read(pll, secctl) >>
|
||||
PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
|
||||
|
||||
ret = ret / prediv / output_div * mult;
|
||||
}
|
||||
} else {
|
||||
switch (pll) {
|
||||
case PASS_PLL:
|
||||
ret = external_clk[pa_clk];
|
||||
reg = KS2_PASSPLLCTL0;
|
||||
break;
|
||||
case TETRIS_PLL:
|
||||
ret = external_clk[tetris_clk];
|
||||
reg = KS2_ARMPLLCTL0;
|
||||
break;
|
||||
case DDR3A_PLL:
|
||||
ret = external_clk[ddr3a_clk];
|
||||
reg = KS2_DDR3APLLCTL0;
|
||||
break;
|
||||
case DDR3B_PLL:
|
||||
ret = external_clk[ddr3b_clk];
|
||||
reg = KS2_DDR3BPLLCTL0;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
tmp = __raw_readl(reg);
|
||||
|
||||
if (!(tmp & PLLCTL_BYPASS)) {
|
||||
/* Bypass disabled */
|
||||
prediv = (tmp & PLL_DIV_MASK) + 1;
|
||||
mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
|
||||
output_div = ((tmp >> PLL_CLKOD_SHIFT) &
|
||||
PLL_CLKOD_MASK) + 1;
|
||||
ret = ((ret / prediv) * mult) / output_div;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
unsigned long clk_get_rate(unsigned int clk)
|
||||
{
|
||||
switch (clk) {
|
||||
case core_pll_clk: return pll_freq_get(CORE_PLL);
|
||||
case pass_pll_clk: return pll_freq_get(PASS_PLL);
|
||||
case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
|
||||
case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
|
||||
case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
|
||||
case sys_clk0_1_clk:
|
||||
case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
|
||||
case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
|
||||
case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
|
||||
case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
|
||||
case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
|
||||
case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
|
||||
case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
|
||||
case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
|
||||
case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
|
||||
case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
|
||||
case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
|
||||
case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
|
||||
case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
|
||||
case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
|
||||
case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
@ -8,9 +8,6 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm-generic/errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/clock_defs.h>
|
||||
|
||||
@ -24,106 +21,6 @@ static void wait_for_completion(const struct pll_init_data *data)
|
||||
}
|
||||
}
|
||||
|
||||
struct pll_regs {
|
||||
u32 reg0, reg1;
|
||||
};
|
||||
|
||||
static const struct pll_regs pll_regs[] = {
|
||||
[CORE_PLL] = { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
|
||||
[PASS_PLL] = { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
|
||||
[TETRIS_PLL] = { K2HK_ARMPLLCTL0, K2HK_ARMPLLCTL1},
|
||||
[DDR3A_PLL] = { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
|
||||
[DDR3B_PLL] = { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
|
||||
};
|
||||
|
||||
/* Fout = Fref * NF(mult) / NR(prediv) / OD */
|
||||
static unsigned long pll_freq_get(int pll)
|
||||
{
|
||||
unsigned long mult = 1, prediv = 1, output_div = 2;
|
||||
unsigned long ret;
|
||||
u32 tmp, reg;
|
||||
|
||||
if (pll == CORE_PLL) {
|
||||
ret = external_clk[sys_clk];
|
||||
if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
|
||||
/* PLL mode */
|
||||
tmp = __raw_readl(K2HK_MAINPLLCTL0);
|
||||
prediv = (tmp & PLL_DIV_MASK) + 1;
|
||||
mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
|
||||
(pllctl_reg_read(pll, mult) &
|
||||
PLLM_MULT_LO_MASK)) + 1;
|
||||
output_div = ((pllctl_reg_read(pll, secctl) >>
|
||||
PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
|
||||
|
||||
ret = ret / prediv / output_div * mult;
|
||||
}
|
||||
} else {
|
||||
switch (pll) {
|
||||
case PASS_PLL:
|
||||
ret = external_clk[pa_clk];
|
||||
reg = K2HK_PASSPLLCTL0;
|
||||
break;
|
||||
case TETRIS_PLL:
|
||||
ret = external_clk[tetris_clk];
|
||||
reg = K2HK_ARMPLLCTL0;
|
||||
break;
|
||||
case DDR3A_PLL:
|
||||
ret = external_clk[ddr3a_clk];
|
||||
reg = K2HK_DDR3APLLCTL0;
|
||||
break;
|
||||
case DDR3B_PLL:
|
||||
ret = external_clk[ddr3b_clk];
|
||||
reg = K2HK_DDR3BPLLCTL0;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
tmp = __raw_readl(reg);
|
||||
|
||||
if (!(tmp & PLLCTL_BYPASS)) {
|
||||
/* Bypass disabled */
|
||||
prediv = (tmp & PLL_DIV_MASK) + 1;
|
||||
mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
|
||||
output_div = ((tmp >> PLL_CLKOD_SHIFT) &
|
||||
PLL_CLKOD_MASK) + 1;
|
||||
ret = ((ret / prediv) * mult) / output_div;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
unsigned long clk_get_rate(unsigned int clk)
|
||||
{
|
||||
switch (clk) {
|
||||
case core_pll_clk: return pll_freq_get(CORE_PLL);
|
||||
case pass_pll_clk: return pll_freq_get(PASS_PLL);
|
||||
case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
|
||||
case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
|
||||
case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
|
||||
case sys_clk0_1_clk:
|
||||
case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
|
||||
case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
|
||||
case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
|
||||
case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
|
||||
case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
|
||||
case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
|
||||
case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
|
||||
case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
|
||||
case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
|
||||
case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
|
||||
case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
|
||||
case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
|
||||
case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
|
||||
case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
|
||||
case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void init_pll(const struct pll_init_data *data)
|
||||
{
|
||||
u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
|
||||
@ -139,7 +36,7 @@ void init_pll(const struct pll_init_data *data)
|
||||
tmp = pllctl_reg_read(data->pll, secctl);
|
||||
|
||||
if (tmp & (PLLCTL_BYPASS)) {
|
||||
setbits_le32(pll_regs[data->pll].reg1,
|
||||
setbits_le32(keystone_pll_regs[data->pll].reg1,
|
||||
BIT(MAIN_ENSAT_OFFSET));
|
||||
|
||||
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
|
||||
@ -159,21 +56,24 @@ void init_pll(const struct pll_init_data *data)
|
||||
|
||||
pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
|
||||
|
||||
clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
|
||||
(pllm << 6));
|
||||
clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
|
||||
PLLM_MULT_HI_SMASK, (pllm << 6));
|
||||
|
||||
/* Set the BWADJ (12 bit field) */
|
||||
tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
|
||||
clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
|
||||
clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
|
||||
PLL_BWADJ_LO_SMASK,
|
||||
(tmp_ctl << PLL_BWADJ_LO_SHIFT));
|
||||
clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
|
||||
clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
|
||||
PLL_BWADJ_HI_MASK,
|
||||
(tmp_ctl >> 8));
|
||||
|
||||
/*
|
||||
* Set the pll divider (6 bit field) *
|
||||
* PLLD[5:0] is located in MAINPLLCTL0
|
||||
*/
|
||||
clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);
|
||||
clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
|
||||
PLL_DIV_MASK, plld);
|
||||
|
||||
/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
|
||||
pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
|
||||
@ -206,17 +106,18 @@ void init_pll(const struct pll_init_data *data)
|
||||
|
||||
tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
|
||||
|
||||
#ifndef CONFIG_SOC_K2E
|
||||
} else if (data->pll == TETRIS_PLL) {
|
||||
bwadj = pllm >> 1;
|
||||
/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
|
||||
setbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
|
||||
setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
|
||||
/*
|
||||
* Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
|
||||
* only applicable for Kepler
|
||||
*/
|
||||
clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
|
||||
clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
|
||||
/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
|
||||
setbits_le32(pll_regs[data->pll].reg1 ,
|
||||
setbits_le32(keystone_pll_regs[data->pll].reg1 ,
|
||||
PLL_PLLRST | PLLCTL_ENSAT);
|
||||
|
||||
/*
|
||||
@ -229,13 +130,13 @@ void init_pll(const struct pll_init_data *data)
|
||||
(pllm << 6) |
|
||||
(plld & PLL_DIV_MASK) |
|
||||
(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
|
||||
__raw_writel(tmp, pll_regs[data->pll].reg0);
|
||||
__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
|
||||
|
||||
/* Set BWADJ[11:8] bits */
|
||||
tmp = __raw_readl(pll_regs[data->pll].reg1);
|
||||
tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
|
||||
tmp &= ~(PLL_BWADJ_HI_MASK);
|
||||
tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
|
||||
__raw_writel(tmp, pll_regs[data->pll].reg1);
|
||||
__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
|
||||
/*
|
||||
* 5 Wait for at least 5 us based on the reference
|
||||
* clock (PLL reset time)
|
||||
@ -243,26 +144,27 @@ void init_pll(const struct pll_init_data *data)
|
||||
sdelay(21000); /* Wait for a minimum of 7 us*/
|
||||
|
||||
/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
|
||||
clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
|
||||
clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
|
||||
/*
|
||||
* 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
|
||||
* (PLL lock time)
|
||||
*/
|
||||
sdelay(105000);
|
||||
/* 8 disable bypass */
|
||||
clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
|
||||
clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
|
||||
/*
|
||||
* 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
|
||||
* only applicable for Kepler
|
||||
*/
|
||||
setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
|
||||
setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
|
||||
#endif
|
||||
} else {
|
||||
setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
|
||||
setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
|
||||
/*
|
||||
* process keeps state of Bypass bit while programming
|
||||
* all other DDR PLL settings
|
||||
*/
|
||||
tmp = __raw_readl(pll_regs[data->pll].reg0);
|
||||
tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
|
||||
tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
|
||||
|
||||
/*
|
||||
@ -274,10 +176,10 @@ void init_pll(const struct pll_init_data *data)
|
||||
(pllm << PLL_MULT_SHIFT) |
|
||||
(plld & PLL_DIV_MASK) |
|
||||
(pllod << PLL_CLKOD_SHIFT);
|
||||
__raw_writel(tmp, pll_regs[data->pll].reg0);
|
||||
__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
|
||||
|
||||
/* Set BWADJ[11:8] bits */
|
||||
tmp = __raw_readl(pll_regs[data->pll].reg1);
|
||||
tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
|
||||
tmp &= ~(PLL_BWADJ_HI_MASK);
|
||||
tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
|
||||
|
||||
@ -285,20 +187,20 @@ void init_pll(const struct pll_init_data *data)
|
||||
if (data->pll == PASS_PLL)
|
||||
tmp |= PLLCTL_PAPLL;
|
||||
|
||||
__raw_writel(tmp, pll_regs[data->pll].reg1);
|
||||
__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
|
||||
|
||||
/* Reset bit: bit 14 for both DDR3 & PASS PLL */
|
||||
tmp = PLL_PLLRST;
|
||||
/* Set RESET bit = 1 */
|
||||
setbits_le32(pll_regs[data->pll].reg1, tmp);
|
||||
setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
|
||||
/* Wait for a minimum of 7 us*/
|
||||
sdelay(21000);
|
||||
/* Clear RESET bit */
|
||||
clrbits_le32(pll_regs[data->pll].reg1, tmp);
|
||||
clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
|
||||
sdelay(105000);
|
||||
|
||||
/* clear BYPASS (Enable PLL Mode) */
|
||||
clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
|
||||
clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
|
||||
sdelay(21000); /* Wait for a minimum of 7 us*/
|
||||
}
|
||||
|
||||
|
@ -27,12 +27,19 @@ int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
|
||||
if (strncmp(argv[1], "pa", 2) == 0)
|
||||
cmd_pll_data.pll = PASS_PLL;
|
||||
#ifndef CONFIG_SOC_K2E
|
||||
else if (strncmp(argv[1], "arm", 3) == 0)
|
||||
cmd_pll_data.pll = TETRIS_PLL;
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_K2HK
|
||||
else if (strncmp(argv[1], "ddr3a", 5) == 0)
|
||||
cmd_pll_data.pll = DDR3A_PLL;
|
||||
else if (strncmp(argv[1], "ddr3b", 5) == 0)
|
||||
cmd_pll_data.pll = DDR3B_PLL;
|
||||
#else
|
||||
else if (strncmp(argv[1], "ddr3", 4) == 0)
|
||||
cmd_pll_data.pll = DDR3_PLL;
|
||||
#endif
|
||||
else
|
||||
goto pll_cmd_usage;
|
||||
|
||||
@ -51,11 +58,20 @@ pll_cmd_usage:
|
||||
return cmd_usage(cmdtp);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_K2HK
|
||||
U_BOOT_CMD(
|
||||
pllset, 5, 0, do_pll_cmd,
|
||||
"set pll multiplier and pre divider",
|
||||
"<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
|
||||
);
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_K2E
|
||||
U_BOOT_CMD(
|
||||
pllset, 5, 0, do_pll_cmd,
|
||||
"set pll multiplier and pre divider",
|
||||
"<pa|ddr3> <mult> <div> <OD>\n"
|
||||
);
|
||||
#endif
|
||||
|
||||
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
@ -79,7 +95,12 @@ U_BOOT_CMD(
|
||||
getclk, 2, 0, do_getclk_cmd,
|
||||
"get clock rate",
|
||||
"<clk index>\n"
|
||||
"See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
|
||||
#ifdef CONFIG_SOC_K2HK
|
||||
"See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_K2E
|
||||
"See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
|
||||
#endif
|
||||
);
|
||||
|
||||
int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
|
@ -7,10 +7,11 @@
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <asm/arch/ddr3.h>
|
||||
|
||||
void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
|
||||
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
@ -57,7 +58,7 @@ void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
|
||||
;
|
||||
}
|
||||
|
||||
void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
|
||||
void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
|
||||
{
|
||||
__raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
|
||||
__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
|
||||
@ -67,3 +68,21 @@ void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
|
||||
__raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
|
||||
__raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
|
||||
}
|
||||
|
||||
void ddr3_reset_ddrphy(void)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
/* Assert DDR3A PHY reset */
|
||||
tmp = readl(KS2_DDR3APLLCTL1);
|
||||
tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
|
||||
writel(tmp, KS2_DDR3APLLCTL1);
|
||||
|
||||
/* wait 10us to catch the reset */
|
||||
udelay(10);
|
||||
|
||||
/* Release DDR3A PHY reset */
|
||||
tmp = readl(KS2_DDR3APLLCTL1);
|
||||
tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
|
||||
__raw_writel(tmp, KS2_DDR3APLLCTL1);
|
||||
}
|
||||
|
@ -10,13 +10,14 @@
|
||||
#include <common.h>
|
||||
#include <ns16550.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/msmc.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
void chip_configuration_unlock(void)
|
||||
{
|
||||
__raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
|
||||
__raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
|
||||
__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
|
||||
__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
|
||||
}
|
||||
|
||||
int arch_cpu_init(void)
|
||||
@ -24,11 +25,12 @@ int arch_cpu_init(void)
|
||||
chip_configuration_unlock();
|
||||
icache_enable();
|
||||
|
||||
#ifdef CONFIG_SOC_K2HK
|
||||
share_all_segments(8);
|
||||
share_all_segments(9);
|
||||
share_all_segments(10); /* QM PDSP */
|
||||
share_all_segments(11); /* PCIE */
|
||||
msmc_share_all_segments(8); /* TETRIS */
|
||||
msmc_share_all_segments(9); /* NETCP */
|
||||
msmc_share_all_segments(10); /* QM PDSP */
|
||||
msmc_share_all_segments(11); /* PCIE 0 */
|
||||
#ifdef CONFIG_SOC_K2E
|
||||
msmc_share_all_segments(13); /* PCIE 1 */
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
87
arch/arm/cpu/armv7/keystone/keystone.c
Normal file
87
arch/arm/cpu/armv7/keystone/keystone.c
Normal file
@ -0,0 +1,87 @@
|
||||
/*
|
||||
* Keystone EVM : Board initialization
|
||||
*
|
||||
* (C) Copyright 2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mon.h>
|
||||
#include <asm/arch/psc_defs.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
/**
|
||||
* cpu_to_bus - swap bytes of the 32-bit data if the device is BE
|
||||
* @ptr - array of data
|
||||
* @length - lenght of data array
|
||||
*/
|
||||
int cpu_to_bus(u32 *ptr, u32 length)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
if (!(readl(KS2_DEVSTAT) & 0x1))
|
||||
for (i = 0; i < length; i++, ptr++)
|
||||
*ptr = cpu_to_be32(*ptr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int turn_off_myself(void)
|
||||
{
|
||||
printf("Turning off ourselves\r\n");
|
||||
mon_power_off(0);
|
||||
|
||||
psc_disable_module(KS2_LPSC_TETRIS);
|
||||
psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
|
||||
|
||||
asm volatile ("isb\n"
|
||||
"dsb\n"
|
||||
"wfi\n");
|
||||
|
||||
printf("What! Should not see that\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void turn_off_all_dsps(int num_dsps)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_dsps; i++) {
|
||||
if (psc_disable_module(i + KS2_LPSC_GEM_0))
|
||||
printf("Cannot disable module for #%d DSP", i);
|
||||
|
||||
if (psc_disable_domain(i + 8))
|
||||
printf("Cannot disable domain for #%d DSP", i);
|
||||
}
|
||||
}
|
||||
|
||||
int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
return turn_off_myself();
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
killme, 1, 0, do_killme_cmd,
|
||||
"turn off main ARM core",
|
||||
"turn off main ARM core. Should not live after that :(\n"
|
||||
);
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
char *env;
|
||||
long ks2_debug = 0;
|
||||
|
||||
env = getenv("ks2_debug");
|
||||
|
||||
if (env)
|
||||
ks2_debug = simple_strtol(env, NULL, 0);
|
||||
|
||||
if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0)
|
||||
turn_off_all_dsps(KS2_NUM_DSPS);
|
||||
|
||||
return 0;
|
||||
}
|
@ -8,7 +8,7 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/msmc.h>
|
||||
|
||||
struct mpax {
|
||||
u32 mpaxl;
|
||||
@ -56,9 +56,9 @@ struct msms_regs {
|
||||
};
|
||||
|
||||
|
||||
void share_all_segments(int priv_id)
|
||||
void msmc_share_all_segments(int priv_id)
|
||||
{
|
||||
struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE;
|
||||
struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
|
||||
int j;
|
||||
|
||||
for (j = 0; j < 8; j++) {
|
||||
|
@ -16,10 +16,6 @@
|
||||
#define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr))
|
||||
#define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr))
|
||||
|
||||
#ifdef CONFIG_SOC_K2HK
|
||||
#define DEVICE_PSC_BASE K2HK_PSC_BASE
|
||||
#endif
|
||||
|
||||
int psc_delay(void)
|
||||
{
|
||||
udelay(10);
|
||||
@ -55,7 +51,7 @@ int psc_wait(u32 domain_num)
|
||||
retry = 0;
|
||||
|
||||
do {
|
||||
ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
|
||||
ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT);
|
||||
ptstat = ptstat & (1 << domain_num);
|
||||
} while ((ptstat != 0) && ((retry += psc_delay()) <
|
||||
PSC_PTSTAT_TIMEOUT_LIMIT));
|
||||
@ -71,7 +67,7 @@ u32 psc_get_domain_num(u32 mod_num)
|
||||
u32 domain_num;
|
||||
|
||||
/* Get the power domain associated with the module number */
|
||||
domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
|
||||
domain_num = DEVICE_REG32_R(KS2_PSC_BASE +
|
||||
PSC_REG_MDCFG(mod_num));
|
||||
domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
|
||||
|
||||
@ -106,7 +102,7 @@ int psc_set_state(u32 mod_num, u32 state)
|
||||
* Get the power domain associated with the module number, and reset
|
||||
* isolation functionality
|
||||
*/
|
||||
v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
|
||||
v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
|
||||
domain_num = PSC_REG_MDCFG_GET_PD(v);
|
||||
reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
|
||||
|
||||
@ -123,24 +119,24 @@ int psc_set_state(u32 mod_num, u32 state)
|
||||
* change is made if the new state is power down.
|
||||
*/
|
||||
if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
|
||||
pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
|
||||
pdctl = DEVICE_REG32_R(KS2_PSC_BASE +
|
||||
PSC_REG_PDCTL(domain_num));
|
||||
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
|
||||
PSC_REG_VAL_PDCTL_NEXT_ON);
|
||||
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
|
||||
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num),
|
||||
pdctl);
|
||||
}
|
||||
|
||||
/* Set the next state for the module to enabled/disabled */
|
||||
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
|
||||
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
|
||||
mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
|
||||
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
|
||||
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
|
||||
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
|
||||
|
||||
/* Trigger the enable */
|
||||
ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
|
||||
ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
|
||||
ptcmd |= (u32)(1<<domain_num);
|
||||
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
|
||||
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
|
||||
|
||||
/* Wait on the complete */
|
||||
return psc_wait(domain_num);
|
||||
@ -161,7 +157,7 @@ int psc_enable_module(u32 mod_num)
|
||||
u32 mdctl;
|
||||
|
||||
/* Set the bit to apply reset */
|
||||
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
|
||||
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
|
||||
if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
|
||||
return 0;
|
||||
|
||||
@ -180,11 +176,11 @@ int psc_disable_module(u32 mod_num)
|
||||
u32 mdctl;
|
||||
|
||||
/* Set the bit to apply reset */
|
||||
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
|
||||
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
|
||||
if ((mdctl & 0x3f) == 0)
|
||||
return 0;
|
||||
mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
|
||||
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
|
||||
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
|
||||
|
||||
return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
|
||||
}
|
||||
@ -203,11 +199,11 @@ int psc_set_reset_iso(u32 mod_num)
|
||||
u32 mdctl;
|
||||
|
||||
/* Set the reset isolation bit */
|
||||
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
|
||||
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
|
||||
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
|
||||
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
|
||||
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
|
||||
|
||||
v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
|
||||
v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
|
||||
if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
|
||||
return 0;
|
||||
|
||||
@ -224,14 +220,14 @@ int psc_disable_domain(u32 domain_num)
|
||||
u32 pdctl;
|
||||
u32 ptcmd;
|
||||
|
||||
pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num));
|
||||
pdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
|
||||
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
|
||||
pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
|
||||
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
|
||||
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
|
||||
|
||||
ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
|
||||
ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
|
||||
ptcmd |= (u32)(1 << domain_num);
|
||||
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
|
||||
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
|
||||
|
||||
return psc_wait(domain_num);
|
||||
}
|
||||
|
@ -18,10 +18,18 @@
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_K2HK_EVM
|
||||
static struct pll_init_data spl_pll_config[] = {
|
||||
CORE_PLL_799,
|
||||
TETRIS_PLL_500,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_K2E_EVM
|
||||
static struct pll_init_data spl_pll_config[] = {
|
||||
CORE_PLL_800,
|
||||
};
|
||||
#endif
|
||||
|
||||
void spl_init_keystone_plls(void)
|
||||
{
|
||||
|
@ -10,10 +10,13 @@
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/gic.h>
|
||||
#include <asm/armv7.h>
|
||||
#include <asm/proc-armv/ptrace.h>
|
||||
|
||||
.arch_extension sec
|
||||
.arch_extension virt
|
||||
|
||||
.pushsection ._secure.text, "ax"
|
||||
|
||||
.align 5
|
||||
/* the vector table for secure state and HYP mode */
|
||||
_monitor_vectors:
|
||||
@ -22,43 +25,95 @@ _monitor_vectors:
|
||||
adr pc, _secure_monitor
|
||||
.word 0
|
||||
.word 0
|
||||
adr pc, _hyp_trap
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
|
||||
.macro is_cpu_virt_capable tmp
|
||||
mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1
|
||||
and \tmp, \tmp, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
|
||||
cmp \tmp, #(1 << CPUID_ARM_VIRT_SHIFT)
|
||||
.endm
|
||||
|
||||
/*
|
||||
* secure monitor handler
|
||||
* U-boot calls this "software interrupt" in start.S
|
||||
* This is executed on a "smc" instruction, we use a "smc #0" to switch
|
||||
* to non-secure state.
|
||||
* We use only r0 and r1 here, due to constraints in the caller.
|
||||
* r0, r1, r2: passed to the callee
|
||||
* ip: target PC
|
||||
*/
|
||||
_secure_monitor:
|
||||
mrc p15, 0, r1, c1, c1, 0 @ read SCR
|
||||
bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits
|
||||
orr r1, r1, #0x31 @ enable NS, AW, FW bits
|
||||
#ifdef CONFIG_ARMV7_PSCI
|
||||
ldr r5, =_psci_vectors @ Switch to the next monitor
|
||||
mcr p15, 0, r5, c12, c0, 1
|
||||
isb
|
||||
|
||||
#ifdef CONFIG_ARMV7_VIRT
|
||||
mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
|
||||
and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
|
||||
cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
|
||||
orreq r1, r1, #0x100 @ allow HVC instruction
|
||||
@ Obtain a secure stack, and configure the PSCI backend
|
||||
bl psci_arch_init
|
||||
#endif
|
||||
|
||||
mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
|
||||
|
||||
mrc p15, 0, r5, c1, c1, 0 @ read SCR
|
||||
bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
|
||||
orr r5, r5, #0x31 @ enable NS, AW, FW bits
|
||||
@ FIQ preserved for secure mode
|
||||
mov r6, #SVC_MODE @ default mode is SVC
|
||||
is_cpu_virt_capable r4
|
||||
#ifdef CONFIG_ARMV7_VIRT
|
||||
mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value
|
||||
mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR
|
||||
orreq r5, r5, #0x100 @ allow HVC instruction
|
||||
moveq r6, #HYP_MODE @ Enter the kernel as HYP
|
||||
#endif
|
||||
|
||||
movs pc, lr @ return to non-secure SVC
|
||||
mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
|
||||
isb
|
||||
|
||||
_hyp_trap:
|
||||
mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1
|
||||
mov pc, lr @ do no switch modes, but
|
||||
@ return to caller
|
||||
bne 1f
|
||||
|
||||
@ Reset CNTVOFF to 0 before leaving monitor mode
|
||||
mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1
|
||||
ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits
|
||||
movne r4, #0
|
||||
mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
|
||||
1:
|
||||
mov lr, ip
|
||||
mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F
|
||||
tst lr, #1 @ Check for Thumb PC
|
||||
orrne ip, ip, #T_BIT @ Set T if Thumb
|
||||
orr ip, ip, r6 @ Slot target mode in
|
||||
msr spsr_cxfs, ip @ Set full SPSR
|
||||
movs pc, lr @ ERET to non-secure
|
||||
|
||||
ENTRY(_do_nonsec_entry)
|
||||
mov ip, r0
|
||||
mov r0, r1
|
||||
mov r1, r2
|
||||
mov r2, r3
|
||||
smc #0
|
||||
ENDPROC(_do_nonsec_entry)
|
||||
|
||||
.macro get_cbar_addr addr
|
||||
#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
|
||||
ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS
|
||||
#else
|
||||
mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
|
||||
bfc \addr, #0, #15 @ clear reserved bits
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro get_gicd_addr addr
|
||||
get_cbar_addr \addr
|
||||
add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset
|
||||
.endm
|
||||
|
||||
.macro get_gicc_addr addr, tmp
|
||||
get_cbar_addr \addr
|
||||
is_cpu_virt_capable \tmp
|
||||
movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
|
||||
moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
|
||||
add \addr, \addr, \tmp
|
||||
.endm
|
||||
|
||||
#ifndef CONFIG_ARMV7_PSCI
|
||||
/*
|
||||
* Secondary CPUs start here and call the code for the core specific parts
|
||||
* of the non-secure and HYP mode transition. The GIC distributor specific
|
||||
@ -66,31 +121,21 @@ _hyp_trap:
|
||||
* Then they go back to wfi and wait to be woken up by the kernel again.
|
||||
*/
|
||||
ENTRY(_smp_pen)
|
||||
mrs r0, cpsr
|
||||
orr r0, r0, #0xc0
|
||||
msr cpsr, r0 @ disable interrupts
|
||||
ldr r1, =_start
|
||||
mcr p15, 0, r1, c12, c0, 0 @ set VBAR
|
||||
cpsid i
|
||||
cpsid f
|
||||
|
||||
bl _nonsec_init
|
||||
mov r12, r0 @ save GICC address
|
||||
#ifdef CONFIG_ARMV7_VIRT
|
||||
bl _switch_to_hyp
|
||||
#endif
|
||||
|
||||
ldr r1, [r12, #GICC_IAR] @ acknowledge IPI
|
||||
str r1, [r12, #GICC_EOIR] @ signal end of interrupt
|
||||
|
||||
adr r0, _smp_pen @ do not use this address again
|
||||
b smp_waitloop @ wait for IPIs, board specific
|
||||
ENDPROC(_smp_pen)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Switch a core to non-secure state.
|
||||
*
|
||||
* 1. initialize the GIC per-core interface
|
||||
* 2. allow coprocessor access in non-secure modes
|
||||
* 3. switch the cpu mode (by calling "smc #0")
|
||||
*
|
||||
* Called from smp_pen by secondary cores and directly by the BSP.
|
||||
* Do not assume that the stack is available and only use registers
|
||||
@ -100,38 +145,23 @@ ENDPROC(_smp_pen)
|
||||
* though, but we check this in C before calling this function.
|
||||
*/
|
||||
ENTRY(_nonsec_init)
|
||||
#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
|
||||
ldr r2, =CONFIG_ARM_GIC_BASE_ADDRESS
|
||||
#else
|
||||
mrc p15, 4, r2, c15, c0, 0 @ read CBAR
|
||||
bfc r2, #0, #15 @ clear reserved bits
|
||||
#endif
|
||||
add r3, r2, #GIC_DIST_OFFSET @ GIC dist i/f offset
|
||||
get_gicd_addr r3
|
||||
|
||||
mvn r1, #0 @ all bits to 1
|
||||
str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts
|
||||
|
||||
mrc p15, 0, r0, c0, c0, 0 @ read MIDR
|
||||
ldr r1, =MIDR_PRIMARY_PART_MASK
|
||||
and r0, r0, r1 @ mask out variant and revision
|
||||
get_gicc_addr r3, r1
|
||||
|
||||
ldr r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK
|
||||
cmp r0, r1 @ check for Cortex-A7
|
||||
|
||||
ldr r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK
|
||||
cmpne r0, r1 @ check for Cortex-A15
|
||||
|
||||
movne r1, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
|
||||
moveq r1, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
|
||||
add r3, r2, r1 @ r3 = GIC CPU i/f addr
|
||||
|
||||
mov r1, #1 @ set GICC_CTLR[enable]
|
||||
mov r1, #3 @ Enable both groups
|
||||
str r1, [r3, #GICC_CTLR] @ and clear all other bits
|
||||
mov r1, #0xff
|
||||
str r1, [r3, #GICC_PMR] @ set priority mask register
|
||||
|
||||
mrc p15, 0, r0, c1, c1, 2
|
||||
movw r1, #0x3fff
|
||||
movt r1, #0x0006
|
||||
mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec
|
||||
movt r1, #0x0004
|
||||
orr r0, r0, r1
|
||||
mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec
|
||||
|
||||
/* The CNTFRQ register of the generic timer needs to be
|
||||
* programmed in secure state. Some primary bootloaders / firmware
|
||||
@ -149,21 +179,9 @@ ENTRY(_nonsec_init)
|
||||
|
||||
adr r1, _monitor_vectors
|
||||
mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
|
||||
|
||||
mrc p15, 0, ip, c12, c0, 0 @ save secure copy of VBAR
|
||||
|
||||
isb
|
||||
smc #0 @ call into MONITOR mode
|
||||
|
||||
mcr p15, 0, ip, c12, c0, 0 @ write non-secure copy of VBAR
|
||||
|
||||
mov r1, #1
|
||||
str r1, [r3, #GICC_CTLR] @ enable non-secure CPU i/f
|
||||
add r2, r2, #GIC_DIST_OFFSET
|
||||
str r1, [r2, #GICD_CTLR] @ allow private interrupts
|
||||
|
||||
mov r0, r3 @ return GICC address
|
||||
|
||||
bx lr
|
||||
ENDPROC(_nonsec_init)
|
||||
|
||||
@ -175,18 +193,10 @@ ENTRY(smp_waitloop)
|
||||
ldr r1, [r1]
|
||||
cmp r0, r1 @ make sure we dont execute this code
|
||||
beq smp_waitloop @ again (due to a spurious wakeup)
|
||||
mov pc, r1
|
||||
mov r0, r1
|
||||
b _do_nonsec_entry
|
||||
ENDPROC(smp_waitloop)
|
||||
.weak smp_waitloop
|
||||
#endif
|
||||
|
||||
ENTRY(_switch_to_hyp)
|
||||
mov r0, lr
|
||||
mov r1, sp @ save SVC copy of LR and SP
|
||||
isb
|
||||
hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
|
||||
mov sp, r1
|
||||
mov lr, r0 @ restore SVC copy of LR and SP
|
||||
|
||||
bx lr
|
||||
ENDPROC(_switch_to_hyp)
|
||||
.popsection
|
||||
|
@ -123,7 +123,8 @@ void s_init(void)
|
||||
hw_data_init();
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
|
||||
if (warm_reset() &&
|
||||
(is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
|
||||
force_emif_self_refresh();
|
||||
#endif
|
||||
watchdog_init();
|
||||
|
@ -87,9 +87,13 @@ void gpmc_init(void)
|
||||
STNOR_GPMC_CONFIG6,
|
||||
STNOR_GPMC_CONFIG7
|
||||
};
|
||||
u32 size = GPMC_SIZE_16M;
|
||||
u32 base = CONFIG_SYS_FLASH_BASE;
|
||||
#elif defined(CONFIG_NAND)
|
||||
u32 size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
|
||||
/* > 64MB */ ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
|
||||
/* > 32MB */ ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
|
||||
/* > 16MB */ ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
|
||||
/* min 16MB */ GPMC_SIZE_16M)));
|
||||
#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
|
||||
/* configure GPMC for NAND */
|
||||
const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
|
||||
M_NAND_GPMC_CONFIG2,
|
||||
@ -99,8 +103,9 @@ void gpmc_init(void)
|
||||
M_NAND_GPMC_CONFIG6,
|
||||
0
|
||||
};
|
||||
u32 size = GPMC_SIZE_256M;
|
||||
u32 base = CONFIG_SYS_NAND_BASE;
|
||||
u32 size = GPMC_SIZE_16M;
|
||||
|
||||
#elif defined(CONFIG_CMD_ONENAND)
|
||||
const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1,
|
||||
ONENAND_GPMC_CONFIG2,
|
||||
@ -110,8 +115,8 @@ void gpmc_init(void)
|
||||
ONENAND_GPMC_CONFIG6,
|
||||
0
|
||||
};
|
||||
u32 base = PISMO1_ONEN_BASE;
|
||||
u32 size = PISMO1_ONEN_SIZE;
|
||||
u32 size = GPMC_SIZE_128M;
|
||||
u32 base = CONFIG_SYS_ONENAND_BASE;
|
||||
#else
|
||||
const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
|
||||
u32 size = 0;
|
||||
|
@ -1,139 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author :
|
||||
* Manikandan Pillai <mani.pillai@ti.com>
|
||||
*
|
||||
* Initial Code from:
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <command.h>
|
||||
|
||||
struct gpmc *gpmc_cfg;
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
|
||||
M_NAND_GPMC_CONFIG1,
|
||||
M_NAND_GPMC_CONFIG2,
|
||||
M_NAND_GPMC_CONFIG3,
|
||||
M_NAND_GPMC_CONFIG4,
|
||||
M_NAND_GPMC_CONFIG5,
|
||||
M_NAND_GPMC_CONFIG6, 0
|
||||
};
|
||||
#endif /* CONFIG_CMD_NAND */
|
||||
|
||||
#if defined(CONFIG_CMD_ONENAND)
|
||||
static const u32 gpmc_onenand[GPMC_MAX_REG] = {
|
||||
ONENAND_GPMC_CONFIG1,
|
||||
ONENAND_GPMC_CONFIG2,
|
||||
ONENAND_GPMC_CONFIG3,
|
||||
ONENAND_GPMC_CONFIG4,
|
||||
ONENAND_GPMC_CONFIG5,
|
||||
ONENAND_GPMC_CONFIG6, 0
|
||||
};
|
||||
#endif /* CONFIG_CMD_ONENAND */
|
||||
|
||||
/********************************************************
|
||||
* mem_ok() - test used to see if timings are correct
|
||||
* for a part. Helps in guessing which part
|
||||
* we are currently using.
|
||||
*******************************************************/
|
||||
u32 mem_ok(u32 cs)
|
||||
{
|
||||
u32 val1, val2, addr;
|
||||
u32 pattern = 0x12345678;
|
||||
|
||||
addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
|
||||
|
||||
writel(0x0, addr + 0x400); /* clear pos A */
|
||||
writel(pattern, addr); /* pattern to pos B */
|
||||
writel(0x0, addr + 4); /* remove pattern off the bus */
|
||||
val1 = readl(addr + 0x400); /* get pos A value */
|
||||
val2 = readl(addr); /* get val2 */
|
||||
writel(0x0, addr + 0x400); /* clear pos A */
|
||||
|
||||
if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
|
||||
u32 size)
|
||||
{
|
||||
writel(0, &cs->config7);
|
||||
sdelay(1000);
|
||||
/* Delay for settling */
|
||||
writel(gpmc_config[0], &cs->config1);
|
||||
writel(gpmc_config[1], &cs->config2);
|
||||
writel(gpmc_config[2], &cs->config3);
|
||||
writel(gpmc_config[3], &cs->config4);
|
||||
writel(gpmc_config[4], &cs->config5);
|
||||
writel(gpmc_config[5], &cs->config6);
|
||||
|
||||
/*
|
||||
* Enable the config. size is the CS size and goes in
|
||||
* bits 11:8. We set bit 6 to enable this CS and the base
|
||||
* address goes into bits 5:0.
|
||||
*/
|
||||
writel((size << 8) | (GPMC_CS_ENABLE << 6) |
|
||||
((base >> 24) & GPMC_BASEADDR_MASK),
|
||||
&cs->config7);
|
||||
sdelay(2000);
|
||||
}
|
||||
|
||||
/*****************************************************
|
||||
* gpmc_init(): init gpmc bus
|
||||
* Init GPMC for x16, MuxMode (SDRAM in x32).
|
||||
* This code can only be executed from SRAM or SDRAM.
|
||||
*****************************************************/
|
||||
void gpmc_init(void)
|
||||
{
|
||||
/* putting a blanket check on GPMC based on ZeBu for now */
|
||||
gpmc_cfg = (struct gpmc *)GPMC_BASE;
|
||||
#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
|
||||
const u32 *gpmc_config = NULL;
|
||||
u32 base = 0;
|
||||
u32 size = 0;
|
||||
#endif
|
||||
u32 config = 0;
|
||||
|
||||
/* global settings */
|
||||
writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
|
||||
writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
|
||||
|
||||
config = readl(&gpmc_cfg->config);
|
||||
config &= (~0xf00);
|
||||
writel(config, &gpmc_cfg->config);
|
||||
|
||||
/*
|
||||
* Disable the GPMC0 config set by ROM code
|
||||
* It conflicts with our MPDB (both at 0x08000000)
|
||||
*/
|
||||
writel(0, &gpmc_cfg->cs[0].config7);
|
||||
sdelay(1000);
|
||||
|
||||
#if defined(CONFIG_CMD_NAND) /* CS 0 */
|
||||
gpmc_config = gpmc_m_nand;
|
||||
|
||||
base = PISMO1_NAND_BASE;
|
||||
size = PISMO1_NAND_SIZE;
|
||||
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_ONENAND)
|
||||
gpmc_config = gpmc_onenand;
|
||||
base = PISMO1_ONEN_BASE;
|
||||
size = PISMO1_ONEN_SIZE;
|
||||
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
|
||||
#endif
|
||||
}
|
102
arch/arm/cpu/armv7/psci.S
Normal file
102
arch/arm/cpu/armv7/psci.S
Normal file
@ -0,0 +1,102 @@
|
||||
/*
|
||||
* Copyright (C) 2013,2014 - ARM Ltd
|
||||
* Author: Marc Zyngier <marc.zyngier@arm.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/psci.h>
|
||||
|
||||
.pushsection ._secure.text, "ax"
|
||||
|
||||
.arch_extension sec
|
||||
|
||||
.align 5
|
||||
.globl _psci_vectors
|
||||
_psci_vectors:
|
||||
b default_psci_vector @ reset
|
||||
b default_psci_vector @ undef
|
||||
b _smc_psci @ smc
|
||||
b default_psci_vector @ pabort
|
||||
b default_psci_vector @ dabort
|
||||
b default_psci_vector @ hyp
|
||||
b default_psci_vector @ irq
|
||||
b psci_fiq_enter @ fiq
|
||||
|
||||
ENTRY(psci_fiq_enter)
|
||||
movs pc, lr
|
||||
ENDPROC(psci_fiq_enter)
|
||||
.weak psci_fiq_enter
|
||||
|
||||
ENTRY(default_psci_vector)
|
||||
movs pc, lr
|
||||
ENDPROC(default_psci_vector)
|
||||
.weak default_psci_vector
|
||||
|
||||
ENTRY(psci_cpu_suspend)
|
||||
ENTRY(psci_cpu_off)
|
||||
ENTRY(psci_cpu_on)
|
||||
ENTRY(psci_migrate)
|
||||
mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented)
|
||||
mov pc, lr
|
||||
ENDPROC(psci_migrate)
|
||||
ENDPROC(psci_cpu_on)
|
||||
ENDPROC(psci_cpu_off)
|
||||
ENDPROC(psci_cpu_suspend)
|
||||
.weak psci_cpu_suspend
|
||||
.weak psci_cpu_off
|
||||
.weak psci_cpu_on
|
||||
.weak psci_migrate
|
||||
|
||||
_psci_table:
|
||||
.word ARM_PSCI_FN_CPU_SUSPEND
|
||||
.word psci_cpu_suspend
|
||||
.word ARM_PSCI_FN_CPU_OFF
|
||||
.word psci_cpu_off
|
||||
.word ARM_PSCI_FN_CPU_ON
|
||||
.word psci_cpu_on
|
||||
.word ARM_PSCI_FN_MIGRATE
|
||||
.word psci_migrate
|
||||
.word 0
|
||||
.word 0
|
||||
|
||||
_smc_psci:
|
||||
push {r4-r7,lr}
|
||||
|
||||
@ Switch to secure
|
||||
mrc p15, 0, r7, c1, c1, 0
|
||||
bic r4, r7, #1
|
||||
mcr p15, 0, r4, c1, c1, 0
|
||||
isb
|
||||
|
||||
adr r4, _psci_table
|
||||
1: ldr r5, [r4] @ Load PSCI function ID
|
||||
ldr r6, [r4, #4] @ Load target PC
|
||||
cmp r5, #0 @ If reach the end, bail out
|
||||
moveq r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid)
|
||||
beq 2f
|
||||
cmp r0, r5 @ If not matching, try next entry
|
||||
addne r4, r4, #8
|
||||
bne 1b
|
||||
|
||||
blx r6 @ Execute PSCI function
|
||||
|
||||
@ Switch back to non-secure
|
||||
2: mcr p15, 0, r7, c1, c1, 0
|
||||
|
||||
pop {r4-r7, lr}
|
||||
movs pc, lr @ Return to the kernel
|
||||
|
||||
.popsection
|
@ -13,5 +13,6 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o
|
||||
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
|
||||
obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
|
||||
obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
|
||||
obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
|
||||
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
|
||||
obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
|
||||
|
@ -53,6 +53,7 @@ static const struct {
|
||||
{ 0x40, "R8A7740" },
|
||||
{ 0x45, "R8A7790" },
|
||||
{ 0x47, "R8A7791" },
|
||||
{ 0x4C, "R8A7794" },
|
||||
{ 0x0, "CPU" },
|
||||
};
|
||||
|
||||
|
1513
arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
Normal file
1513
arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -11,6 +11,8 @@ obj-y += timer.o
|
||||
obj-y += board.o
|
||||
obj-y += clock.o
|
||||
obj-y += pinmux.o
|
||||
obj-$(CONFIG_SUN4I) += clock_sun4i.o
|
||||
obj-$(CONFIG_SUN5I) += clock_sun4i.o
|
||||
obj-$(CONFIG_SUN7I) += clock_sun4i.o
|
||||
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
@ -18,6 +20,8 @@ obj-y += cpu_info.o
|
||||
endif
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-$(CONFIG_SUN4I) += dram.o
|
||||
obj-$(CONFIG_SUN5I) += dram.o
|
||||
obj-$(CONFIG_SUN7I) += dram.o
|
||||
ifdef CONFIG_SPL_FEL
|
||||
obj-y += start.o
|
||||
|
@ -11,6 +11,7 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <netdev.h>
|
||||
#include <miiphy.h>
|
||||
#include <serial.h>
|
||||
@ -24,6 +25,8 @@
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/timer.h>
|
||||
|
||||
#include <linux/compiler.h>
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/* Pointer to the global data structure for SPL */
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
@ -47,15 +50,38 @@ u32 spl_boot_mode(void)
|
||||
|
||||
int gpio_init(void)
|
||||
{
|
||||
#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
|
||||
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
|
||||
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
|
||||
sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
|
||||
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
|
||||
sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
|
||||
sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
|
||||
sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
|
||||
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
|
||||
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
|
||||
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
|
||||
sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
|
||||
#else
|
||||
#error Unsupported console port number. Please fix pin mux settings in board.c
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
static const struct sunxi_wdog *wdog =
|
||||
&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
|
||||
|
||||
/* Set the watchdog for its shortest interval (.5s) and wait */
|
||||
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
|
||||
writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
|
||||
|
||||
while (1) {
|
||||
/* sun5i sometimes gets stuck without this */
|
||||
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
|
||||
}
|
||||
}
|
||||
|
||||
/* do some early init */
|
||||
@ -72,11 +98,16 @@ void s_init(void)
|
||||
clock_init();
|
||||
timer_init();
|
||||
gpio_init();
|
||||
i2c_init_board();
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
gd = &gdata;
|
||||
preloader_console_init();
|
||||
|
||||
#ifdef CONFIG_SPL_I2C_SUPPORT
|
||||
/* Needed early by sunxi_board_init if PMU is enabled */
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
#endif
|
||||
sunxi_board_init();
|
||||
#endif
|
||||
}
|
||||
@ -96,7 +127,15 @@ void enable_caches(void)
|
||||
*/
|
||||
int cpu_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc;
|
||||
__maybe_unused int rc;
|
||||
|
||||
#ifdef CONFIG_SUNXI_EMAC
|
||||
rc = sunxi_emac_initialize(bis);
|
||||
if (rc < 0) {
|
||||
printf("sunxi: failed to initialize emac\n");
|
||||
return rc;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SUNXI_GMAC
|
||||
rc = sunxi_gmac_initialize(bis);
|
||||
|
@ -36,8 +36,7 @@ void clock_init_safe(void)
|
||||
CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
|
||||
&ccm->cpu_ahb_apb0_cfg);
|
||||
#ifdef CONFIG_SUN7I
|
||||
writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
|
||||
&ccm->ahb_gate0);
|
||||
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
|
||||
#endif
|
||||
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
|
||||
}
|
||||
|
@ -13,7 +13,22 @@
|
||||
#ifdef CONFIG_DISPLAY_CPUINFO
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
#ifdef CONFIG_SUN4I
|
||||
puts("CPU: Allwinner A10 (SUN4I)\n");
|
||||
#elif defined CONFIG_SUN5I
|
||||
u32 val = readl(SUNXI_SID_BASE + 0x08);
|
||||
switch ((val >> 12) & 0xf) {
|
||||
case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break;
|
||||
case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break;
|
||||
case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break;
|
||||
default: puts("CPU: Allwinner A1X (SUN5I)\n");
|
||||
}
|
||||
#elif defined CONFIG_SUN7I
|
||||
puts("CPU: Allwinner A20 (SUN7I)\n");
|
||||
#else
|
||||
#warning Please update cpu_info.c with correct CPU information
|
||||
puts("CPU: SUNXI Family\n");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
@ -53,16 +53,37 @@ static void mctl_ddr3_reset(void)
|
||||
struct sunxi_dram_reg *dram =
|
||||
(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
|
||||
|
||||
#ifdef CONFIG_SUN4I
|
||||
struct sunxi_timer_reg *timer =
|
||||
(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
|
||||
u32 reg_val;
|
||||
|
||||
writel(0, &timer->cpu_cfg);
|
||||
reg_val = readl(&timer->cpu_cfg);
|
||||
|
||||
if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
|
||||
CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
|
||||
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
|
||||
udelay(2);
|
||||
clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
|
||||
udelay(2);
|
||||
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
|
||||
}
|
||||
}
|
||||
|
||||
static void mctl_set_drive(void)
|
||||
{
|
||||
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
|
||||
|
||||
#ifdef CONFIG_SUN7I
|
||||
clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
|
||||
#else
|
||||
clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
|
||||
#endif
|
||||
DRAM_MCR_MODE_EN(0x3) |
|
||||
0xffc);
|
||||
}
|
||||
@ -134,6 +155,26 @@ static void mctl_enable_dllx(u32 phase)
|
||||
}
|
||||
|
||||
static u32 hpcr_value[32] = {
|
||||
#ifdef CONFIG_SUN5I
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0x1031, 0x1031, 0x0735, 0x1035,
|
||||
0x1035, 0x0731, 0x1031, 0,
|
||||
0x0301, 0x0301, 0x0301, 0x0301,
|
||||
0x0301, 0x0301, 0x0301, 0
|
||||
#endif
|
||||
#ifdef CONFIG_SUN4I
|
||||
0x0301, 0x0301, 0x0301, 0x0301,
|
||||
0x0301, 0x0301, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0x1031, 0x1031, 0x0735, 0x5031,
|
||||
0x1035, 0x0731, 0x1031, 0x0735,
|
||||
0x1035, 0x1031, 0x0731, 0x1035,
|
||||
0x1031, 0x0301, 0x0301, 0x0731
|
||||
#endif
|
||||
#ifdef CONFIG_SUN7I
|
||||
0x0301, 0x0301, 0x0301, 0x0301,
|
||||
0x0301, 0x0301, 0x0301, 0x0301,
|
||||
@ -223,22 +264,38 @@ static void mctl_setup_dram_clock(u32 clk)
|
||||
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
|
||||
/* setup MBUS clock */
|
||||
reg_val = CCM_MBUS_CTRL_GATE |
|
||||
#ifdef CONFIG_SUN7I
|
||||
CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
|
||||
CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
|
||||
CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
|
||||
#else /* defined(CONFIG_SUN5I) */
|
||||
CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
|
||||
CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
|
||||
CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
|
||||
#endif
|
||||
writel(reg_val, &ccm->mbus_clk_cfg);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* open DRAMC AHB & DLL register clock
|
||||
* close it first
|
||||
*/
|
||||
#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
|
||||
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
|
||||
#else
|
||||
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
|
||||
#endif
|
||||
udelay(22);
|
||||
|
||||
/* then open it */
|
||||
#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
|
||||
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
|
||||
#else
|
||||
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
|
||||
#endif
|
||||
udelay(22);
|
||||
}
|
||||
|
||||
@ -385,6 +442,13 @@ static void dramc_clock_output_en(u32 on)
|
||||
else
|
||||
clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
|
||||
#endif
|
||||
#ifdef CONFIG_SUN4I
|
||||
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
||||
if (on)
|
||||
setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
|
||||
else
|
||||
clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
|
||||
#endif
|
||||
}
|
||||
|
||||
static const u16 tRFC_table[2][6] = {
|
||||
@ -420,12 +484,25 @@ unsigned long dramc_init(struct dram_para *para)
|
||||
/* setup DRAM relative clock */
|
||||
mctl_setup_dram_clock(para->clock);
|
||||
|
||||
#ifdef CONFIG_SUN5I
|
||||
/* Disable any pad power save control */
|
||||
writel(0, &dram->ppwrsctl);
|
||||
#endif
|
||||
|
||||
/* reset external DRAM */
|
||||
#ifndef CONFIG_SUN7I
|
||||
mctl_ddr3_reset();
|
||||
#endif
|
||||
mctl_set_drive();
|
||||
|
||||
/* dram clock off */
|
||||
dramc_clock_output_en(0);
|
||||
|
||||
#ifdef CONFIG_SUN4I
|
||||
/* select dram controller 1 */
|
||||
writel(DRAM_CSEL_MAGIC, &dram->csel);
|
||||
#endif
|
||||
|
||||
mctl_itm_disable();
|
||||
mctl_enable_dll0(para->tpr3);
|
||||
|
||||
@ -482,6 +559,9 @@ unsigned long dramc_init(struct dram_para *para)
|
||||
mctl_ddr3_reset();
|
||||
else
|
||||
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
|
||||
#else
|
||||
/* dram clock on */
|
||||
dramc_clock_output_en(1);
|
||||
#endif
|
||||
|
||||
udelay(1);
|
||||
@ -490,6 +570,22 @@ unsigned long dramc_init(struct dram_para *para)
|
||||
|
||||
mctl_enable_dllx(para->tpr3);
|
||||
|
||||
#ifdef CONFIG_SUN4I
|
||||
/* set odt impedance divide ratio */
|
||||
reg_val = ((para->zq) >> 8) & 0xfffff;
|
||||
reg_val |= ((para->zq) & 0xff) << 20;
|
||||
reg_val |= (para->zq) & 0xf0000000;
|
||||
writel(reg_val, &dram->zqcr0);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SUN4I
|
||||
/* set I/O configure register */
|
||||
reg_val = 0x00cc0000;
|
||||
reg_val |= (para->odt_en) & 0x3;
|
||||
reg_val |= ((para->odt_en) & 0x3) << 30;
|
||||
writel(reg_val, &dram->iocr);
|
||||
#endif
|
||||
|
||||
/* set refresh period */
|
||||
dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);
|
||||
|
||||
|
@ -26,6 +26,11 @@ SECTIONS
|
||||
*(.data*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
. = .;
|
||||
|
||||
|
@ -27,6 +27,7 @@ SECTIONS
|
||||
.text :
|
||||
{
|
||||
__start = .;
|
||||
*(.vectors)
|
||||
arch/arm/cpu/armv7/start.o (.text)
|
||||
*(.text*)
|
||||
} > .sram
|
||||
@ -37,6 +38,11 @@ SECTIONS
|
||||
. = ALIGN(4);
|
||||
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
} > .sram
|
||||
|
||||
. = ALIGN(4);
|
||||
__image_copy_end = .;
|
||||
_end = .;
|
||||
|
100
arch/arm/cpu/armv7/virt-dt.c
Normal file
100
arch/arm/cpu/armv7/virt-dt.c
Normal file
@ -0,0 +1,100 @@
|
||||
/*
|
||||
* Copyright (C) 2013 - ARM Ltd
|
||||
* Author: Marc Zyngier <marc.zyngier@arm.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <stdio_dev.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/armv7.h>
|
||||
#include <asm/psci.h>
|
||||
|
||||
static int fdt_psci(void *fdt)
|
||||
{
|
||||
#ifdef CONFIG_ARMV7_PSCI
|
||||
int nodeoff;
|
||||
int tmp;
|
||||
|
||||
nodeoff = fdt_path_offset(fdt, "/cpus");
|
||||
if (nodeoff < 0) {
|
||||
printf("couldn't find /cpus\n");
|
||||
return nodeoff;
|
||||
}
|
||||
|
||||
/* add 'enable-method = "psci"' to each cpu node */
|
||||
for (tmp = fdt_first_subnode(fdt, nodeoff);
|
||||
tmp >= 0;
|
||||
tmp = fdt_next_subnode(fdt, tmp)) {
|
||||
const struct fdt_property *prop;
|
||||
int len;
|
||||
|
||||
prop = fdt_get_property(fdt, tmp, "device_type", &len);
|
||||
if (!prop)
|
||||
continue;
|
||||
if (len < 4)
|
||||
continue;
|
||||
if (strcmp(prop->data, "cpu"))
|
||||
continue;
|
||||
|
||||
fdt_setprop_string(fdt, tmp, "enable-method", "psci");
|
||||
}
|
||||
|
||||
nodeoff = fdt_path_offset(fdt, "/psci");
|
||||
if (nodeoff < 0) {
|
||||
nodeoff = fdt_path_offset(fdt, "/");
|
||||
if (nodeoff < 0)
|
||||
return nodeoff;
|
||||
|
||||
nodeoff = fdt_add_subnode(fdt, nodeoff, "psci");
|
||||
if (nodeoff < 0)
|
||||
return nodeoff;
|
||||
}
|
||||
|
||||
tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci");
|
||||
if (tmp)
|
||||
return tmp;
|
||||
tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
|
||||
if (tmp)
|
||||
return tmp;
|
||||
tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", ARM_PSCI_FN_CPU_SUSPEND);
|
||||
if (tmp)
|
||||
return tmp;
|
||||
tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF);
|
||||
if (tmp)
|
||||
return tmp;
|
||||
tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON);
|
||||
if (tmp)
|
||||
return tmp;
|
||||
tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE);
|
||||
if (tmp)
|
||||
return tmp;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int armv7_update_dt(void *fdt)
|
||||
{
|
||||
#ifndef CONFIG_ARMV7_SECURE_BASE
|
||||
/* secure code lives in RAM, keep it alive */
|
||||
fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
|
||||
__secure_end - __secure_start);
|
||||
#endif
|
||||
|
||||
return fdt_psci(fdt);
|
||||
}
|
@ -13,17 +13,10 @@
|
||||
#include <asm/armv7.h>
|
||||
#include <asm/gic.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/secure.h>
|
||||
|
||||
unsigned long gic_dist_addr;
|
||||
|
||||
static unsigned int read_cpsr(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
asm volatile ("mrs %0, cpsr\n" : "=r" (reg));
|
||||
return reg;
|
||||
}
|
||||
|
||||
static unsigned int read_id_pfr1(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
@ -37,25 +30,8 @@ static unsigned long get_gicd_base_address(void)
|
||||
#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
|
||||
return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
|
||||
#else
|
||||
unsigned midr;
|
||||
unsigned periphbase;
|
||||
|
||||
/* check whether we are an Cortex-A15 or A7.
|
||||
* The actual HYP switch should work with all CPUs supporting
|
||||
* the virtualization extension, but we need the GIC address,
|
||||
* which we know only for sure for those two CPUs.
|
||||
*/
|
||||
asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
|
||||
switch (midr & MIDR_PRIMARY_PART_MASK) {
|
||||
case MIDR_CORTEX_A9_R0P1:
|
||||
case MIDR_CORTEX_A15_R0P0:
|
||||
case MIDR_CORTEX_A7_R0P0:
|
||||
break;
|
||||
default:
|
||||
printf("nonsec: could not determine GIC address.\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* get the GIC base address from the CBAR register */
|
||||
asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
|
||||
|
||||
@ -72,6 +48,18 @@ static unsigned long get_gicd_base_address(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
static void relocate_secure_section(void)
|
||||
{
|
||||
#ifdef CONFIG_ARMV7_SECURE_BASE
|
||||
size_t sz = __secure_end - __secure_start;
|
||||
|
||||
memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz);
|
||||
flush_dcache_range(CONFIG_ARMV7_SECURE_BASE,
|
||||
CONFIG_ARMV7_SECURE_BASE + sz + 1);
|
||||
invalidate_icache_all();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void kick_secondary_cpus_gic(unsigned long gicdaddr)
|
||||
{
|
||||
/* kick all CPUs (except this one) by writing to GICD_SGIR */
|
||||
@ -83,35 +71,7 @@ void __weak smp_kick_all_cpus(void)
|
||||
kick_secondary_cpus_gic(gic_dist_addr);
|
||||
}
|
||||
|
||||
int armv7_switch_hyp(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
/* check whether we are in HYP mode already */
|
||||
if ((read_cpsr() & 0x1f) == 0x1a) {
|
||||
debug("CPU already in HYP mode\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* check whether the CPU supports the virtualization extensions */
|
||||
reg = read_id_pfr1();
|
||||
if ((reg & CPUID_ARM_VIRT_MASK) != 1 << CPUID_ARM_VIRT_SHIFT) {
|
||||
printf("HYP mode: Virtualization extensions not implemented.\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* call the HYP switching code on this CPU also */
|
||||
_switch_to_hyp();
|
||||
|
||||
if ((read_cpsr() & 0x1F) != 0x1a) {
|
||||
printf("HYP mode: switch not successful.\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int armv7_switch_nonsec(void)
|
||||
int armv7_init_nonsec(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
unsigned itlinesnr, i;
|
||||
@ -147,11 +107,13 @@ int armv7_switch_nonsec(void)
|
||||
for (i = 1; i <= itlinesnr; i++)
|
||||
writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
|
||||
|
||||
smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
|
||||
#ifndef CONFIG_ARMV7_PSCI
|
||||
smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
|
||||
smp_kick_all_cpus();
|
||||
#endif
|
||||
|
||||
/* call the non-sec switching code on this CPU also */
|
||||
_nonsec_init();
|
||||
|
||||
relocate_secure_section();
|
||||
secure_ram_addr(_nonsec_init)();
|
||||
return 0;
|
||||
}
|
||||
|
@ -34,7 +34,7 @@ void zynq_ddrc_init(void)
|
||||
/* ECC is enabled when memory is in 16bit mode and it is enabled */
|
||||
if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) &&
|
||||
(width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) {
|
||||
puts("Memory: ECC enabled\n");
|
||||
puts("ECC enabled ");
|
||||
/*
|
||||
* Clear the first 1MB because it is not initialized from
|
||||
* first stage bootloader. To get ECC to work all memory has
|
||||
@ -42,6 +42,6 @@ void zynq_ddrc_init(void)
|
||||
*/
|
||||
memset((void *)0, 0, 1 * 1024 * 1024);
|
||||
} else {
|
||||
puts("Memory: ECC disabled\n");
|
||||
puts("ECC disabled ");
|
||||
}
|
||||
}
|
||||
|
@ -7,6 +7,8 @@
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
@ -23,6 +25,34 @@ SECTIONS
|
||||
*(.text*)
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) || defined(CONFIG_ARMV7_PSCI)
|
||||
|
||||
#ifndef CONFIG_ARMV7_SECURE_BASE
|
||||
#define CONFIG_ARMV7_SECURE_BASE
|
||||
#endif
|
||||
|
||||
.__secure_start : {
|
||||
. = ALIGN(0x1000);
|
||||
*(.__secure_start)
|
||||
}
|
||||
|
||||
.secure_text CONFIG_ARMV7_SECURE_BASE :
|
||||
AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
|
||||
{
|
||||
*(._secure.text)
|
||||
}
|
||||
|
||||
. = LOADADDR(.__secure_start) +
|
||||
SIZEOF(.__secure_start) +
|
||||
SIZEOF(.secure_text);
|
||||
|
||||
__secure_end_lma = .;
|
||||
.__secure_end : AT(__secure_end_lma) {
|
||||
*(.__secure_end)
|
||||
LONG(0x1d1071c); /* Must output something to reset LMA */
|
||||
}
|
||||
#endif
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
|
@ -33,11 +33,7 @@
|
||||
#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
|
||||
#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
|
||||
#define MT47H128M16RT25E_RATIO 0x80
|
||||
#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
|
||||
#define MT47H128M16RT25E_RD_DQS 0x12
|
||||
#define MT47H128M16RT25E_WR_DQS 0x00
|
||||
#define MT47H128M16RT25E_PHY_WRLVL 0x00
|
||||
#define MT47H128M16RT25E_PHY_GATELVL 0x00
|
||||
#define MT47H128M16RT25E_PHY_WR_DATA 0x40
|
||||
#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
|
||||
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
|
||||
|
@ -59,13 +59,6 @@
|
||||
/* max number of GPMC regs */
|
||||
#define GPMC_MAX_REG 7
|
||||
|
||||
#define PISMO1_NOR 1
|
||||
#define PISMO1_NAND 2
|
||||
#define PISMO2_CS0 3
|
||||
#define PISMO2_CS1 4
|
||||
#define PISMO1_ONENAND 5
|
||||
#define DBG_MPDB 6
|
||||
#define PISMO2_NAND_CS0 7
|
||||
#define PISMO2_NAND_CS1 8
|
||||
|
||||
#endif /* endif _MEM_H_ */
|
||||
|
68
arch/arm/include/asm/arch-keystone/clock-k2e.h
Normal file
68
arch/arm/include/asm/arch-keystone/clock-k2e.h
Normal file
@ -0,0 +1,68 @@
|
||||
/*
|
||||
* K2E: Clock management APIs
|
||||
*
|
||||
* (C) Copyright 2012-2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_K2E_H
|
||||
#define __ASM_ARCH_CLOCK_K2E_H
|
||||
|
||||
enum ext_clk_e {
|
||||
sys_clk,
|
||||
alt_core_clk,
|
||||
pa_clk,
|
||||
ddr3_clk,
|
||||
mcm_clk,
|
||||
pcie_clk,
|
||||
sgmii_clk,
|
||||
xgmii_clk,
|
||||
usb_clk,
|
||||
ext_clk_count /* number of external clocks */
|
||||
};
|
||||
|
||||
extern unsigned int external_clk[ext_clk_count];
|
||||
|
||||
enum clk_e {
|
||||
core_pll_clk,
|
||||
pass_pll_clk,
|
||||
ddr3_pll_clk,
|
||||
sys_clk0_clk,
|
||||
sys_clk0_1_clk,
|
||||
sys_clk0_2_clk,
|
||||
sys_clk0_3_clk,
|
||||
sys_clk0_4_clk,
|
||||
sys_clk0_6_clk,
|
||||
sys_clk0_8_clk,
|
||||
sys_clk0_12_clk,
|
||||
sys_clk0_24_clk,
|
||||
sys_clk1_clk,
|
||||
sys_clk1_3_clk,
|
||||
sys_clk1_4_clk,
|
||||
sys_clk1_6_clk,
|
||||
sys_clk1_12_clk,
|
||||
sys_clk2_clk,
|
||||
sys_clk3_clk
|
||||
};
|
||||
|
||||
#define KS2_CLK1_6 sys_clk0_6_clk
|
||||
|
||||
/* PLL identifiers */
|
||||
enum pll_type_e {
|
||||
CORE_PLL,
|
||||
PASS_PLL,
|
||||
DDR3_PLL,
|
||||
};
|
||||
|
||||
#define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
|
||||
#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
|
||||
#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2}
|
||||
#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2}
|
||||
#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
|
||||
#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
|
||||
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
|
||||
#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
|
||||
|
||||
#endif
|
@ -10,10 +10,6 @@
|
||||
#ifndef __ASM_ARCH_CLOCK_K2HK_H
|
||||
#define __ASM_ARCH_CLOCK_K2HK_H
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
enum ext_clk_e {
|
||||
sys_clk,
|
||||
alt_core_clk,
|
||||
@ -56,7 +52,7 @@ enum clk_e {
|
||||
sys_clk3_clk
|
||||
};
|
||||
|
||||
#define K2HK_CLK1_6 sys_clk0_6_clk
|
||||
#define KS2_CLK1_6 sys_clk0_6_clk
|
||||
|
||||
/* PLL identifiers */
|
||||
enum pll_type_e {
|
||||
@ -66,15 +62,6 @@ enum pll_type_e {
|
||||
DDR3A_PLL,
|
||||
DDR3B_PLL,
|
||||
};
|
||||
#define MAIN_PLL CORE_PLL
|
||||
|
||||
/* PLL configuration data */
|
||||
struct pll_init_data {
|
||||
int pll;
|
||||
int pll_m; /* PLL Multiplier */
|
||||
int pll_d; /* PLL divider */
|
||||
int pll_od; /* PLL output divider */
|
||||
};
|
||||
|
||||
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
|
||||
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
|
||||
@ -98,12 +85,4 @@ struct pll_init_data {
|
||||
#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
|
||||
#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
|
||||
|
||||
void init_plls(int num_pll, struct pll_init_data *config);
|
||||
void init_pll(const struct pll_init_data *data);
|
||||
unsigned long clk_get_rate(unsigned int clk);
|
||||
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
|
||||
int clk_set_rate(unsigned int clk, unsigned long hz);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
@ -10,8 +10,40 @@
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#ifdef CONFIG_SOC_K2HK
|
||||
#include <asm/arch/clock-k2hk.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_K2E
|
||||
#include <asm/arch/clock-k2e.h>
|
||||
#endif
|
||||
|
||||
#define MAIN_PLL CORE_PLL
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
struct keystone_pll_regs {
|
||||
u32 reg0;
|
||||
u32 reg1;
|
||||
};
|
||||
|
||||
/* PLL configuration data */
|
||||
struct pll_init_data {
|
||||
int pll;
|
||||
int pll_m; /* PLL Multiplier */
|
||||
int pll_d; /* PLL divider */
|
||||
int pll_od; /* PLL output divider */
|
||||
};
|
||||
|
||||
extern const struct keystone_pll_regs keystone_pll_regs[];
|
||||
|
||||
void init_plls(int num_pll, struct pll_init_data *config);
|
||||
void init_pll(const struct pll_init_data *data);
|
||||
unsigned long clk_get_rate(unsigned int clk);
|
||||
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
|
||||
int clk_set_rate(unsigned int clk, unsigned long hz);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
@ -50,7 +50,7 @@ struct pllctl_regs {
|
||||
};
|
||||
|
||||
static struct pllctl_regs *pllctl_regs[] = {
|
||||
(struct pllctl_regs *)(CLOCK_BASE + 0x100)
|
||||
(struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100)
|
||||
};
|
||||
|
||||
#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
|
||||
|
56
arch/arm/include/asm/arch-keystone/ddr3.h
Normal file
56
arch/arm/include/asm/arch-keystone/ddr3.h
Normal file
@ -0,0 +1,56 @@
|
||||
/*
|
||||
* DDR3
|
||||
*
|
||||
* (C) Copyright 2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _DDR3_H_
|
||||
#define _DDR3_H_
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
struct ddr3_phy_config {
|
||||
unsigned int pllcr;
|
||||
unsigned int pgcr1_mask;
|
||||
unsigned int pgcr1_val;
|
||||
unsigned int ptr0;
|
||||
unsigned int ptr1;
|
||||
unsigned int ptr2;
|
||||
unsigned int ptr3;
|
||||
unsigned int ptr4;
|
||||
unsigned int dcr_mask;
|
||||
unsigned int dcr_val;
|
||||
unsigned int dtpr0;
|
||||
unsigned int dtpr1;
|
||||
unsigned int dtpr2;
|
||||
unsigned int mr0;
|
||||
unsigned int mr1;
|
||||
unsigned int mr2;
|
||||
unsigned int dtcr;
|
||||
unsigned int pgcr2;
|
||||
unsigned int zq0cr1;
|
||||
unsigned int zq1cr1;
|
||||
unsigned int zq2cr1;
|
||||
unsigned int pir_v1;
|
||||
unsigned int pir_v2;
|
||||
};
|
||||
|
||||
struct ddr3_emif_config {
|
||||
unsigned int sdcfg;
|
||||
unsigned int sdtim1;
|
||||
unsigned int sdtim2;
|
||||
unsigned int sdtim3;
|
||||
unsigned int sdtim4;
|
||||
unsigned int zqcfg;
|
||||
unsigned int sdrfc;
|
||||
};
|
||||
|
||||
void ddr3_init(void);
|
||||
void ddr3_reset_ddrphy(void);
|
||||
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
|
||||
void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
|
||||
|
||||
#endif
|
44
arch/arm/include/asm/arch-keystone/hardware-k2e.h
Normal file
44
arch/arm/include/asm/arch-keystone/hardware-k2e.h
Normal file
@ -0,0 +1,44 @@
|
||||
/*
|
||||
* K2E: SoC definitions
|
||||
*
|
||||
* (C) Copyright 2012-2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_HARDWARE_K2E_H
|
||||
#define __ASM_ARCH_HARDWARE_K2E_H
|
||||
|
||||
/* PA SS Registers */
|
||||
#define KS2_PASS_BASE 0x24000000
|
||||
|
||||
/* Power and Sleep Controller (PSC) Domains */
|
||||
#define KS2_LPSC_MOD_RST 0
|
||||
#define KS2_LPSC_USB_1 1
|
||||
#define KS2_LPSC_USB 2
|
||||
#define KS2_LPSC_EMIF25_SPI 3
|
||||
#define KS2_LPSC_TSIP 4
|
||||
#define KS2_LPSC_DEBUGSS_TRC 5
|
||||
#define KS2_LPSC_TETB_TRC 6
|
||||
#define KS2_LPSC_PKTPROC 7
|
||||
#define KS2_LPSC_PA KS2_LPSC_PKTPROC
|
||||
#define KS2_LPSC_SGMII 8
|
||||
#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
|
||||
#define KS2_LPSC_CRYPTO 9
|
||||
#define KS2_LPSC_PCIE 10
|
||||
#define KS2_LPSC_VUSR0 12
|
||||
#define KS2_LPSC_CHIP_SRSS 13
|
||||
#define KS2_LPSC_MSMC 14
|
||||
#define KS2_LPSC_EMIF4F_DDR3 23
|
||||
#define KS2_LPSC_PCIE_1 27
|
||||
#define KS2_LPSC_XGE 50
|
||||
|
||||
/* Chip Interrupt Controller */
|
||||
#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
|
||||
#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
|
||||
|
||||
/* Number of DSP cores */
|
||||
#define KS2_NUM_DSPS 1
|
||||
|
||||
#endif
|
@ -6,136 +6,82 @@
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
|
||||
#define __ASM_ARCH_HARDWARE_K2HK_H
|
||||
|
||||
#define K2HK_PLL_CNTRL_BASE 0x02310000
|
||||
#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
|
||||
#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
|
||||
#define KS2_RSTCTRL_KEY 0x5a69
|
||||
#define KS2_RSTCTRL_MASK 0xffff0000
|
||||
#define KS2_RSTCTRL_SWRST 0xfffe0000
|
||||
#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
|
||||
|
||||
#define K2HK_PSC_BASE 0x02350000
|
||||
#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
|
||||
#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
|
||||
#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
|
||||
|
||||
#define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
|
||||
|
||||
#define ARM_PLL_EN BIT(13)
|
||||
|
||||
#define K2HK_SPI0_BASE 0x21000400
|
||||
#define K2HK_SPI1_BASE 0x21000600
|
||||
#define K2HK_SPI2_BASE 0x21000800
|
||||
#define K2HK_SPI_BASE K2HK_SPI0_BASE
|
||||
|
||||
/* Chip configuration unlock codes and registers */
|
||||
#define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
|
||||
#define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
|
||||
#define KEYSTONE_KICK0_MAGIC 0x83e70b13
|
||||
#define KEYSTONE_KICK1_MAGIC 0x95a4f1e0
|
||||
#define KS2_ARM_PLL_EN BIT(13)
|
||||
|
||||
/* PA SS Registers */
|
||||
#define KS2_PASS_BASE 0x02000000
|
||||
|
||||
/* PLL control registers */
|
||||
#define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
|
||||
#define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
|
||||
#define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
|
||||
#define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
|
||||
#define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
|
||||
#define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
|
||||
#define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
|
||||
#define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
|
||||
#define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
|
||||
#define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
|
||||
#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
|
||||
#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
|
||||
|
||||
/* Power and Sleep Controller (PSC) Domains */
|
||||
#define K2HK_LPSC_MOD 0
|
||||
#define K2HK_LPSC_DUMMY1 1
|
||||
#define K2HK_LPSC_USB 2
|
||||
#define K2HK_LPSC_EMIF25_SPI 3
|
||||
#define K2HK_LPSC_TSIP 4
|
||||
#define K2HK_LPSC_DEBUGSS_TRC 5
|
||||
#define K2HK_LPSC_TETB_TRC 6
|
||||
#define K2HK_LPSC_PKTPROC 7
|
||||
#define KS2_LPSC_PA K2HK_LPSC_PKTPROC
|
||||
#define K2HK_LPSC_SGMII 8
|
||||
#define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII
|
||||
#define K2HK_LPSC_CRYPTO 9
|
||||
#define K2HK_LPSC_PCIE 10
|
||||
#define K2HK_LPSC_SRIO 11
|
||||
#define K2HK_LPSC_VUSR0 12
|
||||
#define K2HK_LPSC_CHIP_SRSS 13
|
||||
#define K2HK_LPSC_MSMC 14
|
||||
#define K2HK_LPSC_GEM_0 15
|
||||
#define K2HK_LPSC_GEM_1 16
|
||||
#define K2HK_LPSC_GEM_2 17
|
||||
#define K2HK_LPSC_GEM_3 18
|
||||
#define K2HK_LPSC_GEM_4 19
|
||||
#define K2HK_LPSC_GEM_5 20
|
||||
#define K2HK_LPSC_GEM_6 21
|
||||
#define K2HK_LPSC_GEM_7 22
|
||||
#define K2HK_LPSC_EMIF4F_DDR3A 23
|
||||
#define K2HK_LPSC_EMIF4F_DDR3B 24
|
||||
#define K2HK_LPSC_TAC 25
|
||||
#define K2HK_LPSC_RAC 26
|
||||
#define K2HK_LPSC_RAC_1 27
|
||||
#define K2HK_LPSC_FFTC_A 28
|
||||
#define K2HK_LPSC_FFTC_B 29
|
||||
#define K2HK_LPSC_FFTC_C 30
|
||||
#define K2HK_LPSC_FFTC_D 31
|
||||
#define K2HK_LPSC_FFTC_E 32
|
||||
#define K2HK_LPSC_FFTC_F 33
|
||||
#define K2HK_LPSC_AI2 34
|
||||
#define K2HK_LPSC_TCP3D_0 35
|
||||
#define K2HK_LPSC_TCP3D_1 36
|
||||
#define K2HK_LPSC_TCP3D_2 37
|
||||
#define K2HK_LPSC_TCP3D_3 38
|
||||
#define K2HK_LPSC_VCP2X4_A 39
|
||||
#define K2HK_LPSC_CP2X4_B 40
|
||||
#define K2HK_LPSC_VCP2X4_C 41
|
||||
#define K2HK_LPSC_VCP2X4_D 42
|
||||
#define K2HK_LPSC_VCP2X4_E 43
|
||||
#define K2HK_LPSC_VCP2X4_F 44
|
||||
#define K2HK_LPSC_VCP2X4_G 45
|
||||
#define K2HK_LPSC_VCP2X4_H 46
|
||||
#define K2HK_LPSC_BCP 47
|
||||
#define K2HK_LPSC_DXB 48
|
||||
#define K2HK_LPSC_VUSR1 49
|
||||
#define K2HK_LPSC_XGE 50
|
||||
#define K2HK_LPSC_ARM_SREFLEX 51
|
||||
#define K2HK_LPSC_TETRIS 52
|
||||
#define KS2_LPSC_MOD 0
|
||||
#define KS2_LPSC_DUMMY1 1
|
||||
#define KS2_LPSC_USB 2
|
||||
#define KS2_LPSC_EMIF25_SPI 3
|
||||
#define KS2_LPSC_TSIP 4
|
||||
#define KS2_LPSC_DEBUGSS_TRC 5
|
||||
#define KS2_LPSC_TETB_TRC 6
|
||||
#define KS2_LPSC_PKTPROC 7
|
||||
#define KS2_LPSC_PA KS2_LPSC_PKTPROC
|
||||
#define KS2_LPSC_SGMII 8
|
||||
#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
|
||||
#define KS2_LPSC_CRYPTO 9
|
||||
#define KS2_LPSC_PCIE 10
|
||||
#define KS2_LPSC_SRIO 11
|
||||
#define KS2_LPSC_VUSR0 12
|
||||
#define KS2_LPSC_CHIP_SRSS 13
|
||||
#define KS2_LPSC_MSMC 14
|
||||
#define KS2_LPSC_GEM_1 16
|
||||
#define KS2_LPSC_GEM_2 17
|
||||
#define KS2_LPSC_GEM_3 18
|
||||
#define KS2_LPSC_GEM_4 19
|
||||
#define KS2_LPSC_GEM_5 20
|
||||
#define KS2_LPSC_GEM_6 21
|
||||
#define KS2_LPSC_GEM_7 22
|
||||
#define KS2_LPSC_EMIF4F_DDR3A 23
|
||||
#define KS2_LPSC_EMIF4F_DDR3B 24
|
||||
#define KS2_LPSC_TAC 25
|
||||
#define KS2_LPSC_RAC 26
|
||||
#define KS2_LPSC_RAC_1 27
|
||||
#define KS2_LPSC_FFTC_A 28
|
||||
#define KS2_LPSC_FFTC_B 29
|
||||
#define KS2_LPSC_FFTC_C 30
|
||||
#define KS2_LPSC_FFTC_D 31
|
||||
#define KS2_LPSC_FFTC_E 32
|
||||
#define KS2_LPSC_FFTC_F 33
|
||||
#define KS2_LPSC_AI2 34
|
||||
#define KS2_LPSC_TCP3D_0 35
|
||||
#define KS2_LPSC_TCP3D_1 36
|
||||
#define KS2_LPSC_TCP3D_2 37
|
||||
#define KS2_LPSC_TCP3D_3 38
|
||||
#define KS2_LPSC_VCP2X4_A 39
|
||||
#define KS2_LPSC_CP2X4_B 40
|
||||
#define KS2_LPSC_VCP2X4_C 41
|
||||
#define KS2_LPSC_VCP2X4_D 42
|
||||
#define KS2_LPSC_VCP2X4_E 43
|
||||
#define KS2_LPSC_VCP2X4_F 44
|
||||
#define KS2_LPSC_VCP2X4_G 45
|
||||
#define KS2_LPSC_VCP2X4_H 46
|
||||
#define KS2_LPSC_BCP 47
|
||||
#define KS2_LPSC_DXB 48
|
||||
#define KS2_LPSC_VUSR1 49
|
||||
#define KS2_LPSC_XGE 50
|
||||
#define KS2_LPSC_ARM_SREFLEX 51
|
||||
|
||||
/* DDR3A definitions */
|
||||
#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
|
||||
#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000
|
||||
#define K2HK_DDR3A_DDRPHYC 0x02329000
|
||||
/* DDR3B definitions */
|
||||
#define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000
|
||||
#define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000
|
||||
#define K2HK_DDR3B_DDRPHYC 0x02328000
|
||||
#define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000
|
||||
#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
|
||||
#define KS2_DDR3B_DDRPHYC 0x02328000
|
||||
|
||||
/* Queue manager */
|
||||
#define DEVICE_QM_MANAGER_BASE 0x02a02000
|
||||
#define DEVICE_QM_DESC_SETUP_BASE 0x02a03000
|
||||
#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000
|
||||
#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
|
||||
#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000
|
||||
#define DEVICE_QM_NUM_LINKRAMS 2
|
||||
#define DEVICE_QM_NUM_MEMREGIONS 20
|
||||
|
||||
#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
|
||||
#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
|
||||
#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
|
||||
#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
|
||||
|
||||
#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
|
||||
#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
|
||||
#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
|
||||
|
||||
/* MSMC control */
|
||||
#define K2HK_MSMC_CTRL_BASE 0x0bc00000
|
||||
/* Number of DSP cores */
|
||||
#define KS2_NUM_DSPS 8
|
||||
|
||||
#endif /* __ASM_ARCH_HARDWARE_H */
|
||||
|
@ -22,42 +22,6 @@
|
||||
typedef volatile unsigned int dv_reg;
|
||||
typedef volatile unsigned int *dv_reg_p;
|
||||
|
||||
struct ddr3_phy_config {
|
||||
unsigned int pllcr;
|
||||
unsigned int pgcr1_mask;
|
||||
unsigned int pgcr1_val;
|
||||
unsigned int ptr0;
|
||||
unsigned int ptr1;
|
||||
unsigned int ptr2;
|
||||
unsigned int ptr3;
|
||||
unsigned int ptr4;
|
||||
unsigned int dcr_mask;
|
||||
unsigned int dcr_val;
|
||||
unsigned int dtpr0;
|
||||
unsigned int dtpr1;
|
||||
unsigned int dtpr2;
|
||||
unsigned int mr0;
|
||||
unsigned int mr1;
|
||||
unsigned int mr2;
|
||||
unsigned int dtcr;
|
||||
unsigned int pgcr2;
|
||||
unsigned int zq0cr1;
|
||||
unsigned int zq1cr1;
|
||||
unsigned int zq2cr1;
|
||||
unsigned int pir_v1;
|
||||
unsigned int pir_v2;
|
||||
};
|
||||
|
||||
struct ddr3_emif_config {
|
||||
unsigned int sdcfg;
|
||||
unsigned int sdtim1;
|
||||
unsigned int sdtim2;
|
||||
unsigned int sdtim3;
|
||||
unsigned int sdtim4;
|
||||
unsigned int zqcfg;
|
||||
unsigned int sdrfc;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#define BIT(x) (1 << (x))
|
||||
@ -105,6 +69,11 @@ struct ddr3_emif_config {
|
||||
#define NOSRA_MASK 0x08000000
|
||||
#define ECC_MASK 0x00000001
|
||||
|
||||
/* DDR3 definitions */
|
||||
#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
|
||||
#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
|
||||
#define KS2_DDR3A_DDRPHYC 0x02329000
|
||||
|
||||
#define KS2_DDR3_MIDR_OFFSET 0x00
|
||||
#define KS2_DDR3_STATUS_OFFSET 0x04
|
||||
#define KS2_DDR3_SDCFG_OFFSET 0x08
|
||||
@ -116,39 +85,103 @@ struct ddr3_emif_config {
|
||||
#define KS2_DDR3_PMCTL_OFFSET 0x38
|
||||
#define KS2_DDR3_ZQCFG_OFFSET 0xC8
|
||||
|
||||
#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
|
||||
|
||||
#define KS2_UART0_BASE 0x02530c00
|
||||
#define KS2_UART1_BASE 0x02531000
|
||||
|
||||
/* Boot Config */
|
||||
#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
|
||||
#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
|
||||
#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
|
||||
|
||||
/* PSC */
|
||||
#define KS2_PSC_BASE 0x02350000
|
||||
#define KS2_LPSC_GEM_0 15
|
||||
#define KS2_LPSC_TETRIS 52
|
||||
#define KS2_TETRIS_PWR_DOMAIN 31
|
||||
|
||||
/* Chip configuration unlock codes and registers */
|
||||
#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
|
||||
#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
|
||||
#define KS2_KICK0_MAGIC 0x83e70b13
|
||||
#define KS2_KICK1_MAGIC 0x95a4f1e0
|
||||
|
||||
/* PLL control registers */
|
||||
#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
|
||||
#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
|
||||
#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
|
||||
#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
|
||||
#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
|
||||
#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
|
||||
#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
|
||||
#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
|
||||
|
||||
#define KS2_PLL_CNTRL_BASE 0x02310000
|
||||
#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
|
||||
#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4)
|
||||
#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
|
||||
#define KS2_RSTCTRL_KEY 0x5a69
|
||||
#define KS2_RSTCTRL_MASK 0xffff0000
|
||||
#define KS2_RSTCTRL_SWRST 0xfffe0000
|
||||
|
||||
/* SPI */
|
||||
#define KS2_SPI0_BASE 0x21000400
|
||||
#define KS2_SPI1_BASE 0x21000600
|
||||
#define KS2_SPI2_BASE 0x21000800
|
||||
#define KS2_SPI_BASE KS2_SPI0_BASE
|
||||
|
||||
/* AEMIF */
|
||||
#define KS2_AEMIF_CNTRL_BASE 0x21000a00
|
||||
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
|
||||
|
||||
/* Flag from ks2_debug options to check if DSPs need to stay ON */
|
||||
#define DBG_LEAVE_DSPS_ON 0x1
|
||||
|
||||
/* Queue manager */
|
||||
#define KS2_QM_MANAGER_BASE 0x02a02000
|
||||
#define KS2_QM_DESC_SETUP_BASE 0x02a03000
|
||||
#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000
|
||||
#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
|
||||
#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
|
||||
|
||||
/* MSMC control */
|
||||
#define KS2_MSMC_CTRL_BASE 0x0bc00000
|
||||
|
||||
#ifdef CONFIG_SOC_K2HK
|
||||
#include <asm/arch/hardware-k2hk.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_K2E
|
||||
#include <asm/arch/hardware-k2e.h>
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
static inline int cpu_is_k2hk(void)
|
||||
{
|
||||
unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
|
||||
unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
|
||||
unsigned int part_no = (jtag_id >> 12) & 0xffff;
|
||||
|
||||
return (part_no == 0xb981) ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline int cpu_is_k2e(void)
|
||||
{
|
||||
unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
|
||||
unsigned int part_no = (jtag_id >> 12) & 0xffff;
|
||||
|
||||
return (part_no == 0xb9a6) ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline int cpu_revision(void)
|
||||
{
|
||||
unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
|
||||
unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
|
||||
unsigned int rev = (jtag_id >> 28) & 0xf;
|
||||
|
||||
return rev;
|
||||
}
|
||||
|
||||
void share_all_segments(int priv_id);
|
||||
int cpu_to_bus(u32 *ptr, u32 length);
|
||||
void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
|
||||
void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
|
||||
void init_ddr3(void);
|
||||
void sdelay(unsigned long);
|
||||
|
||||
#endif
|
||||
|
15
arch/arm/include/asm/arch-keystone/mon.h
Normal file
15
arch/arm/include/asm/arch-keystone/mon.h
Normal file
@ -0,0 +1,15 @@
|
||||
/*
|
||||
* K2HK: secure kernel command header file
|
||||
*
|
||||
* (C) Copyright 2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _MON_H_
|
||||
#define _MON_H_
|
||||
|
||||
int mon_power_off(int core_id);
|
||||
|
||||
#endif
|
17
arch/arm/include/asm/arch-keystone/msmc.h
Normal file
17
arch/arm/include/asm/arch-keystone/msmc.h
Normal file
@ -0,0 +1,17 @@
|
||||
/*
|
||||
* MSMC controller
|
||||
*
|
||||
* (C) Copyright 2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _MSMC_H_
|
||||
#define _MSMC_H_
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
void msmc_share_all_segments(int priv_id);
|
||||
|
||||
#endif
|
@ -129,7 +129,8 @@
|
||||
*/
|
||||
#ifdef CONFIG_CMD_I2C
|
||||
#ifndef CONFIG_SYS_I2C_SOFT
|
||||
#define CONFIG_I2C_MVTWSI
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MVTWSI
|
||||
#endif
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x0
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
@ -98,7 +98,6 @@ struct ctrl_id {
|
||||
#define DEBUG_BASE 0x08000000 /* debug board */
|
||||
#define NAND_BASE 0x30000000 /* NAND addr */
|
||||
/* (actual size small port) */
|
||||
#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
|
||||
#define ONENAND_MAP 0x20000000 /* OneNand addr */
|
||||
/* (actual size small port) */
|
||||
/* SMS */
|
||||
|
@ -427,20 +427,7 @@ enum {
|
||||
/* max number of GPMC regs */
|
||||
#define GPMC_MAX_REG 7
|
||||
|
||||
#define PISMO1_NOR 1
|
||||
#define PISMO1_NAND 2
|
||||
#define PISMO2_CS0 3
|
||||
#define PISMO2_CS1 4
|
||||
#define PISMO1_ONENAND 5
|
||||
#define DBG_MPDB 6
|
||||
#define PISMO2_NAND_CS0 7
|
||||
#define PISMO2_NAND_CS1 8
|
||||
|
||||
/* make it readable for the gpmc_init */
|
||||
#define PISMO1_NOR_BASE FLASH_BASE
|
||||
#define PISMO1_NAND_BASE NAND_BASE
|
||||
#define PISMO2_CS0_BASE PISMO2_MAP1
|
||||
#define PISMO1_ONEN_BASE ONENAND_MAP
|
||||
#define DBG_MPDB_BASE DEBUG_BASE
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
@ -13,6 +13,9 @@ void r8a7790_pinmux_init(void);
|
||||
#elif defined(CONFIG_R8A7791)
|
||||
#include "r8a7791-gpio.h"
|
||||
void r8a7791_pinmux_init(void);
|
||||
#elif defined(CONFIG_R8A7794)
|
||||
#include "r8a7794-gpio.h"
|
||||
void r8a7794_pinmux_init(void);
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_GPIO_H */
|
||||
|
176
arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h
Normal file
176
arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h
Normal file
@ -0,0 +1,176 @@
|
||||
#ifndef __ASM_R8A7794_H__
|
||||
#define __ASM_R8A7794_H__
|
||||
|
||||
/* Pin Function Controller:
|
||||
* GPIO_FN_xx - GPIO used to select pin function
|
||||
* GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
|
||||
*/
|
||||
enum {
|
||||
GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
|
||||
GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
|
||||
GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
|
||||
GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
|
||||
GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
|
||||
GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
|
||||
GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
|
||||
GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
|
||||
|
||||
GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
|
||||
GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
|
||||
GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
|
||||
GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
|
||||
GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
|
||||
GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
|
||||
GPIO_GP_1_24, GPIO_GP_1_25,
|
||||
|
||||
GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
|
||||
GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
|
||||
GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
|
||||
GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
|
||||
GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
|
||||
GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
|
||||
GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
|
||||
GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
|
||||
|
||||
GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
|
||||
GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
|
||||
GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
|
||||
GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
|
||||
GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
|
||||
GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
|
||||
GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
|
||||
GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
|
||||
|
||||
GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
|
||||
GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
|
||||
GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
|
||||
GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
|
||||
GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
|
||||
GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
|
||||
GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
|
||||
GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
|
||||
|
||||
GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
|
||||
GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
|
||||
GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
|
||||
GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
|
||||
GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
|
||||
GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
|
||||
GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
|
||||
|
||||
GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
|
||||
GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
|
||||
GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
|
||||
GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
|
||||
GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
|
||||
GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
|
||||
GPIO_GP_6_24, GPIO_GP_6_25,
|
||||
|
||||
GPIO_FN_A2, GPIO_FN_WE0_N, GPIO_FN_WE1_N, GPIO_FN_DACK0,
|
||||
GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN,
|
||||
GPIO_FN_USB1_OVC, GPIO_FN_SD0_CLK, GPIO_FN_SD0_CMD,
|
||||
GPIO_FN_SD0_DATA0, GPIO_FN_SD0_DATA1, GPIO_FN_SD0_DATA2,
|
||||
GPIO_FN_SD0_DATA3, GPIO_FN_SD0_CD, GPIO_FN_SD0_WP,
|
||||
GPIO_FN_SD1_CLK, GPIO_FN_SD1_CMD, GPIO_FN_SD1_DATA0,
|
||||
GPIO_FN_SD1_DATA1, GPIO_FN_SD1_DATA2, GPIO_FN_SD1_DATA3,
|
||||
|
||||
/*
|
||||
* From IPSR0 to IPSR5 have been removed because they does not use.
|
||||
*/
|
||||
|
||||
/* IPSR6 */
|
||||
GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE, GPIO_FN_CC50_STATE28,
|
||||
GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
|
||||
GPIO_FN_CC50_STATE29, GPIO_FN_DU0_DISP, GPIO_FN_QPOLA,
|
||||
GPIO_FN_CC50_STATE30, GPIO_FN_DU0_CDE, GPIO_FN_QPOLB,
|
||||
GPIO_FN_CC50_STATE31, GPIO_FN_VI0_CLK, GPIO_FN_AVB_RX_CLK,
|
||||
GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_AVB_RX_DV, GPIO_FN_VI0_DATA1_VI0_B1,
|
||||
GPIO_FN_AVB_RXD0, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_AVB_RXD1,
|
||||
GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_AVB_RXD2, GPIO_FN_VI0_DATA4_VI0_B4,
|
||||
GPIO_FN_AVB_RXD3, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_AVB_RXD4,
|
||||
GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA7_VI0_B7,
|
||||
GPIO_FN_AVB_RXD6, GPIO_FN_VI0_CLKENB, GPIO_FN_I2C3_SCL,
|
||||
GPIO_FN_SCIFA5_RXD_C, GPIO_FN_IETX_C, GPIO_FN_AVB_RXD7,
|
||||
GPIO_FN_VI0_FIELD, GPIO_FN_I2C3_SDA, GPIO_FN_SCIFA5_TXD_C,
|
||||
GPIO_FN_IECLK_C, GPIO_FN_AVB_RX_ER, GPIO_FN_VI0_HSYNC_N,
|
||||
GPIO_FN_SCIF0_RXD_B, GPIO_FN_I2C0_SCL_C, GPIO_FN_IERX_C,
|
||||
GPIO_FN_AVB_COL, GPIO_FN_VI0_VSYNC_N, GPIO_FN_SCIF0_TXD_B,
|
||||
GPIO_FN_I2C0_SDA_C, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_AVB_TX_EN,
|
||||
GPIO_FN_ETH_MDIO, GPIO_FN_VI0_G0, GPIO_FN_MSIOF2_RXD_B,
|
||||
GPIO_FN_IIC0_SCL_D, GPIO_FN_AVB_TX_CLK, GPIO_FN_ADIDATA, GPIO_FN_AD_DI,
|
||||
|
||||
/* IPSR7 */
|
||||
GPIO_FN_ETH_CRS_DV, GPIO_FN_VI0_G1, GPIO_FN_MSIOF2_TXD_B,
|
||||
GPIO_FN_IIC0_SDA_D, GPIO_FN_AVB_TXD0, GPIO_FN_ADICS_SAMP, GPIO_FN_AD_DO,
|
||||
GPIO_FN_ETH_RX_ER, GPIO_FN_VI0_G2, GPIO_FN_MSIOF2_SCK_B,
|
||||
GPIO_FN_CAN0_RX_B, GPIO_FN_AVB_TXD1, GPIO_FN_ADICLK, GPIO_FN_AD_CLK,
|
||||
GPIO_FN_ETH_RXD0, GPIO_FN_VI0_G3, GPIO_FN_MSIOF2_SYNC_B,
|
||||
GPIO_FN_CAN0_TX_B, GPIO_FN_AVB_TXD2, GPIO_FN_ADICHS0, GPIO_FN_AD_NCS_N,
|
||||
GPIO_FN_ETH_RXD1, GPIO_FN_VI0_G4, GPIO_FN_MSIOF2_SS1_B,
|
||||
GPIO_FN_SCIF4_RXD_D, GPIO_FN_AVB_TXD3, GPIO_FN_ADICHS1,
|
||||
GPIO_FN_ETH_LINK, GPIO_FN_VI0_G5, GPIO_FN_MSIOF2_SS2_B,
|
||||
GPIO_FN_SCIF4_TXD_D, GPIO_FN_AVB_TXD4, GPIO_FN_ADICHS2,
|
||||
GPIO_FN_ETH_REFCLK, GPIO_FN_VI0_G6, GPIO_FN_SCIF2_SCK_C,
|
||||
GPIO_FN_AVB_TXD5, GPIO_FN_SSI_SCK5_B, GPIO_FN_ETH_TXD1, GPIO_FN_VI0_G7,
|
||||
GPIO_FN_SCIF2_RXD_C, GPIO_FN_IIC1_SCL_D, GPIO_FN_AVB_TXD6,
|
||||
GPIO_FN_SSI_WS5_B, GPIO_FN_ETH_TX_EN, GPIO_FN_VI0_R0,
|
||||
GPIO_FN_SCIF2_TXD_C, GPIO_FN_IIC1_SDA_D, GPIO_FN_AVB_TXD7,
|
||||
GPIO_FN_SSI_SDATA5_B, GPIO_FN_ETH_MAGIC, GPIO_FN_VI0_R1,
|
||||
GPIO_FN_SCIF3_SCK_B, GPIO_FN_AVB_TX_ER, GPIO_FN_SSI_SCK6_B,
|
||||
GPIO_FN_ETH_TXD0, GPIO_FN_VI0_R2, GPIO_FN_SCIF3_RXD_B,
|
||||
GPIO_FN_I2C4_SCL_E, GPIO_FN_AVB_GTX_CLK, GPIO_FN_SSI_WS6_B,
|
||||
GPIO_FN_DREQ0_N, GPIO_FN_SCIFB1_RXD,
|
||||
|
||||
/* IPSR8 */
|
||||
GPIO_FN_ETH_MDC, GPIO_FN_VI0_R3, GPIO_FN_SCIF3_TXD_B,
|
||||
GPIO_FN_I2C4_SDA_E, GPIO_FN_AVB_MDC, GPIO_FN_SSI_SDATA6_B,
|
||||
GPIO_FN_HSCIF0_HRX, GPIO_FN_VI0_R4, GPIO_FN_I2C1_SCL_C,
|
||||
GPIO_FN_AUDIO_CLKA_B, GPIO_FN_AVB_MDIO, GPIO_FN_SSI_SCK78_B,
|
||||
GPIO_FN_HSCIF0_HTX, GPIO_FN_VI0_R5, GPIO_FN_I2C1_SDA_C,
|
||||
GPIO_FN_AUDIO_CLKB_B, GPIO_FN_AVB_LINK, GPIO_FN_SSI_WS78_B,
|
||||
GPIO_FN_HSCIF0_HCTS_N, GPIO_FN_VI0_R6, GPIO_FN_SCIF0_RXD_D,
|
||||
GPIO_FN_I2C0_SCL_E, GPIO_FN_AVB_MAGIC, GPIO_FN_SSI_SDATA7_B,
|
||||
GPIO_FN_HSCIF0_HRTS_N, GPIO_FN_VI0_R7, GPIO_FN_SCIF0_TXD_D,
|
||||
GPIO_FN_I2C0_SDA_E, GPIO_FN_AVB_PHY_INT, GPIO_FN_SSI_SDATA8_B,
|
||||
GPIO_FN_HSCIF0_HSCK, GPIO_FN_SCIF_CLK_B, GPIO_FN_AVB_CRS,
|
||||
GPIO_FN_AUDIO_CLKC_B, GPIO_FN_I2C0_SCL, GPIO_FN_SCIF0_RXD_C,
|
||||
GPIO_FN_PWM5, GPIO_FN_TCLK1_B, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN1_RX_D,
|
||||
GPIO_FN_TPUTO0_B, GPIO_FN_I2C0_SDA, GPIO_FN_SCIF0_TXD_C, GPIO_FN_TPUTO0,
|
||||
GPIO_FN_CAN_CLK, GPIO_FN_DVC_MUTE, GPIO_FN_CAN1_TX_D, GPIO_FN_I2C1_SCL,
|
||||
GPIO_FN_SCIF4_RXD, GPIO_FN_PWM5_B, GPIO_FN_DU1_DR0, GPIO_FN_RIF1_SYNC_B,
|
||||
GPIO_FN_TS_SDATA_D, GPIO_FN_TPUTO1_B, GPIO_FN_I2C1_SDA,
|
||||
GPIO_FN_SCIF4_TXD, GPIO_FN_IRQ5, GPIO_FN_DU1_DR1, GPIO_FN_RIF1_CLK_B,
|
||||
GPIO_FN_TS_SCK_D, GPIO_FN_BPFCLK_C, GPIO_FN_MSIOF0_RXD,
|
||||
GPIO_FN_SCIF5_RXD, GPIO_FN_I2C2_SCL_C, GPIO_FN_DU1_DR2,
|
||||
GPIO_FN_RIF1_D0_B, GPIO_FN_TS_SDEN_D, GPIO_FN_FMCLK_C, GPIO_FN_RDS_CLK,
|
||||
|
||||
/*
|
||||
* From IPSR9 to IPSR10 have been removed because they does not use.
|
||||
*/
|
||||
|
||||
/* IPSR11 */
|
||||
GPIO_FN_SSI_WS5, GPIO_FN_SCIFA3_RXD, GPIO_FN_I2C3_SCL_C,
|
||||
GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5,
|
||||
GPIO_FN_SCIFA3_TXD, GPIO_FN_I2C3_SDA_C, GPIO_FN_DU1_DOTCLKOUT1,
|
||||
GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SCK6, GPIO_FN_SCIFA1_SCK_B,
|
||||
GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_SSI_WS6,
|
||||
GPIO_FN_SCIFA1_RXD_B, GPIO_FN_I2C4_SCL_C, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC,
|
||||
GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_SDATA6, GPIO_FN_SCIFA1_TXD_B,
|
||||
GPIO_FN_I2C4_SDA_C, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
|
||||
GPIO_FN_CAN_DEBUGOUT15, GPIO_FN_SSI_SCK78, GPIO_FN_SCIFA2_SCK_B,
|
||||
GPIO_FN_IIC0_SDA_C, GPIO_FN_DU1_DISP, GPIO_FN_SSI_WS78,
|
||||
GPIO_FN_SCIFA2_RXD_B, GPIO_FN_IIC0_SCL_C, GPIO_FN_DU1_CDE,
|
||||
GPIO_FN_SSI_SDATA7, GPIO_FN_SCIFA2_TXD_B, GPIO_FN_IRQ8,
|
||||
GPIO_FN_AUDIO_CLKA_D, GPIO_FN_CAN_CLK_D, GPIO_FN_PCMOE_N,
|
||||
GPIO_FN_SSI_SCK0129, GPIO_FN_MSIOF1_RXD_B, GPIO_FN_SCIF5_RXD_D,
|
||||
GPIO_FN_ADIDATA_B, GPIO_FN_AD_DI_B, GPIO_FN_PCMWE_N, GPIO_FN_SSI_WS0129,
|
||||
GPIO_FN_MSIOF1_TXD_B, GPIO_FN_SCIF5_TXD_D, GPIO_FN_ADICS_SAMP_B,
|
||||
GPIO_FN_AD_DO_B, GPIO_FN_SSI_SDATA0, GPIO_FN_MSIOF1_SCK_B,
|
||||
GPIO_FN_PWM0_B, GPIO_FN_ADICLK_B, GPIO_FN_AD_CLK_B,
|
||||
|
||||
/*
|
||||
* From IPSR12 to IPSR13 have been removed because they does not use.
|
||||
*/
|
||||
};
|
||||
|
||||
#endif /* __ASM_R8A7794_H__ */
|
14
arch/arm/include/asm/arch-rmobile/r8a7794.h
Normal file
14
arch/arm/include/asm/arch-rmobile/r8a7794.h
Normal file
@ -0,0 +1,14 @@
|
||||
/*
|
||||
* arch/arm/include/asm/arch-rmobile/r8a7794.h
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_R8A7794_H
|
||||
#define __ASM_ARCH_R8A7794_H
|
||||
|
||||
#include "rcar-base.h"
|
||||
|
||||
#endif /* __ASM_ARCH_R8A7794_H */
|
@ -10,7 +10,7 @@
|
||||
#define __ASM_ARCH_RCAR_BASE_H
|
||||
|
||||
/*
|
||||
* R-Car (R8A7790/R8A7791) I/O Addresses
|
||||
* R-Car (R8A7790/R8A7791/R8A7794) I/O Addresses
|
||||
*/
|
||||
#define RWDT_BASE 0xE6020000
|
||||
#define SWDT_BASE 0xE6030000
|
||||
@ -116,7 +116,7 @@
|
||||
#define SYS_AXI_SAT1_BASE 0xFF8009C0
|
||||
#define SYS_AXI_SDM0_BASE 0xFF800A00
|
||||
#define SYS_AXI_SDM1_BASE 0xFF800A40
|
||||
#define SYS_AXI_TRAB_BASE 0xFF800B00
|
||||
#define SYS_AXI_TRAB_BASE 0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
|
||||
#define SYS_AXI_UDM0_BASE 0xFF800B80
|
||||
#define SYS_AXI_UDM1_BASE 0xFF800BC0
|
||||
|
||||
|
@ -10,6 +10,8 @@
|
||||
#include <asm/arch/r8a7790.h>
|
||||
#elif defined(CONFIG_R8A7791)
|
||||
#include <asm/arch/r8a7791.h>
|
||||
#elif defined(CONFIG_R8A7794)
|
||||
#include <asm/arch/r8a7794.h>
|
||||
#else
|
||||
#error "SOC Name not defined"
|
||||
#endif
|
||||
|
@ -143,5 +143,7 @@ int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
|
||||
int sunxi_gpio_get_cfgpin(u32 pin);
|
||||
int sunxi_gpio_set_drv(u32 pin, u32 val);
|
||||
int sunxi_gpio_set_pull(u32 pin, u32 val);
|
||||
int sunxi_name_to_gpio(const char *name);
|
||||
#define name_to_gpio(name) sunxi_name_to_gpio(name)
|
||||
|
||||
#endif /* _SUNXI_GPIO_H */
|
||||
|
15
arch/arm/include/asm/arch-sunxi/i2c.h
Normal file
15
arch/arm/include/asm/arch-sunxi/i2c.h
Normal file
@ -0,0 +1,15 @@
|
||||
/*
|
||||
* Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _SUNXI_I2C_H_
|
||||
#define _SUNXI_I2C_H_
|
||||
|
||||
#include <asm/arch/cpu.h>
|
||||
|
||||
#define CONFIG_I2C_MVTWSI_BASE SUNXI_TWI0_BASE
|
||||
/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
|
||||
#define CONFIG_SYS_TCLK 24000000
|
||||
|
||||
#endif
|
@ -11,6 +11,11 @@
|
||||
#ifndef _SUNXI_TIMER_H_
|
||||
#define _SUNXI_TIMER_H_
|
||||
|
||||
#define WDT_CTRL_RESTART (0x1 << 0)
|
||||
#define WDT_CTRL_KEY (0x0a57 << 1)
|
||||
#define WDT_MODE_EN (0x1 << 0)
|
||||
#define WDT_MODE_RESET_EN (0x1 << 1)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
@ -78,13 +78,18 @@ void v7_outer_cache_inval_range(u32 start, u32 end);
|
||||
|
||||
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
|
||||
|
||||
int armv7_switch_nonsec(void);
|
||||
int armv7_switch_hyp(void);
|
||||
int armv7_init_nonsec(void);
|
||||
int armv7_update_dt(void *fdt);
|
||||
|
||||
/* defined in assembly file */
|
||||
unsigned int _nonsec_init(void);
|
||||
void _do_nonsec_entry(void *target_pc, unsigned long r0,
|
||||
unsigned long r1, unsigned long r2);
|
||||
void _smp_pen(void);
|
||||
void _switch_to_hyp(void);
|
||||
|
||||
extern char __secure_start[];
|
||||
extern char __secure_end[];
|
||||
|
||||
#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
|
||||
|
||||
#endif /* ! __ASSEMBLY__ */
|
||||
|
@ -595,6 +595,14 @@ static inline u32 omap_revision(void)
|
||||
return *omap_si_rev;
|
||||
}
|
||||
|
||||
#define OMAP44xx 0x44000000
|
||||
|
||||
static inline u8 is_omap44xx(void)
|
||||
{
|
||||
extern u32 *const omap_si_rev;
|
||||
return (*omap_si_rev & 0xFF000000) == OMAP44xx;
|
||||
};
|
||||
|
||||
#define OMAP54xx 0x54000000
|
||||
|
||||
static inline u8 is_omap54xx(void)
|
||||
|
@ -38,12 +38,14 @@ struct pt_regs {
|
||||
#define IRQ_MODE 0x12
|
||||
#define SVC_MODE 0x13
|
||||
#define ABT_MODE 0x17
|
||||
#define HYP_MODE 0x1a
|
||||
#define UND_MODE 0x1b
|
||||
#define SYSTEM_MODE 0x1f
|
||||
#define MODE_MASK 0x1f
|
||||
#define T_BIT 0x20
|
||||
#define F_BIT 0x40
|
||||
#define I_BIT 0x80
|
||||
#define A_BIT 0x100
|
||||
#define CC_V_BIT (1 << 28)
|
||||
#define CC_C_BIT (1 << 29)
|
||||
#define CC_Z_BIT (1 << 30)
|
||||
|
35
arch/arm/include/asm/psci.h
Normal file
35
arch/arm/include/asm/psci.h
Normal file
@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (C) 2013 - ARM Ltd
|
||||
* Author: Marc Zyngier <marc.zyngier@arm.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __ARM_PSCI_H__
|
||||
#define __ARM_PSCI_H__
|
||||
|
||||
/* PSCI interface */
|
||||
#define ARM_PSCI_FN_BASE 0x95c1ba5e
|
||||
#define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n))
|
||||
|
||||
#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0)
|
||||
#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1)
|
||||
#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2)
|
||||
#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3)
|
||||
|
||||
#define ARM_PSCI_RET_SUCCESS 0
|
||||
#define ARM_PSCI_RET_NI (-1)
|
||||
#define ARM_PSCI_RET_INVAL (-2)
|
||||
#define ARM_PSCI_RET_DENIED (-3)
|
||||
|
||||
#endif /* __ARM_PSCI_H__ */
|
26
arch/arm/include/asm/secure.h
Normal file
26
arch/arm/include/asm/secure.h
Normal file
@ -0,0 +1,26 @@
|
||||
#ifndef __ASM_SECURE_H
|
||||
#define __ASM_SECURE_H
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#ifdef CONFIG_ARMV7_SECURE_BASE
|
||||
/*
|
||||
* Warning, horror ahead.
|
||||
*
|
||||
* The target code lives in our "secure ram", but u-boot doesn't know
|
||||
* that, and has blindly added reloc_off to every relocation
|
||||
* entry. Gahh. Do the opposite conversion. This hack also prevents
|
||||
* GCC from generating code veeners, which u-boot doesn't relocate at
|
||||
* all...
|
||||
*/
|
||||
#define secure_ram_addr(_fn) ({ \
|
||||
DECLARE_GLOBAL_DATA_PTR; \
|
||||
void *__fn = _fn; \
|
||||
typeof(_fn) *__tmp = (__fn - gd->reloc_off); \
|
||||
__tmp; \
|
||||
})
|
||||
#else
|
||||
#define secure_ram_addr(_fn) (_fn)
|
||||
#endif
|
||||
|
||||
#endif
|
@ -17,13 +17,14 @@
|
||||
|
||||
#include <common.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/armv7.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int arch_fixup_memory_node(void *blob)
|
||||
int arch_fixup_fdt(void *blob)
|
||||
{
|
||||
bd_t *bd = gd->bd;
|
||||
int bank;
|
||||
int bank, ret;
|
||||
u64 start[CONFIG_NR_DRAM_BANKS];
|
||||
u64 size[CONFIG_NR_DRAM_BANKS];
|
||||
|
||||
@ -32,5 +33,12 @@ int arch_fixup_memory_node(void *blob)
|
||||
size[bank] = bd->bi_dram[bank].size;
|
||||
}
|
||||
|
||||
return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
|
||||
ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
|
||||
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = armv7_update_dt(blob);
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
@ -20,6 +20,7 @@
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/bootm.h>
|
||||
#include <asm/secure.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
|
||||
@ -184,27 +185,17 @@ static void setup_end_tag(bd_t *bd)
|
||||
|
||||
__weak void setup_board_tags(struct tag **in_params) {}
|
||||
|
||||
#ifdef CONFIG_ARM64
|
||||
static void do_nonsec_virt_switch(void)
|
||||
{
|
||||
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
|
||||
if (armv7_switch_nonsec() == 0)
|
||||
#ifdef CONFIG_ARMV7_VIRT
|
||||
if (armv7_switch_hyp() == 0)
|
||||
debug("entered HYP mode\n");
|
||||
#else
|
||||
debug("entered non-secure state\n");
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARM64
|
||||
smp_kick_all_cpus();
|
||||
flush_dcache_all(); /* flush cache before swtiching to EL2 */
|
||||
armv8_switch_to_el2();
|
||||
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
|
||||
armv8_switch_to_el1();
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Subcommand: PREP */
|
||||
static void boot_prep_linux(bootm_headers_t *images)
|
||||
@ -242,7 +233,6 @@ static void boot_prep_linux(bootm_headers_t *images)
|
||||
printf("FDT and ATAGS support not compiled in - hanging\n");
|
||||
hang();
|
||||
}
|
||||
do_nonsec_virt_switch();
|
||||
}
|
||||
|
||||
/* Subcommand: GO */
|
||||
@ -260,8 +250,10 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
|
||||
|
||||
announce_and_cleanup(fake);
|
||||
|
||||
if (!fake)
|
||||
if (!fake) {
|
||||
do_nonsec_virt_switch();
|
||||
kernel_entry(images->ft_addr);
|
||||
}
|
||||
#else
|
||||
unsigned long machid = gd->bd->bi_arch_number;
|
||||
char *s;
|
||||
@ -287,8 +279,15 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
|
||||
else
|
||||
r2 = gd->bd->bi_boot_params;
|
||||
|
||||
if (!fake)
|
||||
if (!fake) {
|
||||
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
|
||||
armv7_init_nonsec();
|
||||
secure_ram_addr(_do_nonsec_entry)(kernel_entry,
|
||||
0, machid, r2);
|
||||
#else
|
||||
kernel_entry(0, machid, r2);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -360,7 +359,7 @@ void boot_prep_vxworks(bootm_headers_t *images)
|
||||
if (images->ft_addr) {
|
||||
off = fdt_path_offset(images->ft_addr, "/memory");
|
||||
if (off < 0) {
|
||||
if (arch_fixup_memory_node(images->ft_addr))
|
||||
if (arch_fixup_fdt(images->ft_addr))
|
||||
puts("## WARNING: fixup memory failed!\n");
|
||||
}
|
||||
}
|
||||
|
@ -103,7 +103,7 @@ void show_regs (struct pt_regs *regs)
|
||||
"UK12_26", "UK13_26", "UK14_26", "UK15_26",
|
||||
"USER_32", "FIQ_32", "IRQ_32", "SVC_32",
|
||||
"UK4_32", "UK5_32", "UK6_32", "ABT_32",
|
||||
"UK8_32", "UK9_32", "UK10_32", "UND_32",
|
||||
"UK8_32", "UK9_32", "HYP_32", "UND_32",
|
||||
"UK12_32", "UK13_32", "UK14_32", "SYS_32",
|
||||
};
|
||||
|
||||
|
@ -25,4 +25,6 @@ char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
|
||||
char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
|
||||
char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
|
||||
char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
|
||||
char __secure_start[0] __attribute__((section(".__secure_start")));
|
||||
char __secure_end[0] __attribute__((section(".__secure_end")));
|
||||
char _end[0] __attribute__((section(".__end")));
|
||||
|
@ -112,11 +112,11 @@ static void jtag_send(const char *raw_str, uint32_t len)
|
||||
if (cooked_str != raw_str)
|
||||
free((char *)cooked_str);
|
||||
}
|
||||
static void jtag_putc(const char c)
|
||||
static void jtag_putc(struct stdio_dev *dev, const char c)
|
||||
{
|
||||
jtag_send(&c, 1);
|
||||
}
|
||||
static void jtag_puts(const char *s)
|
||||
static void jtag_puts(struct stdio_dev *dev, const char *s)
|
||||
{
|
||||
jtag_send(s, strlen(s));
|
||||
}
|
||||
@ -133,7 +133,7 @@ static int jtag_tstc_dbg(void)
|
||||
}
|
||||
|
||||
/* Higher layers want to know when any data is available */
|
||||
static int jtag_tstc(void)
|
||||
static int jtag_tstc(struct stdio_dev *dev)
|
||||
{
|
||||
return jtag_tstc_dbg() || leftovers_len;
|
||||
}
|
||||
@ -142,7 +142,7 @@ static int jtag_tstc(void)
|
||||
* [32bit length][actual data]
|
||||
*/
|
||||
static uint32_t leftovers;
|
||||
static int jtag_getc(void)
|
||||
static int jtag_getc(struct stdio_dev *dev)
|
||||
{
|
||||
int ret;
|
||||
uint32_t emudat;
|
||||
@ -173,7 +173,7 @@ static int jtag_getc(void)
|
||||
leftovers = emudat;
|
||||
}
|
||||
|
||||
return jtag_getc();
|
||||
return jtag_getc(dev);
|
||||
}
|
||||
|
||||
int drv_jtag_console_init(void)
|
||||
|
@ -15,7 +15,7 @@ typedef long __kernel_off_t;
|
||||
typedef int __kernel_pid_t;
|
||||
typedef unsigned int __kernel_uid_t;
|
||||
typedef unsigned int __kernel_gid_t;
|
||||
typedef unsigned long __kernel_size_t;
|
||||
typedef unsigned int __kernel_size_t;
|
||||
typedef int __kernel_ssize_t;
|
||||
typedef long __kernel_ptrdiff_t;
|
||||
typedef long __kernel_time_t;
|
||||
|
@ -384,7 +384,7 @@ struct stdio_dev *open_port(int num, int baudrate)
|
||||
sprintf(env_val, "%d", baudrate);
|
||||
setenv(env_var, env_val);
|
||||
|
||||
if (port->start())
|
||||
if (port->start(port))
|
||||
return NULL;
|
||||
|
||||
set_bit(num, &initialized);
|
||||
@ -407,7 +407,7 @@ int close_port(int num)
|
||||
if (!port)
|
||||
return -1;
|
||||
|
||||
ret = port->stop();
|
||||
ret = port->stop(port);
|
||||
clear_bit(num, &initialized);
|
||||
|
||||
return ret;
|
||||
@ -418,7 +418,7 @@ int write_port(struct stdio_dev *port, char *buf)
|
||||
if (!port || !buf)
|
||||
return -1;
|
||||
|
||||
port->puts(buf);
|
||||
port->puts(port, buf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -433,8 +433,8 @@ int read_port(struct stdio_dev *port, char *buf, int size)
|
||||
if (!size)
|
||||
return 0;
|
||||
|
||||
while (port->tstc()) {
|
||||
buf[cnt++] = port->getc();
|
||||
while (port->tstc(port)) {
|
||||
buf[cnt++] = port->getc(port);
|
||||
if (cnt > size)
|
||||
break;
|
||||
}
|
||||
|
@ -948,7 +948,7 @@ static inline void console_newline (void)
|
||||
}
|
||||
}
|
||||
|
||||
void video_putc (const char c)
|
||||
void video_putc(struct stdio_dev *dev, const char c)
|
||||
{
|
||||
if (!video_enable) {
|
||||
serial_putc (c);
|
||||
@ -985,7 +985,7 @@ void video_putc (const char c)
|
||||
}
|
||||
}
|
||||
|
||||
void video_puts (const char *s)
|
||||
void video_puts(struct stdio_dev *dev, const char *s)
|
||||
{
|
||||
int count = strlen (s);
|
||||
|
||||
@ -994,7 +994,7 @@ void video_puts (const char *s)
|
||||
serial_putc (*s++);
|
||||
else
|
||||
while (count--)
|
||||
video_putc (*s++);
|
||||
video_putc(dev, *s++);
|
||||
}
|
||||
|
||||
/************************************************************************/
|
||||
|
@ -4,6 +4,7 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm/root.h>
|
||||
#include <os.h>
|
||||
#include <asm/state.h>
|
||||
|
||||
@ -14,6 +15,9 @@ void reset_cpu(ulong ignored)
|
||||
if (state_uninit())
|
||||
os_exit(2);
|
||||
|
||||
if (dm_uninit())
|
||||
os_exit(2);
|
||||
|
||||
/* This is considered normal termination for now */
|
||||
os_exit(0);
|
||||
}
|
||||
|
@ -6,6 +6,7 @@
|
||||
#include <common.h>
|
||||
#include <os.h>
|
||||
#include <asm/getopt.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/sections.h>
|
||||
#include <asm/state.h>
|
||||
|
||||
@ -218,6 +219,7 @@ SANDBOX_CMDLINE_OPT_SHORT(terminal, 't', 1,
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
struct sandbox_state *state;
|
||||
gd_t data;
|
||||
int ret;
|
||||
|
||||
ret = state_init();
|
||||
@ -236,6 +238,12 @@ int main(int argc, char *argv[])
|
||||
if (state->ram_buf_rm && state->ram_buf_fname)
|
||||
os_unlink(state->ram_buf_fname);
|
||||
|
||||
memset(&data, '\0', sizeof(data));
|
||||
gd = &data;
|
||||
#ifdef CONFIG_SYS_MALLOC_F_LEN
|
||||
gd->malloc_base = CONFIG_MALLOC_F_ADDR;
|
||||
#endif
|
||||
|
||||
/* Do pre- and post-relocation init */
|
||||
board_init_f(0);
|
||||
|
||||
|
@ -7,7 +7,6 @@
|
||||
#ifndef _ASM_CONFIG_H_
|
||||
#define _ASM_CONFIG_H_
|
||||
|
||||
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
|
||||
#define CONFIG_SANDBOX_ARCH
|
||||
|
||||
/* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */
|
||||
|
@ -1,76 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Nobuhiro Iwamatsu
|
||||
* Copyright (C) 2008 Renesas Solutions Corp.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
|
||||
OUTPUT_ARCH(sh)
|
||||
ENTRY(_start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/*
|
||||
* entry and reloct_dst will be provided via ldflags
|
||||
*/
|
||||
. = .;
|
||||
|
||||
PROVIDE (_ftext = .);
|
||||
PROVIDE (_fcode = .);
|
||||
PROVIDE (_start = .);
|
||||
|
||||
.text :
|
||||
{
|
||||
KEEP(arch/sh/cpu/sh2/start.o (.text))
|
||||
. = ALIGN(8192);
|
||||
common/env_embedded.o (.ppcenv)
|
||||
. = ALIGN(8192);
|
||||
common/env_embedded.o (.ppcenvr)
|
||||
. = ALIGN(8192);
|
||||
*(.text)
|
||||
. = ALIGN(4);
|
||||
} =0xFF
|
||||
PROVIDE (_ecode = .);
|
||||
.rodata :
|
||||
{
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (_etext = .);
|
||||
|
||||
|
||||
PROVIDE (_fdata = .);
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (_edata = .);
|
||||
|
||||
PROVIDE (_fgot = .);
|
||||
.got :
|
||||
{
|
||||
*(.got)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (_egot = .);
|
||||
|
||||
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
PROVIDE (reloc_dst_end = .);
|
||||
|
||||
PROVIDE (bss_start = .);
|
||||
PROVIDE (__bss_start = .);
|
||||
.bss :
|
||||
{
|
||||
*(.bss)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (bss_end = .);
|
||||
|
||||
PROVIDE (__bss_end = .);
|
||||
}
|
@ -1,80 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2007
|
||||
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
*
|
||||
* Copyright (C) 2008-2009
|
||||
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
|
||||
OUTPUT_ARCH(sh)
|
||||
ENTRY(_start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/*
|
||||
* entry and reloct_dst will be provided via ldflags
|
||||
*/
|
||||
. = .;
|
||||
|
||||
PROVIDE (_ftext = .);
|
||||
PROVIDE (_fcode = .);
|
||||
PROVIDE (_start = .);
|
||||
|
||||
.text :
|
||||
{
|
||||
KEEP(arch/sh/cpu/sh4/start.o (.text))
|
||||
. = ALIGN(8192);
|
||||
common/env_embedded.o (.ppcenv)
|
||||
. = ALIGN(8192);
|
||||
common/env_embedded.o (.ppcenvr)
|
||||
. = ALIGN(8192);
|
||||
*(.text)
|
||||
. = ALIGN(4);
|
||||
} =0xFF
|
||||
PROVIDE (_ecode = .);
|
||||
.rodata :
|
||||
{
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (_etext = .);
|
||||
|
||||
|
||||
PROVIDE (_fdata = .);
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (_edata = .);
|
||||
|
||||
PROVIDE (_fgot = .);
|
||||
.got :
|
||||
{
|
||||
*(.got)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (_egot = .);
|
||||
|
||||
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
PROVIDE (reloc_dst_end = .);
|
||||
/* _reloc_dst_end = .; */
|
||||
|
||||
PROVIDE (bss_start = .);
|
||||
PROVIDE (__bss_start = .);
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.bss)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
PROVIDE (bss_end = .);
|
||||
|
||||
PROVIDE (__bss_end = .);
|
||||
}
|
@ -1,10 +1,10 @@
|
||||
/*
|
||||
* Copyright (C) 2007
|
||||
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*
|
||||
* Copyright (C) 2007
|
||||
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
*
|
||||
* Copyright (C) 2008-2009
|
||||
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*
|
||||
* Copyright (C) 2008
|
||||
* Mark Jonas <mark.jonas@de.bosch.com>
|
||||
*
|
||||
@ -28,7 +28,7 @@ SECTIONS
|
||||
|
||||
.text :
|
||||
{
|
||||
KEEP(arch/sh/cpu/sh3/start.o (.text))
|
||||
KEEP(*/start.o (.text))
|
||||
. = ALIGN(8192);
|
||||
common/env_embedded.o (.ppcenv)
|
||||
. = ALIGN(8192);
|
@ -1,7 +1,5 @@
|
||||
/*
|
||||
* Linker script for Gaisler Research AB's GRSIM LEON3 simulator.
|
||||
*
|
||||
* (C) Copyright 2007
|
||||
* (C) Copyright 2007-2008
|
||||
* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
@ -43,7 +41,7 @@ SECTIONS
|
||||
_text = .;
|
||||
|
||||
*(.start)
|
||||
arch/sparc/cpu/leon3/start.o (.text)
|
||||
*/start.o (.text)
|
||||
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
|
||||
. = ALIGN(8192);
|
||||
/* PROM CODE, Will be relocated to the end of memory,
|
@ -104,7 +104,7 @@ static void __video_putc(const char c, int *x, int *y)
|
||||
}
|
||||
}
|
||||
|
||||
static void video_putc(const char c)
|
||||
static void video_putc(struct stdio_dev *dev, const char c)
|
||||
{
|
||||
int x, y, pos;
|
||||
|
||||
@ -123,7 +123,7 @@ static void video_putc(const char c)
|
||||
outb_p(0xff & (pos >> 1), vidport+1);
|
||||
}
|
||||
|
||||
static void video_puts(const char *s)
|
||||
static void video_puts(struct stdio_dev *dev, const char *s)
|
||||
{
|
||||
int x, y, pos;
|
||||
char c;
|
||||
@ -178,8 +178,6 @@ int video_init(void)
|
||||
vga_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
|
||||
vga_dev.putc = video_putc; /* 'putc' function */
|
||||
vga_dev.puts = video_puts; /* 'puts' function */
|
||||
vga_dev.tstc = NULL; /* 'tstc' function */
|
||||
vga_dev.getc = NULL; /* 'getc' function */
|
||||
|
||||
if (stdio_register(&vga_dev) == 0)
|
||||
return 1;
|
||||
@ -191,8 +189,6 @@ int video_init(void)
|
||||
strcpy(kbd_dev.name, "kbd");
|
||||
kbd_dev.ext = 0;
|
||||
kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
|
||||
kbd_dev.putc = NULL; /* 'putc' function */
|
||||
kbd_dev.puts = NULL; /* 'puts' function */
|
||||
kbd_dev.tstc = i8042_tstc; /* 'tstc' function */
|
||||
kbd_dev.getc = i8042_getc; /* 'getc' function */
|
||||
|
||||
|
@ -391,14 +391,6 @@ void video_stop(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
void video_putc(const char c)
|
||||
{
|
||||
}
|
||||
|
||||
void video_puts(const char *s)
|
||||
{
|
||||
}
|
||||
|
||||
int drv_video_init(void)
|
||||
{
|
||||
int error, devices = 1;
|
||||
@ -448,8 +440,6 @@ int drv_video_init(void)
|
||||
strcpy(videodev.name, "video");
|
||||
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
|
||||
videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
|
||||
videodev.putc = video_putc; /* 'putc' function */
|
||||
videodev.puts = video_puts; /* 'puts' function */
|
||||
|
||||
error = stdio_register(&videodev);
|
||||
|
||||
|
@ -281,14 +281,6 @@ static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
|
||||
|
||||
}
|
||||
|
||||
void video_putc(const char c)
|
||||
{
|
||||
}
|
||||
|
||||
void video_puts(const char *s)
|
||||
{
|
||||
}
|
||||
|
||||
int drv_video_init(void)
|
||||
{
|
||||
int error, devices = 1;
|
||||
@ -338,8 +330,6 @@ int drv_video_init(void)
|
||||
strcpy(videodev.name, "video");
|
||||
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
|
||||
videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
|
||||
videodev.putc = video_putc; /* 'putc' function */
|
||||
videodev.puts = video_puts; /* 'puts' function */
|
||||
|
||||
error = stdio_register(&videodev);
|
||||
|
||||
|
@ -283,14 +283,6 @@ static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
|
||||
|
||||
}
|
||||
|
||||
void video_putc(const char c)
|
||||
{
|
||||
}
|
||||
|
||||
void video_puts(const char *s)
|
||||
{
|
||||
}
|
||||
|
||||
int drv_video_init(void)
|
||||
{
|
||||
int error, devices = 1;
|
||||
@ -342,8 +334,6 @@ int drv_video_init(void)
|
||||
strcpy(videodev.name, "video");
|
||||
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
|
||||
videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
|
||||
videodev.putc = video_putc; /* 'putc' function */
|
||||
videodev.puts = video_puts; /* 'puts' function */
|
||||
|
||||
error = stdio_register(&videodev);
|
||||
|
||||
|
@ -12,9 +12,6 @@
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_BSP)
|
||||
|
||||
extern int do_source (cmd_tbl_t *, int, int, char *[]);
|
||||
|
||||
#define ADDRMASK 0xfffff000
|
||||
|
||||
/*
|
||||
@ -27,7 +24,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
int count2 = 0;
|
||||
char addr[16];
|
||||
char str[] = "\\|/-";
|
||||
char *local_args[2];
|
||||
u32 la, ptm1la;
|
||||
|
||||
#if defined(CONFIG_440)
|
||||
@ -84,9 +80,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
* Boot image via "source" command
|
||||
*/
|
||||
printf("executing script at addr 0x%s ...\n", addr);
|
||||
local_args[0] = addr;
|
||||
local_args[1] = NULL;
|
||||
do_source(cmdtp, 0, 1, local_args);
|
||||
source(la, NULL);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
|
@ -56,14 +56,16 @@ ulong flash_init(void)
|
||||
|
||||
int flash_get_offsets(ulong base, flash_info_t * info)
|
||||
{
|
||||
int j, k;
|
||||
int i;
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
|
||||
|
||||
info->start[0] = base;
|
||||
for (k = 0, j = 0; j < CONFIG_SYS_SST_SECT; j++, k++) {
|
||||
info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ;
|
||||
info->protect[k] = 0;
|
||||
info->protect[0] = 0;
|
||||
for (i = 1; i < CONFIG_SYS_SST_SECT; i++) {
|
||||
info->start[i] = info->start[i - 1]
|
||||
+ CONFIG_SYS_SST_SECTSZ;
|
||||
info->protect[i] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1,143 +0,0 @@
|
||||
/*
|
||||
* Linker script for Gaisler Research AB's GR-CPCI-AX2000 board
|
||||
* with template design.
|
||||
*
|
||||
* (C) Copyright 2008
|
||||
* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
|
||||
OUTPUT_ARCH(sparc)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
|
||||
.text : {
|
||||
_load_addr = .;
|
||||
_text = .;
|
||||
|
||||
*(.start)
|
||||
arch/sparc/cpu/leon3/start.o (.text)
|
||||
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
|
||||
. = ALIGN(8192);
|
||||
/* PROM CODE, Will be relocated to the end of memory,
|
||||
* no global data accesses please.
|
||||
*/
|
||||
__prom_start = .;
|
||||
*(.prom.pgt)
|
||||
*(.prom.data)
|
||||
*(.prom.text)
|
||||
. = ALIGN(16);
|
||||
__prom_end = .;
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
/* *(.got1)*/
|
||||
. = ALIGN(16);
|
||||
*(.eh_frame)
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
/* CMD Table */
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.data.rel)
|
||||
*(.data.rel.*)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
__got_start = .;
|
||||
.got : {
|
||||
*(.got)
|
||||
/* *(.data.rel)
|
||||
*(.data.rel.local)*/
|
||||
. = ALIGN(16);
|
||||
}
|
||||
__got_end = .;
|
||||
|
||||
/* .data.rel : { } */
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(16); /* to speed clearing of bss up */
|
||||
}
|
||||
__bss_end = . ;
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
|
||||
/* Relocated into main memory */
|
||||
|
||||
/* Start of main memory */
|
||||
/*. = 0x40000000;*/
|
||||
|
||||
.stack (NOLOAD) : { *(.stack) }
|
||||
|
||||
/* PROM CODE */
|
||||
|
||||
/* global data in RAM passed to kernel after booting */
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
}
|
@ -1,143 +0,0 @@
|
||||
/*
|
||||
* Linker script for Gaisler Research AB's Template design
|
||||
* for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA.
|
||||
*
|
||||
* (C) Copyright 2008
|
||||
* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
|
||||
OUTPUT_ARCH(sparc)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
|
||||
.text : {
|
||||
_load_addr = .;
|
||||
_text = .;
|
||||
|
||||
*(.start)
|
||||
arch/sparc/cpu/leon3/start.o (.text)
|
||||
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
|
||||
. = ALIGN(8192);
|
||||
/* PROM CODE, Will be relocated to the end of memory,
|
||||
* no global data accesses please.
|
||||
*/
|
||||
__prom_start = .;
|
||||
*(.prom.pgt)
|
||||
*(.prom.data)
|
||||
*(.prom.text)
|
||||
. = ALIGN(16);
|
||||
__prom_end = .;
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
/* *(.got1)*/
|
||||
. = ALIGN(16);
|
||||
*(.eh_frame)
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
/* CMD Table */
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.data.rel)
|
||||
*(.data.rel.*)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
__got_start = .;
|
||||
.got : {
|
||||
*(.got)
|
||||
/* *(.data.rel)
|
||||
*(.data.rel.local)*/
|
||||
. = ALIGN(16);
|
||||
}
|
||||
__got_end = .;
|
||||
|
||||
/* .data.rel : { } */
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(16); /* to speed clearing of bss up */
|
||||
}
|
||||
__bss_end = . ;
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
|
||||
/* Relocated into main memory */
|
||||
|
||||
/* Start of main memory */
|
||||
/*. = 0x40000000;*/
|
||||
|
||||
.stack (NOLOAD) : { *(.stack) }
|
||||
|
||||
/* PROM CODE */
|
||||
|
||||
/* global data in RAM passed to kernel after booting */
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
}
|
@ -1,145 +0,0 @@
|
||||
/*
|
||||
* Linker script for Gaisler Research AB's GR-XC3S-1500 board
|
||||
* with template design.
|
||||
*
|
||||
* (C) Copyright 2007
|
||||
* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
|
||||
OUTPUT_ARCH(sparc)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
|
||||
.text : {
|
||||
_load_addr = .;
|
||||
_text = .;
|
||||
|
||||
*(.start)
|
||||
arch/sparc/cpu/leon3/start.o (.text)
|
||||
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
|
||||
. = ALIGN(8192);
|
||||
/* PROM CODE, Will be relocated to the end of memory,
|
||||
* no global data accesses please.
|
||||
*/
|
||||
__prom_start = .;
|
||||
*(.prom.pgt)
|
||||
*(.prom.data)
|
||||
*(.prom.text)
|
||||
. = ALIGN(16);
|
||||
__prom_end = .;
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
/* *(.got1)*/
|
||||
. = ALIGN(16);
|
||||
*(.eh_frame)
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
/* CMD Table */
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.data.rel)
|
||||
*(.data.rel.*)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
__got_start = .;
|
||||
.got : {
|
||||
*(.got)
|
||||
/* *(.data.rel)
|
||||
*(.data.rel.local)*/
|
||||
. = ALIGN(16);
|
||||
}
|
||||
__got_end = .;
|
||||
|
||||
/* .data.rel : { } */
|
||||
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(16); /* to speed clearing of bss up */
|
||||
}
|
||||
__bss_end = . ;
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
|
||||
/* Relocated into main memory */
|
||||
|
||||
/* Start of main memory */
|
||||
/*. = 0x40000000;*/
|
||||
|
||||
.stack (NOLOAD) : { *(.stack) }
|
||||
|
||||
/* PROM CODE */
|
||||
|
||||
/* global data in RAM passed to kernel after booting */
|
||||
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
}
|
@ -1,142 +0,0 @@
|
||||
/*
|
||||
* Linker script for Gaisler Research AB's GRSIM LEON2 simulator.
|
||||
*
|
||||
* (C) Copyright 2007
|
||||
* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
|
||||
OUTPUT_ARCH(sparc)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
|
||||
.text : {
|
||||
_load_addr = .;
|
||||
_text = .;
|
||||
|
||||
*(.start)
|
||||
arch/sparc/cpu/leon2/start.o (.text)
|
||||
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
|
||||
. = ALIGN(8192);
|
||||
/* PROM CODE, Will be relocated to the end of memory,
|
||||
* no global data accesses please.
|
||||
*/
|
||||
__prom_start = .;
|
||||
*(.prom.pgt)
|
||||
*(.prom.data)
|
||||
*(.prom.text)
|
||||
. = ALIGN(16);
|
||||
__prom_end = .;
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
/* *(.got1)*/
|
||||
. = ALIGN(16);
|
||||
*(.eh_frame)
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
/* CMD Table */
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.data.rel)
|
||||
*(.data.rel.*)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
__got_start = .;
|
||||
.got : {
|
||||
*(.got)
|
||||
/* *(.data.rel)
|
||||
*(.data.rel.local)*/
|
||||
. = ALIGN(16);
|
||||
}
|
||||
__got_end = .;
|
||||
|
||||
/* .data.rel : { } */
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(16); /* to speed clearing of bss up */
|
||||
}
|
||||
__bss_end = . ;
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
|
||||
/* Relocated into main memory */
|
||||
|
||||
/* Start of main memory */
|
||||
/*. = 0x40000000;*/
|
||||
|
||||
.stack (NOLOAD) : { *(.stack) }
|
||||
|
||||
/* PROM CODE */
|
||||
|
||||
/* global data in RAM passed to kernel after booting */
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
}
|
@ -34,41 +34,17 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
static const struct ddr_data ddr2_data = {
|
||||
.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
|
||||
(MT47H128M16RT25E_RD_DQS<<20) |
|
||||
(MT47H128M16RT25E_RD_DQS<<10) |
|
||||
(MT47H128M16RT25E_RD_DQS<<0)),
|
||||
.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
|
||||
(MT47H128M16RT25E_WR_DQS<<20) |
|
||||
(MT47H128M16RT25E_WR_DQS<<10) |
|
||||
(MT47H128M16RT25E_WR_DQS<<0)),
|
||||
.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
|
||||
(MT47H128M16RT25E_PHY_WRLVL<<20) |
|
||||
(MT47H128M16RT25E_PHY_WRLVL<<10) |
|
||||
(MT47H128M16RT25E_PHY_WRLVL<<0)),
|
||||
.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
|
||||
(MT47H128M16RT25E_PHY_GATELVL<<20) |
|
||||
(MT47H128M16RT25E_PHY_GATELVL<<10) |
|
||||
(MT47H128M16RT25E_PHY_GATELVL<<0)),
|
||||
.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
|
||||
(MT47H128M16RT25E_PHY_FIFO_WE<<20) |
|
||||
(MT47H128M16RT25E_PHY_FIFO_WE<<10) |
|
||||
(MT47H128M16RT25E_PHY_FIFO_WE<<0)),
|
||||
.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
|
||||
(MT47H128M16RT25E_PHY_WR_DATA<<20) |
|
||||
(MT47H128M16RT25E_PHY_WR_DATA<<10) |
|
||||
(MT47H128M16RT25E_PHY_WR_DATA<<0)),
|
||||
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
|
||||
.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
|
||||
.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
|
||||
};
|
||||
|
||||
static const struct cmd_control ddr2_cmd_ctrl_data = {
|
||||
.cmd0csratio = MT47H128M16RT25E_RATIO,
|
||||
.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
|
||||
|
||||
.cmd1csratio = MT47H128M16RT25E_RATIO,
|
||||
.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
|
||||
|
||||
.cmd2csratio = MT47H128M16RT25E_RATIO,
|
||||
.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
|
||||
};
|
||||
|
||||
static const struct emif_regs ddr2_emif_reg_data = {
|
||||
|
@ -204,8 +204,6 @@ int drv_isa_kbd_init (void)
|
||||
memset (&kbddev, 0, sizeof(kbddev));
|
||||
strcpy(kbddev.name, DEVNAME);
|
||||
kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
|
||||
kbddev.putc = NULL ;
|
||||
kbddev.puts = NULL ;
|
||||
kbddev.getc = kbd_getc ;
|
||||
kbddev.tstc = kbd_testc ;
|
||||
|
||||
@ -250,7 +248,7 @@ void kbd_put_queue(char data)
|
||||
}
|
||||
|
||||
/* test if a character is in the queue */
|
||||
int kbd_testc(void)
|
||||
int kbd_testc(struct stdio_dev *dev)
|
||||
{
|
||||
if(in_pointer==out_pointer)
|
||||
return(0); /* no data */
|
||||
@ -258,7 +256,7 @@ int kbd_testc(void)
|
||||
return(1);
|
||||
}
|
||||
/* gets the character from the queue */
|
||||
int kbd_getc(void)
|
||||
int kbd_getc(struct stdio_dev *dev)
|
||||
{
|
||||
char c;
|
||||
while(in_pointer==out_pointer);
|
||||
|
@ -8,8 +8,10 @@
|
||||
#ifndef _KBD_H_
|
||||
#define _KBD_H_
|
||||
|
||||
extern int kbd_testc(void);
|
||||
extern int kbd_getc(void);
|
||||
struct stdio_dev;
|
||||
|
||||
int kbd_testc(struct stdio_dev *sdev);
|
||||
int kbd_getc(struct stdio_dev *sdev);
|
||||
extern void kbd_interrupt(void);
|
||||
extern char *kbd_initialize(void);
|
||||
|
||||
|
@ -445,7 +445,7 @@ void pci_con_put_it(const char c)
|
||||
PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA);
|
||||
}
|
||||
|
||||
void pci_con_putc(const char c)
|
||||
void pci_con_putc(struct stdio_dev *dev, const char c)
|
||||
{
|
||||
pci_con_put_it(c);
|
||||
if(c == '\n')
|
||||
@ -453,7 +453,7 @@ void pci_con_putc(const char c)
|
||||
}
|
||||
|
||||
|
||||
int pci_con_getc(void)
|
||||
int pci_con_getc(struct stdio_dev *dev)
|
||||
{
|
||||
int res;
|
||||
int diff;
|
||||
@ -473,14 +473,14 @@ int pci_con_getc(void)
|
||||
return res;
|
||||
}
|
||||
|
||||
int pci_con_tstc(void)
|
||||
int pci_con_tstc(struct stdio_dev *dev)
|
||||
{
|
||||
if(r_ptr==(volatile int)w_ptr)
|
||||
return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
void pci_con_puts (const char *s)
|
||||
void pci_con_puts(struct stdio_dev *dev, const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
pci_con_putc(*s);
|
||||
|
@ -585,7 +585,7 @@ static void rx51_kp_fill(u8 k, u8 mods)
|
||||
* Routine: rx51_kp_tstc
|
||||
* Description: Test if key was pressed (from buffer).
|
||||
*/
|
||||
int rx51_kp_tstc(void)
|
||||
int rx51_kp_tstc(struct stdio_dev *sdev)
|
||||
{
|
||||
u8 c, r, dk, i;
|
||||
u8 intr;
|
||||
@ -641,10 +641,10 @@ int rx51_kp_tstc(void)
|
||||
* Routine: rx51_kp_getc
|
||||
* Description: Get last pressed key (from buffer).
|
||||
*/
|
||||
int rx51_kp_getc(void)
|
||||
int rx51_kp_getc(struct stdio_dev *sdev)
|
||||
{
|
||||
keybuf_head %= KEYBUF_SIZE;
|
||||
while (!rx51_kp_tstc())
|
||||
while (!rx51_kp_tstc(sdev))
|
||||
WATCHDOG_RESET();
|
||||
return keybuf[keybuf_head++];
|
||||
}
|
||||
|
@ -16,7 +16,9 @@
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <fdt_support.h>
|
||||
#include <lcd.h>
|
||||
#include <mmc.h>
|
||||
#include <asm/arch/mbox.h>
|
||||
#include <asm/arch/sdhci.h>
|
||||
#include <asm/global_data.h>
|
||||
@ -91,7 +93,7 @@ int board_init(void)
|
||||
return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
|
||||
}
|
||||
|
||||
int board_mmc_init(void)
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16);
|
||||
int ret;
|
||||
|
9
board/renesas/alt/Makefile
Normal file
9
board/renesas/alt/Makefile
Normal file
@ -0,0 +1,9 @@
|
||||
#
|
||||
# board/renesas/alt/Makefile
|
||||
#
|
||||
# Copyright (C) 2014 Renesas Electronics Corporation
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
|
||||
obj-y := alt.o qos.o
|
173
board/renesas/alt/alt.c
Normal file
173
board/renesas/alt/alt.c
Normal file
@ -0,0 +1,173 @@
|
||||
/*
|
||||
* board/renesas/alt/alt.c
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/arch/rmobile.h>
|
||||
#include <netdev.h>
|
||||
#include <miiphy.h>
|
||||
#include <i2c.h>
|
||||
#include <div64.h>
|
||||
#include "qos.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define CLK2MHZ(clk) (clk / 1000 / 1000)
|
||||
void s_init(void)
|
||||
{
|
||||
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
|
||||
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
|
||||
|
||||
/* Watchdog init */
|
||||
writel(0xA5A5A500, &rwdt->rwtcsra);
|
||||
writel(0xA5A5A500, &swdt->swtcsra);
|
||||
|
||||
/* QoS */
|
||||
qos_init();
|
||||
}
|
||||
|
||||
#define MSTPSR1 0xE6150038
|
||||
#define SMSTPCR1 0xE6150134
|
||||
#define TMU0_MSTP125 (1 << 25)
|
||||
|
||||
#define MSTPSR7 0xE61501C4
|
||||
#define SMSTPCR7 0xE615014C
|
||||
#define SCIF0_MSTP719 (1 << 19)
|
||||
|
||||
#define MSTPSR8 0xE61509A0
|
||||
#define SMSTPCR8 0xE6150990
|
||||
#define ETHER_MSTP813 (1 << 13)
|
||||
|
||||
#define mstp_setbits(type, addr, saddr, set) \
|
||||
out_##type((saddr), in_##type(addr) | (set))
|
||||
#define mstp_clrbits(type, addr, saddr, clear) \
|
||||
out_##type((saddr), in_##type(addr) & ~(clear))
|
||||
#define mstp_setbits_le32(addr, saddr, set) \
|
||||
mstp_setbits(le32, addr, saddr, set)
|
||||
#define mstp_clrbits_le32(addr, saddr, clear) \
|
||||
mstp_clrbits(le32, addr, saddr, clear)
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* TMU */
|
||||
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
|
||||
|
||||
/* SCIF0 */
|
||||
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719);
|
||||
|
||||
/* ETHER */
|
||||
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void arch_preboot_os(void)
|
||||
{
|
||||
/* Disable TMU0 */
|
||||
mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = ALT_SDRAM_BASE + 0x100;
|
||||
|
||||
/* Init PFC controller */
|
||||
r8a7794_pinmux_init();
|
||||
|
||||
/* Ether Enable */
|
||||
gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
|
||||
gpio_request(GPIO_FN_ETH_RX_ER, NULL);
|
||||
gpio_request(GPIO_FN_ETH_RXD0, NULL);
|
||||
gpio_request(GPIO_FN_ETH_RXD1, NULL);
|
||||
gpio_request(GPIO_FN_ETH_LINK, NULL);
|
||||
gpio_request(GPIO_FN_ETH_REFCLK, NULL);
|
||||
gpio_request(GPIO_FN_ETH_MDIO, NULL);
|
||||
gpio_request(GPIO_FN_ETH_TXD1, NULL);
|
||||
gpio_request(GPIO_FN_ETH_TX_EN, NULL);
|
||||
gpio_request(GPIO_FN_ETH_MAGIC, NULL);
|
||||
gpio_request(GPIO_FN_ETH_TXD0, NULL);
|
||||
gpio_request(GPIO_FN_ETH_MDC, NULL);
|
||||
gpio_request(GPIO_FN_IRQ8, NULL);
|
||||
|
||||
/* PHY reset */
|
||||
gpio_request(GPIO_GP_1_24, NULL);
|
||||
gpio_direction_output(GPIO_GP_1_24, 0);
|
||||
mdelay(20);
|
||||
gpio_set_value(GPIO_GP_1_24, 1);
|
||||
udelay(1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define CXR24 0xEE7003C0 /* MAC address high register */
|
||||
#define CXR25 0xEE7003C8 /* MAC address low register */
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_SH_ETHER
|
||||
int ret = -ENODEV;
|
||||
u32 val;
|
||||
unsigned char enetaddr[6];
|
||||
|
||||
ret = sh_eth_initialize(bis);
|
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr))
|
||||
return ret;
|
||||
|
||||
/* Set Mac address */
|
||||
val = enetaddr[0] << 24 | enetaddr[1] << 16 |
|
||||
enetaddr[2] << 8 | enetaddr[3];
|
||||
writel(val, CXR24);
|
||||
|
||||
val = enetaddr[4] << 8 | enetaddr[5];
|
||||
writel(val, CXR25);
|
||||
|
||||
return ret;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
||||
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct rmobile_sysinfo sysinfo = {
|
||||
CONFIG_RMOBILE_BOARD_STRING
|
||||
};
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = ALT_SDRAM_BASE;
|
||||
gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
u8 val;
|
||||
|
||||
i2c_set_bus_num(1); /* PowerIC connected to ch3 */
|
||||
i2c_init(400000, 0);
|
||||
i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
|
||||
val |= 0x02;
|
||||
i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
|
||||
}
|
944
board/renesas/alt/qos.c
Normal file
944
board/renesas/alt/qos.c
Normal file
@ -0,0 +1,944 @@
|
||||
/*
|
||||
* board/renesas/alt/qos.c
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/rmobile.h>
|
||||
|
||||
/* QoS version 0.10 */
|
||||
|
||||
enum {
|
||||
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
|
||||
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
|
||||
DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
|
||||
DBSC3_15,
|
||||
DBSC3_NR,
|
||||
};
|
||||
|
||||
static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
|
||||
[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
|
||||
[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
|
||||
[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
|
||||
[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
|
||||
[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
|
||||
[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
|
||||
[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
|
||||
[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
|
||||
[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
|
||||
[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
|
||||
[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
|
||||
[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
|
||||
[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
|
||||
[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
|
||||
[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
|
||||
[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
|
||||
};
|
||||
|
||||
static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
|
||||
[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
|
||||
[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
|
||||
[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
|
||||
[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
|
||||
[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
|
||||
[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
|
||||
[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
|
||||
[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
|
||||
[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
|
||||
[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
|
||||
[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
|
||||
[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
|
||||
[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
|
||||
[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
|
||||
[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
|
||||
[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
|
||||
};
|
||||
|
||||
void qos_init(void)
|
||||
{
|
||||
int i;
|
||||
struct rcar_s3c *s3c;
|
||||
struct rcar_s3c_qos *s3c_qos;
|
||||
struct rcar_dbsc3_qos *qos_addr;
|
||||
struct rcar_mxi *mxi;
|
||||
struct rcar_mxi_qos *mxi_qos;
|
||||
struct rcar_axi_qos *axi_qos;
|
||||
|
||||
/* DBSC DBADJ2 */
|
||||
writel(0x20042004, DBSC3_0_DBADJ2);
|
||||
|
||||
/* S3C -QoS */
|
||||
s3c = (struct rcar_s3c *)S3C_BASE;
|
||||
writel(0x1F0D0B0A, &s3c->s3crorr);
|
||||
writel(0x1F0D0B09, &s3c->s3cworr);
|
||||
|
||||
/* QoS Control Registers */
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
|
||||
writel(0x00890089, &s3c_qos->s3cqos0);
|
||||
writel(0x20960010, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x20960010, &s3c_qos->s3cqos5);
|
||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
|
||||
writel(0x00890089, &s3c_qos->s3cqos0);
|
||||
writel(0x20960010, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos3);
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x20960010, &s3c_qos->s3cqos5);
|
||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||
writel(0x20AA2200, &s3c_qos->s3cqos7);
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
|
||||
writel(0x80928092, &s3c_qos->s3cqos0);
|
||||
writel(0x20960020, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA20DC, &s3c_qos->s3cqos3);
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x20960020, &s3c_qos->s3cqos5);
|
||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||
writel(0x20AA20DC, &s3c_qos->s3cqos7);
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
|
||||
writel(0x00820082, &s3c_qos->s3cqos0);
|
||||
writel(0x20960020, &s3c_qos->s3cqos1);
|
||||
writel(0x20302030, &s3c_qos->s3cqos2);
|
||||
writel(0x20AA20FA, &s3c_qos->s3cqos3);
|
||||
writel(0x00002032, &s3c_qos->s3cqos4);
|
||||
writel(0x20960020, &s3c_qos->s3cqos5);
|
||||
writel(0x20302030, &s3c_qos->s3cqos6);
|
||||
writel(0x20AA20FA, &s3c_qos->s3cqos7);
|
||||
writel(0x00002032, &s3c_qos->s3cqos8);
|
||||
|
||||
/* DBSC -QoS */
|
||||
/* DBSC0 - Read */
|
||||
for (i = DBSC3_00; i < DBSC3_NR; i++) {
|
||||
qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
|
||||
writel(0x00000002, &qos_addr->dblgcnt);
|
||||
writel(0x0000207D, &qos_addr->dbtmval0);
|
||||
writel(0x00002053, &qos_addr->dbtmval1);
|
||||
writel(0x0000202A, &qos_addr->dbtmval2);
|
||||
writel(0x00001FBD, &qos_addr->dbtmval3);
|
||||
writel(0x00000001, &qos_addr->dbrqctr);
|
||||
writel(0x00002064, &qos_addr->dbthres0);
|
||||
writel(0x0000203E, &qos_addr->dbthres1);
|
||||
writel(0x00002019, &qos_addr->dbthres2);
|
||||
writel(0x00000001, &qos_addr->dblgqon);
|
||||
}
|
||||
|
||||
/* DBSC0 - Write */
|
||||
for (i = DBSC3_00; i < DBSC3_NR; i++) {
|
||||
qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
|
||||
writel(0x00000002, &qos_addr->dblgcnt);
|
||||
writel(0x0000207D, &qos_addr->dbtmval0);
|
||||
writel(0x00002053, &qos_addr->dbtmval1);
|
||||
writel(0x00002043, &qos_addr->dbtmval2);
|
||||
writel(0x00002030, &qos_addr->dbtmval3);
|
||||
writel(0x00000001, &qos_addr->dbrqctr);
|
||||
writel(0x00002064, &qos_addr->dbthres0);
|
||||
writel(0x0000203E, &qos_addr->dbthres1);
|
||||
writel(0x00002031, &qos_addr->dbthres2);
|
||||
writel(0x00000001, &qos_addr->dblgqon);
|
||||
}
|
||||
|
||||
/* CCI-400 -QoS */
|
||||
writel(0x20001000, CCI_400_MAXOT_1);
|
||||
writel(0x20001000, CCI_400_MAXOT_2);
|
||||
writel(0x0000000C, CCI_400_QOSCNTL_1);
|
||||
writel(0x0000000C, CCI_400_QOSCNTL_2);
|
||||
|
||||
/* MXI -QoS */
|
||||
/* Transaction Control (MXI) */
|
||||
mxi = (struct rcar_mxi *)MXI_BASE;
|
||||
writel(0x00000013, &mxi->mxrtcr);
|
||||
writel(0x00000013, &mxi->mxwtcr);
|
||||
writel(0x00780080, &mxi->mxsaar0);
|
||||
writel(0x02000800, &mxi->mxsaar1);
|
||||
|
||||
/* QoS Control (MXI) */
|
||||
mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
|
||||
writel(0x0000000C, &mxi_qos->vspdu0);
|
||||
writel(0x0000000E, &mxi_qos->du0);
|
||||
|
||||
/* AXI -QoS */
|
||||
/* Transaction Control (MXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x0000214C, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002029, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x0000214C, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x0000214C, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (RT-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (MP-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002037, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002014, &axi_qos->qosctset0);
|
||||
writel(0x00000040, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002014, &axi_qos->qosctset0);
|
||||
writel(0x00000040, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00001FF0, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00002001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x0000206E, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (SYS-AXI256) */
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020EB, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020EB, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020EB, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020EB, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (CCI-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (Media-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020DC, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x000020AA, &axi_qos->qosthres0);
|
||||
writel(0x00002032, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020DC, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x000020AA, &axi_qos->qosthres0);
|
||||
writel(0x00002032, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00001FF0, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00002001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
|
||||
writel(0x00000003, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
|
||||
writel(0x00000003, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
|
||||
writel(0x00000003, &axi_qos->qosconf);
|
||||
writel(0x00002063, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
|
||||
writel(0x00000003, &axi_qos->qosconf);
|
||||
writel(0x00002063, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
}
|
12
board/renesas/alt/qos.h
Normal file
12
board/renesas/alt/qos.h
Normal file
@ -0,0 +1,12 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __QOS_H__
|
||||
#define __QOS_H__
|
||||
|
||||
void qos_init(void);
|
||||
|
||||
#endif
|
@ -10,4 +10,8 @@
|
||||
#
|
||||
obj-y += board.o
|
||||
obj-$(CONFIG_SUNXI_GMAC) += gmac.o
|
||||
obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o
|
||||
obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o
|
||||
obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o
|
||||
obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o
|
||||
obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user